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@ -36,7 +36,7 @@ |
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#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ |
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#endif |
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int zynq_info(Xilinx_desc *desc) |
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static int zynq_info(xilinx_desc *desc) |
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{ |
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return FPGA_SUCCESS; |
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} |
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@ -147,76 +147,57 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) |
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} |
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/* Loop can be huge - support CTRL + C */ |
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if (ctrlc()) |
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return 0; |
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return NULL; |
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} |
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return 0; |
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return NULL; |
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} |
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int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) |
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static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) |
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{ |
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unsigned long ts; /* Timestamp */ |
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u32 partialbit = 0; |
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u32 i, control, isr_status, status, swap, diff; |
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u32 *buf_start; |
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/* Detect if we are going working with partial or full bitstream */ |
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if (bsize != desc->size) { |
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printf("%s: Working with partial bitstream\n", __func__); |
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partialbit = 1; |
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} |
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unsigned long ts; |
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u32 isr_status; |
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buf_start = check_data((u8 *)buf, bsize, &swap); |
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if (!buf_start) |
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return FPGA_FAIL; |
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/* Check if data is postpone from start */ |
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diff = (u32)buf_start - (u32)buf; |
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if (diff) { |
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printf("%s: Bitstream is not validated yet (diff %x)\n", |
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__func__, diff); |
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return FPGA_FAIL; |
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} |
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/* Set up the transfer */ |
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writel((u32)srcbuf, &devcfg_base->dma_src_addr); |
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writel(dstbuf, &devcfg_base->dma_dst_addr); |
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writel(srclen, &devcfg_base->dma_src_len); |
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writel(dstlen, &devcfg_base->dma_dst_len); |
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if ((u32)buf < SZ_1M) { |
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printf("%s: Bitstream has to be placed up to 1MB (%x)\n", |
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__func__, (u32)buf); |
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return FPGA_FAIL; |
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} |
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isr_status = readl(&devcfg_base->int_sts); |
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if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { |
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u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); |
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/* Polling the PCAP_INIT status for Set */ |
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ts = get_timer(0); |
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while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { |
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if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { |
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debug("%s: Error: isr = 0x%08X\n", __func__, |
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isr_status); |
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debug("%s: Write count = 0x%08X\n", __func__, |
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readl(&devcfg_base->write_count)); |
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debug("%s: Read count = 0x%08X\n", __func__, |
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readl(&devcfg_base->read_count)); |
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/*
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* This might be dangerous but permits to flash if |
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* ARCH_DMA_MINALIGN is greater than header size |
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*/ |
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if (new_buf > buf_start) { |
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debug("%s: Aligned buffer is after buffer start\n", |
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__func__); |
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new_buf -= ARCH_DMA_MINALIGN; |
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return FPGA_FAIL; |
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} |
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if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { |
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printf("%s: Timeout wait for DMA to complete\n", |
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__func__); |
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return FPGA_FAIL; |
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} |
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isr_status = readl(&devcfg_base->int_sts); |
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} |
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printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, |
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(u32)buf_start, (u32)new_buf, swap); |
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for (i = 0; i < (bsize/4); i++) |
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new_buf[i] = load_word(&buf_start[i], swap); |
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swap = SWAP_DONE; |
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buf = new_buf; |
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} else if (swap != SWAP_DONE) { |
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/* For bitstream which are aligned */ |
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u32 *new_buf = (u32 *)buf; |
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debug("%s: DMA transfer is done\n", __func__); |
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printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, |
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swap); |
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/* Clear out the DMA status */ |
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writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); |
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for (i = 0; i < (bsize/4); i++) |
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new_buf[i] = load_word(&buf_start[i], swap); |
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return FPGA_SUCCESS; |
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} |
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swap = SWAP_DONE; |
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} |
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static int zynq_dma_xfer_init(u32 partialbit) |
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{ |
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u32 status, control, isr_status; |
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unsigned long ts; |
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/* Clear loopback bit */ |
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clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); |
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@ -298,6 +279,101 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) |
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writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); |
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} |
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return FPGA_SUCCESS; |
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} |
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static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) |
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{ |
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u32 *new_buf; |
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u32 i; |
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if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { |
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new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); |
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/*
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* This might be dangerous but permits to flash if |
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* ARCH_DMA_MINALIGN is greater than header size |
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*/ |
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if (new_buf > buf) { |
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debug("%s: Aligned buffer is after buffer start\n", |
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__func__); |
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new_buf -= ARCH_DMA_MINALIGN; |
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} |
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printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, |
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(u32)buf, (u32)new_buf, swap); |
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for (i = 0; i < (len/4); i++) |
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new_buf[i] = load_word(&buf[i], swap); |
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buf = new_buf; |
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} else if (swap != SWAP_DONE) { |
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/* For bitstream which are aligned */ |
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u32 *new_buf = (u32 *)buf; |
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printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, |
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swap); |
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for (i = 0; i < (len/4); i++) |
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new_buf[i] = load_word(&buf[i], swap); |
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} |
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return buf; |
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} |
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static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, |
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size_t bsize, u32 blocksize, u32 *swap, |
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u32 *partialbit) |
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{ |
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u32 *buf_start; |
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u32 diff; |
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/* Detect if we are going working with partial or full bitstream */ |
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if (bsize != desc->size) { |
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printf("%s: Working with partial bitstream\n", __func__); |
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*partialbit = 1; |
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} |
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buf_start = check_data((u8 *)buf, blocksize, swap); |
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if (!buf_start) |
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return FPGA_FAIL; |
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/* Check if data is postpone from start */ |
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diff = (u32)buf_start - (u32)buf; |
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if (diff) { |
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printf("%s: Bitstream is not validated yet (diff %x)\n", |
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__func__, diff); |
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return FPGA_FAIL; |
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} |
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if ((u32)buf < SZ_1M) { |
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printf("%s: Bitstream has to be placed up to 1MB (%x)\n", |
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__func__, (u32)buf); |
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return FPGA_FAIL; |
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} |
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if (zynq_dma_xfer_init(*partialbit)) |
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return FPGA_FAIL; |
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return 0; |
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} |
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static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) |
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{ |
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unsigned long ts; /* Timestamp */ |
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u32 partialbit = 0; |
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u32 isr_status, swap; |
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/*
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* send bsize inplace of blocksize as it was not a bitstream |
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* in chunks |
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*/ |
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if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, |
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&partialbit)) |
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return FPGA_FAIL; |
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buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); |
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debug("%s: Source = 0x%08X\n", __func__, (u32)buf); |
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debug("%s: Size = %zu\n", __func__, bsize); |
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@ -305,37 +381,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) |
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flush_dcache_range((u32)buf, (u32)buf + |
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roundup(bsize, ARCH_DMA_MINALIGN)); |
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/* Set up the transfer */ |
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writel((u32)buf | 1, &devcfg_base->dma_src_addr); |
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writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); |
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writel(bsize >> 2, &devcfg_base->dma_src_len); |
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writel(0, &devcfg_base->dma_dst_len); |
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if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) |
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return FPGA_FAIL; |
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isr_status = readl(&devcfg_base->int_sts); |
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/* Polling the PCAP_INIT status for Set */ |
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ts = get_timer(0); |
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while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { |
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if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { |
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debug("%s: Error: isr = 0x%08X\n", __func__, |
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isr_status); |
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debug("%s: Write count = 0x%08X\n", __func__, |
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readl(&devcfg_base->write_count)); |
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debug("%s: Read count = 0x%08X\n", __func__, |
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readl(&devcfg_base->read_count)); |
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return FPGA_FAIL; |
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} |
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if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { |
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printf("%s: Timeout wait for DMA to complete\n", |
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__func__); |
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return FPGA_FAIL; |
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} |
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isr_status = readl(&devcfg_base->int_sts); |
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} |
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debug("%s: DMA transfer is done\n", __func__); |
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/* Check FPGA configuration completion */ |
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ts = get_timer(0); |
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while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { |
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@ -349,16 +398,19 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) |
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debug("%s: FPGA config done\n", __func__); |
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/* Clear out the DMA status */ |
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writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); |
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if (!partialbit) |
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zynq_slcr_devcfg_enable(); |
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return FPGA_SUCCESS; |
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} |
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int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) |
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static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
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{ |
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return FPGA_FAIL; |
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} |
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struct xilinx_fpga_op zynq_op = { |
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.load = zynq_load, |
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.dump = zynq_dump, |
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.info = zynq_info, |
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}; |
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Tom Rini
11 years ago