LS1043A, LS1046A, LS1088A, LS2088A. Switch to driver model for SATA on LS1021A and LS1043A. Add support for LS1012AFRWY rev C board. Enable SMMU for LS1043A. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJbrkHRAAoJEO1FWZTaC520r3UQAIBntTglI1QK7YizVxZ1x9DL 42oSEIwkuN0wbndR7Jzx4EPPFJ8yX4v3stoxC3qS5DQ9kHMzuqRQcIDYbcn5Qy7Z vd0mBUmpkRjr988pSaSHVQ8kPasncb545fCUumrXrCmhuG5Ea2Itw1zLdsTf7X5n 39KxFUOAR63BDCT0ZlR4VyMo01GxxHWCzRQH/rOWVzOcJsWF7R52hWIBBzVDxKPv HF9SYaAB0PTFgSjJx5wYQ4xPdHVUp+svtYSJE8JYzEr/BvOVtL2iEi4t2rk19CrX IaVMFydlv2iDgWdoSZFCCN/6lGDWSv1LWPDglWhLQhOYvrJOjZfgzzeAGU7wqoz4 JVjSLf6dHeOma55dbP/epDmyDFqWIfNOQ3uP4RM57xJ0PXQuT7ACVJctr6kHVTGL 1ZZxPdKSSf9lvtzoogPTTYRD5Ry7ud3sYZ0v3OHN1sbVcaHaVoHPeXeSz1sLg3Q+ zhUo1lXx4FcTz9R1fafdcqqAk/YGMZ7sBE+uYJPgExnApxrZID9IiOdGIBxo8jiK ozLmaCIDqRyu/qhQW9WMri1tvYdKwq/739gBvvcIcrLR5RzfNUdwWjhtBokPQQnS WZNqd3/0N8ZFGz7V0GOxCDnAo4nwQeZVFGMtTpoCtjPvr6DWBHsEUlQHTT3dQKz/ TXygMYUYGA+/vux0Dt4I =XRFI -----END PGP SIGNATURE----- Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A. Switch to driver model for SATA on LS1021A and LS1043A. Add support for LS1012AFRWY rev C board. Enable SMMU for LS1043A.lime2-spi
Tom Rini
6 years ago
commit
27f622d568
@ -1,41 +0,0 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/immap_ls102xa.h> |
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#include <ahci.h> |
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#include <scsi.h> |
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/* port register default value */ |
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#define AHCI_PORT_PHY_1_CFG 0xa003fffe |
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#define AHCI_PORT_PHY_2_CFG 0x28183414 |
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#define AHCI_PORT_PHY_3_CFG 0x0e080e06 |
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#define AHCI_PORT_PHY_4_CFG 0x064a080b |
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#define AHCI_PORT_PHY_5_CFG 0x2aa86470 |
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#define AHCI_PORT_TRANS_CFG 0x08000029 |
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#define SATA_ECC_REG_ADDR 0x20220520 |
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#define SATA_ECC_DISABLE 0x00020000 |
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int ls1021a_sata_init(void) |
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{ |
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struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; |
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 |
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out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); |
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#endif |
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out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); |
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out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); |
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out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); |
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out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); |
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out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); |
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out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); |
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ahci_init((void __iomem *)AHCI_BASE_ADDR); |
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scsi_scan(false); |
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return 0; |
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} |
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@ -0,0 +1,90 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP |
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*/ |
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#include <common.h> |
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#include <asm/arch-fsl-layerscape/immap_lsch2.h> |
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#include <asm/arch-fsl-layerscape/fsl_icid.h> |
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#include <asm/arch-fsl-layerscape/fsl_portals.h> |
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#include <fsl_sec.h> |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), |
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}; |
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#endif |
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struct icid_id_table icid_tbl[] = { |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START), |
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SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), |
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#endif |
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SET_SDHC_ICID(FSL_SDHC_STREAM_ID), |
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SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), |
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SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), |
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SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID), |
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SET_SATA_ICID("fsl,ls1043a-ahci", FSL_SATA_STREAM_ID), |
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SET_QDMA_ICID("fsl,ls1043a-qdma", FSL_QDMA_STREAM_ID), |
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SET_EDMA_ICID(FSL_EDMA_STREAM_ID), |
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SET_ETR_ICID(FSL_ETR_STREAM_ID), |
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SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), |
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SET_QE_ICID(FSL_QE_STREAM_ID), |
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#ifdef CONFIG_FSL_CAAM |
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SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2), |
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SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3), |
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SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4), |
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SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5), |
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SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6), |
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SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7), |
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SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8), |
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SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9), |
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SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10), |
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SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11), |
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SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12), |
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#endif |
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}; |
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int icid_tbl_sz = ARRAY_SIZE(icid_tbl); |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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struct fman_icid_id_table fman_icid_tbl[] = { |
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/* port id, icid */ |
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SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END), |
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SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END), |
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}; |
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int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl); |
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#endif |
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@ -1,10 +0,0 @@ |
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/* SPDX-License-Identifier: GPL-2.0+ */ |
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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*/ |
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#ifndef __FSL_SATA_H_ |
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#define __FSL_SATA_H_ |
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int ls1021a_sata_init(void); |
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#endif |
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@ -0,0 +1,12 @@ |
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# |
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# QUICC Engine Drivers |
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# |
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config U_QE |
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bool "Enable support for U QUICC Engine" |
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default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \ |
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|| (TARGET_T1024QDS) \ |
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|| (TARGET_T1024RDB) \ |
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|| (TARGET_T1040QDS && !NOBQFMAN) \ |
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|| (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT) |
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help |
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Choose this option to add support for U QUICC Engine. |
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