@ -295,6 +295,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
int enabled , r , inbound = 0 ;
u16 ltssm ;
u8 temp8 , pcie_cap ;
int pcie_cap_pos ;
int pci_dcr ;
int pci_dsr ;
int pci_lsr ;
# if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
int pci_lcr ;
# endif
volatile ccsr_fsl_pci_t * pci = ( ccsr_fsl_pci_t * ) cfg_addr ;
struct pci_region * reg = hose - > regions + hose - > region_count ;
pci_dev_t dev = PCI_BDF ( hose - > first_busno , 0 , 0 ) ;
@ -367,7 +376,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
hose - > region_count + + ;
/* see if we are a PCIe or PCI controller */
pci_hose_read_config_byte ( hose , dev , FSL_PCIE_CAP_ID , & pcie_cap ) ;
pcie_cap_pos = pci_hose_find_capability ( hose , dev , PCI_CAP_ID_EXP ) ;
pci_dcr = pcie_cap_pos + 0x08 ;
pci_dsr = pcie_cap_pos + 0x0a ;
pci_lsr = pcie_cap_pos + 0x12 ;
pci_hose_read_config_byte ( hose , dev , pcie_cap_pos , & pcie_cap ) ;
# ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */
@ -406,15 +420,16 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
* - Master PERR ( pci )
* - ICCA ( PCIe )
*/
pci_hose_read_config_dword ( hose , dev , PCI_DCR , & temp32 ) ;
pci_hose_read_config_dword ( hose , dev , pci_dcr , & temp32 ) ;
temp32 | = 0xf000e ; /* set URR, FER, NFER (but not CER) */
pci_hose_write_config_dword ( hose , dev , PCI_DCR , temp32 ) ;
pci_hose_write_config_dword ( hose , dev , pci_dcr , temp32 ) ;
# if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
pci_lcr = pcie_cap_pos + 0x10 ;
temp32 = 0 ;
pci_hose_read_config_dword ( hose , dev , PCI_LCR , & temp32 ) ;
pci_hose_read_config_dword ( hose , dev , pci_lcr , & temp32 ) ;
temp32 & = ~ 0x03 ; /* Disable ASPM */
pci_hose_write_config_dword ( hose , dev , PCI_LCR , temp32 ) ;
pci_hose_write_config_dword ( hose , dev , pci_lcr , temp32 ) ;
udelay ( 1 ) ;
# endif
if ( pcie_cap = = PCI_CAP_ID_EXP ) {
@ -494,7 +509,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
out_be32 ( & pci - > pme_msg_int_en , 0xffffffff ) ;
/* Print the negotiated PCIe link width */
pci_hose_read_config_word ( hose , dev , PCI_LSR , & temp16 ) ;
pci_hose_read_config_word ( hose , dev , pci_lsr , & temp16 ) ;
printf ( " x%d, regs @ 0x%lx \n " , ( temp16 & 0x3f0 ) > > 4 ,
pci_info - > regs ) ;
@ -541,9 +556,9 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
out_be32 ( & pci - > pme_msg_det , 0xffffffff ) ;
out_be32 ( & pci - > pedr , 0xffffffff ) ;
pci_hose_read_config_word ( hose , dev , PCI_DSR , & temp16 ) ;
pci_hose_read_config_word ( hose , dev , pci_dsr , & temp16 ) ;
if ( temp16 ) {
pci_hose_write_config_word ( hose , dev , PCI_DSR , 0xffff ) ;
pci_hose_write_config_word ( hose , dev , pci_dsr , 0xffff ) ;
}
pci_hose_read_config_word ( hose , dev , PCI_SEC_STATUS , & temp16 ) ;
@ -554,10 +569,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
int fsl_is_pci_agent ( struct pci_controller * hose )
{
int pcie_cap_pos ;
u8 pcie_cap ;
pci_dev_t dev = PCI_BDF ( hose - > first_busno , 0 , 0 ) ;
pci_hose_read_config_byte ( hose , dev , FSL_PCIE_CAP_ID , & pcie_cap ) ;
pcie_cap_pos = pci_hose_find_capability ( hose , dev , PCI_CAP_ID_EXP ) ;
pci_hose_read_config_byte ( hose , dev , pcie_cap_pos , & pcie_cap ) ;
if ( pcie_cap = = PCI_CAP_ID_EXP ) {
u8 header_type ;
@ -582,6 +599,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
volatile ccsr_fsl_pci_t * pci ;
struct pci_region * r ;
pci_dev_t dev = PCI_BDF ( busno , 0 , 0 ) ;
int pcie_cap_pos ;
u8 pcie_cap ;
pci = ( ccsr_fsl_pci_t * ) pci_info - > regs ;
@ -631,11 +649,11 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
# endif
}
pci_hose_read_config_byte ( hose , dev , FSL_PCIE_CAP_ID , & pcie_cap ) ;
pcie_cap_pos = pci_hose_find_capability ( hose , dev , PCI_CAP_ID_EXP ) ;
pci_hose_read_config_byte ( hose , dev , pcie_cap_pos , & pcie_cap ) ;
printf ( " PCI%s%x: Bus %02x - %02x \n " , pcie_cap = = PCI_CAP_ID_EXP ?
" e " : " " , pci_info - > pci_num ,
hose - > first_busno , hose - > last_busno ) ;
return ( hose - > last_busno + 1 ) ;
}
@ -643,13 +661,15 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
void fsl_pci_config_unlock ( struct pci_controller * hose )
{
pci_dev_t dev = PCI_BDF ( hose - > first_busno , 0 , 0 ) ;
int pcie_cap_pos ;
u8 pcie_cap ;
u16 pbfr ;
if ( ! fsl_is_pci_agent ( hose ) )
return ;
pci_hose_read_config_byte ( hose , dev , FSL_PCIE_CAP_ID , & pcie_cap ) ;
pcie_cap_pos = pci_hose_find_capability ( hose , dev , PCI_CAP_ID_EXP ) ;
pci_hose_read_config_byte ( hose , dev , pcie_cap_pos , & pcie_cap ) ;
if ( pcie_cap ! = 0x0 ) {
/* PCIe - set CFG_READY bit of Configuration Ready Register */
pci_hose_write_config_byte ( hose , dev , FSL_PCIE_CFG_RDY , 0x1 ) ;