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ARM: omap3_logic: Add NOR Flash Support for SOM-LV

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The DM37 and OMAP35 SOM-LV SOM-LV products both support a NOR
flash part connected to CS2 in addition to the NAND part on CS0.
This patch setups the GPMC timings for the MT28 NOR Flash and
enables the CFI-Flash driver now that the CFI stuff is in Kconfig

Signed-off-by: Adam Ford <aford173@gmail.com>
lime2-spi
Adam Ford 6 years ago committed by Tom Rini
parent e18333e501
commit 290097fe27
4 changed files with 70 additions and 7 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 49
      board/logicpd/omap3som/omap3logic.c
  2. 10
      configs/omap35_logic_somlv_defconfig
  3. 11
      configs/omap3_logic_somlv_defconfig
  4. 7
      include/configs/omap3_logic.h

49
board/logicpd/omap3som/omap3logic.c
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@ -40,6 +40,22 @@
DECLARE_GLOBAL_DATA_PTR;
#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
/* This is only needed until SPL gets OF support */
#ifdef CONFIG_SPL_BUILD
static const struct ns16550_platdata omap3logic_serial = {
@ -220,6 +236,28 @@ int misc_init_r(void)
return 0;
}
#if defined(CONFIG_FLASH_CFI_DRIVER)
static const u32 gpmc_dm37_c2nor_config[] = {
LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
};
static const u32 gpmc_omap35_c2nor_config[] = {
LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
};
#endif
/*
* Routine: board_init
* Description: Early hardware init.
@ -230,7 +268,16 @@ int board_init(void)
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_FLASH_CFI_DRIVER)
if (get_cpu_family() == CPU_OMAP36XX) {
/* Enable CS2 for NOR Flash */
enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
0x10000000, GPMC_SIZE_64M);
} else {
enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
0x10000000, GPMC_SIZE_64M);
}
#endif
return 0;
}

10
configs/omap35_logic_somlv_defconfig
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@ -24,8 +24,8 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
@ -39,6 +39,12 @@ CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y

11
configs/omap3_logic_somlv_defconfig
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@ -20,12 +20,11 @@ CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
# CONFIG_CMD_EEPROM is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
@ -40,6 +39,12 @@ CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP36XX_PINS=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y

7
include/configs/omap3_logic.h
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@ -183,9 +183,14 @@
/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#define CONFIG_SYS_FLASH_BASE 0x10000000
#endif
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE 0x4000000
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE

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