This board has not compiled for me for quite some time due to size constraints, remove. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>master
Tom Rini
9 years ago
committed by
Stefan Roese
parent
bb5553c618
commit
29155e7352
@ -1,16 +0,0 @@ |
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if TARGET_OCOTEA |
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|
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config SYS_BOARD |
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default "ocotea" |
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|
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config SYS_VENDOR |
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default "amcc" |
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|
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config SYS_CONFIG_NAME |
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default "ocotea" |
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|
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config DISPLAY_BOARDINFO |
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bool |
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default y |
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|
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endif |
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@ -1,6 +0,0 @@ |
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OCOTEA BOARD |
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M: Stefan Roese <sr@denx.de> |
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S: Maintained |
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F: board/amcc/ocotea/ |
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F: include/configs/ocotea.h |
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F: configs/ocotea_defconfig |
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@ -1,9 +0,0 @@ |
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#
|
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# (C) Copyright 2002-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = ocotea.o flash.o
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extra-y += init.o
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@ -1,73 +0,0 @@ |
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AMCC Ocotea Board |
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|
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Last Update: March 2, 2004 |
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======================================================================= |
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|
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This file contains some handy info regarding U-Boot and the AMCC |
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Ocotea 440gx evaluation board. See the README.ppc440 for additional |
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information. |
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|
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|
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SWITCH SETTINGS & JUMPERS |
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========================== |
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|
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Here's what I've been using successfully. If you feel inclined to |
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change things ... please read the docs! |
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|
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DIPSW U46 U80 |
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------------------------ |
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SW 1 off off |
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SW 2 on off |
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SW 3 off off |
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SW 4 off off |
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SW 5 off off |
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SW 6 on on |
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SW 7 on off |
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SW 8 on off |
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|
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J41: strapped |
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J42: open |
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|
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All others are factory default. |
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|
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|
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I2C Information |
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===================== |
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|
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See README.ebony for information. |
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|
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PCI |
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=========================== |
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|
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Untested at the time of writing. |
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|
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PPC440GX Ethernet EMACs |
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=========================== |
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|
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All EMAC ports have been tested and are known to work |
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with EPS Group 4. |
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|
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Special note about the Cicada CIS8201: |
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The CIS8201 Gigabit PHY comes up in GMII mode by default. |
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One must hit an extended register to allow use of RGMII mode. |
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This has been done in the 440gx_enet.c file with a #ifdef/endif |
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pair. |
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|
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AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. |
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The addresses contained in the config header file are from my particular |
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board and you _*should*_ change them to reflect your board either in the |
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config file and/or in your environment variables. I found the addresses on |
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labels on the bottom side of the board. |
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|
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|
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BDI2k or JTAG Debugging |
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=========================== |
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|
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For ease of debugging you can swap the small boot flash and external SRAM |
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by changing U46:3 to on. You can then use the sram as your boot flash by |
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loading the sram via the jtag debugger. |
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|
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|
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Regards, |
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--Travis |
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<tsawyer@sandburst.com> |
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@ -1,99 +0,0 @@ |
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------------------------------------------ |
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Installation of U-Boot using PIBS firmware |
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------------------------------------------ |
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|
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This document describes how to install U-Boot on the Ocotea PPC440GX |
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Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the |
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soldered FLASH. After this you should be able to switch between PIBS and |
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U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before |
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continuing. |
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|
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Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu |
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program. See the hints for configuring cu above. Make sure you can |
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communicate with the PIBS firmware: reset the board and hit ENTER a couple of |
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times until you see the PIBS prompt (PIBS $). Then proceed as follows: |
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|
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|
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Read MAC Addresses from PIBS |
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---------------------------- |
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|
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To read the configured MAC addresses available on your Ocotea board please use |
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the following commands: |
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|
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PIBS $ echo $hwdaddr0 |
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000173017FE3 |
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PIBS $ echo $hwdaddr1 |
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000173017FE4 |
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PIBS $ echo $hwdaddr2 |
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000173017FE1 |
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PIBS $ echo $hwdaddr3 |
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000173017FE2 |
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|
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In U-Boot this is stored in the following environment variables: |
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|
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* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3) |
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* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4) |
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* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1) |
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* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2) |
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|
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|
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Configure the network interface (ent0 == emac0) |
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----------------------------------------------- |
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|
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To download the U-Boot image we need to configure the ethernet interface with |
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the following commands: |
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|
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PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up |
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PIBS $ set ipdstaddr0=192.168.1.1 |
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status: writing PIBS variable value to FLASH |
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PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin |
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status: writing PIBS variable value to FLASH |
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|
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Please insert correct parameters for your configuration (ip-addresses and |
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file-location). |
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|
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|
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Program U-Boot into soldered User-FLASH |
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--------------------------------------- |
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|
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Please make sure to use a newer version of U-Boot (at least 1.1.3), since |
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older versions don't support running from user-FLASH. |
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|
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To program U-Boot into the soldered user-FLASH use the following command: |
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PIBS $ storefile bin eth 0xffbc0000 |
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This commands loads the file vis ethernet into ram and copies it into the |
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user-FLASH. |
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|
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|
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Switch to U-Boot |
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---------------- |
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|
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Now you can turn your board off and switch SW1 (U46) to on (= closed). After |
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powering the board you should see the following message: |
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|
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U-Boot 1.1.3 (Apr 5 2005 - 22:59:57) |
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|
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AMCC PowerPC 440 GX Rev. C |
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Board: AMCC 440GX Evaluation Board |
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VCO: 1066 MHz |
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CPU: 533 MHz |
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PLB: 152 MHz |
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OPB: 76 MHz |
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EPB: 76 MHz |
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I2C: ready |
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DRAM: 256 MB |
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FLASH: 5 MB |
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PCI: Bus Dev VenId DevId Class Int |
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In: serial |
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Out: serial |
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Err: serial |
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KGDB: kgdb ready |
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ready |
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Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3 |
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BEDBUG:ready |
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=> |
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April 06 2005, Stefan Roese <sr@denx.de> |
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@ -1,20 +0,0 @@ |
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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#
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# AMCC 440GX Reference Platform (Ocotea) board
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#
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1) |
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PLATFORM_CPPFLAGS += -DDEBUG
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endif |
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ifeq ($(dbcr),1) |
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif |
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@ -1,134 +0,0 @@ |
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/*
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* (C) Copyright 2004-2005 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2002 Jun Gu <jung@artesyncp.com> |
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* Add support for Am29F016D and dynamic switch setting. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* Modified 4/5/2001 |
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* Wait for completion of each sector erase command issued |
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* 4/5/2001 |
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* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com |
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*/ |
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#include <common.h> |
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#include <asm/ppc4xx.h> |
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#include <asm/processor.h> |
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#undef DEBUG |
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#ifdef DEBUG |
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#define DEBUGF(x...) printf(x) |
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#else |
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#define DEBUGF(x...) |
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#endif /* DEBUG */ |
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#define BOOT_SMALL_FLASH 0x40 /* 01000000 */ |
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#define FLASH_ONBD_N 2 /* 00000010 */ |
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#define FLASH_SRAM_SEL 1 /* 00000001 */ |
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#define FLASH_ONBD_N 2 /* 00000010 */ |
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#define FLASH_SRAM_SEL 1 /* 00000001 */ |
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#define BOOT_SMALL_FLASH_VAL 4 |
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#define FLASH_ONBD_N_VAL 2 |
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#define FLASH_SRAM_SEL_VAL 1 |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { |
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{0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ |
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{0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ |
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{0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ |
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{0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ |
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{0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ |
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{0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ |
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{0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ |
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{0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ |
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}; |
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/*
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* include common flash code (for amcc boards) |
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*/ |
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#include "../common/flash.c" |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size(vu_long * addr, flash_info_t * info); |
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static int write_word(flash_info_t * info, ulong dest, ulong data); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init(void) |
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{ |
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unsigned long total_b = 0; |
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unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; |
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unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; |
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unsigned char switch_status; |
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unsigned short index = 0; |
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int i; |
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/* read FPGA base register FPGA_REG0 */ |
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switch_status = *fpga_base; |
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/* check the bitmap of switch status */ |
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if (switch_status & BOOT_SMALL_FLASH) { |
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index += BOOT_SMALL_FLASH_VAL; |
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} |
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if (switch_status & FLASH_ONBD_N) { |
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index += FLASH_ONBD_N_VAL; |
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} |
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if (switch_status & FLASH_SRAM_SEL) { |
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index += FLASH_SRAM_SEL_VAL; |
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} |
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DEBUGF("\n"); |
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DEBUGF("FLASH: Index: %d\n", index); |
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/* Init: no FLASHes known */ |
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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flash_info[i].sector_count = -1; |
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flash_info[i].size = 0; |
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/* check whether the address is 0 */ |
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if (flash_addr_table[index][i] == 0) { |
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continue; |
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} |
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/* call flash_get_size() to initialize sector address */ |
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size_b[i] = |
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flash_get_size((vu_long *) flash_addr_table[index][i], |
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&flash_info[i]); |
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flash_info[i].size = size_b[i]; |
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if (flash_info[i].flash_id == FLASH_UNKNOWN) { |
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printf |
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("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", |
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i, size_b[i], size_b[i] << 20); |
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flash_info[i].sector_count = -1; |
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flash_info[i].size = 0; |
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} |
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|
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/* Monitor protection ON by default */ |
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, |
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CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, |
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&flash_info[i]); |
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#ifdef CONFIG_ENV_IS_IN_FLASH |
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
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&flash_info[i]); |
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(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, |
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
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&flash_info[i]); |
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#endif |
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total_b += flash_info[i].size; |
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} |
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return total_b; |
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} |
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@ -1,42 +0,0 @@ |
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/* |
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <ppc_asm.tmpl> |
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#include <config.h> |
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#include <asm/mmu.h> |
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#include <asm/ppc4xx.h> |
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|
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/************************************************************************** |
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* TLB TABLE |
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* |
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* This table is used by the cpu boot code to setup the initial tlb |
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* entries. Rather than make broad assumptions in the cpu source tree, |
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* this table lets each board set things up however they like. |
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* |
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* Pointer to the table is returned in r1 |
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* |
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*************************************************************************/ |
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|
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.section .bootpg,"ax" |
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.globl tlbtab
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|
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tlbtab: |
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tlbtab_start |
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|
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tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
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|
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/* |
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* TLB entries for SDRAM are not needed on this platform. |
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* They are dynamically generated in the SPD DDR(2) detection |
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* routine. |
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*/ |
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|
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) |
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tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) |
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tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) |
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) |
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) |
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tlbtab_end |
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@ -1,387 +0,0 @@ |
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/*
|
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* Copyright (C) 2004 PaulReynolds@lhsolutions.com |
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* |
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* (C) Copyright 2005 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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|
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#include <common.h> |
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#include "ocotea.h" |
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#include <asm/processor.h> |
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#include <spd_sdram.h> |
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#include <asm/ppc4xx-emac.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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#define BOOT_SMALL_FLASH 32 /* 00100000 */ |
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#define FLASH_ONBD_N 2 /* 00000010 */ |
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#define FLASH_SRAM_SEL 1 /* 00000001 */ |
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|
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long int fixed_sdram (void); |
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void fpga_init (void); |
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|
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int board_early_init_f (void) |
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{ |
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unsigned long mfr; |
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unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE; |
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unsigned char switch_status; |
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unsigned long cs0_base; |
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unsigned long cs0_size; |
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unsigned long cs0_twt; |
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unsigned long cs2_base; |
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unsigned long cs2_size; |
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unsigned long cs2_twt; |
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|
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/*-------------------------------------------------------------------------+
|
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| Initialize EBC CONFIG |
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+-------------------------------------------------------------------------*/ |
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mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | |
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EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32); |
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|
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/*-------------------------------------------------------------------------+
|
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| FPGA. Initialize bank 7 with default values. |
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+-------------------------------------------------------------------------*/ |
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mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| |
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EBC_BXAP_BCE_DISABLE| |
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
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EBC_BXAP_BEM_WRITEONLY| |
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EBC_BXAP_PEN_DISABLED); |
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mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| |
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EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
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|
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/* read FPGA base register FPGA_REG0 */ |
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switch_status = *fpga_base; |
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|
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if (switch_status & 0x40) { |
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cs0_base = 0xFFE00000; |
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cs0_size = EBC_BXCR_BS_2MB; |
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cs0_twt = 8; |
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cs2_base = 0xFF800000; |
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cs2_size = EBC_BXCR_BS_4MB; |
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cs2_twt = 10; |
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} else { |
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cs0_base = 0xFFC00000; |
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cs0_size = EBC_BXCR_BS_4MB; |
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cs0_twt = 10; |
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cs2_base = 0xFF800000; |
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cs2_size = EBC_BXCR_BS_2MB; |
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cs2_twt = 8; |
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} |
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|
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/*-------------------------------------------------------------------------+
|
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| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. |
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+-------------------------------------------------------------------------*/ |
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mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| |
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EBC_BXAP_BCE_DISABLE| |
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
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EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
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EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
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EBC_BXAP_BEM_WRITEONLY| |
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EBC_BXAP_PEN_DISABLED); |
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mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)| |
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cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
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|
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/*-------------------------------------------------------------------------+
|
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| 8KB NVRAM/RTC. Initialize bank 1 with default values. |
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+-------------------------------------------------------------------------*/ |
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mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| |
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EBC_BXAP_BCE_DISABLE| |
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EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
||||
EBC_BXAP_BEM_WRITEONLY| |
||||
EBC_BXAP_PEN_DISABLED); |
||||
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)| |
||||
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| 4 MB FLASH. Initialize bank 2 with default values. |
||||
+-------------------------------------------------------------------------*/ |
||||
mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| |
||||
EBC_BXAP_BCE_DISABLE| |
||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
||||
EBC_BXAP_BEM_WRITEONLY| |
||||
EBC_BXAP_PEN_DISABLED); |
||||
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)| |
||||
cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| FPGA. Initialize bank 7 with default values. |
||||
+-------------------------------------------------------------------------*/ |
||||
mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| |
||||
EBC_BXAP_BCE_DISABLE| |
||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| |
||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| |
||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| |
||||
EBC_BXAP_BEM_WRITEONLY| |
||||
EBC_BXAP_PEN_DISABLED); |
||||
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| |
||||
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc. |
||||
*-------------------------------------------------------------------*/ |
||||
/*
|
||||
* Because of the interrupt handling rework to handle 440GX interrupts |
||||
* with the common code, we needed to change names of the UIC registers. |
||||
* Here the new relationship: |
||||
* |
||||
* U-Boot name 440GX name |
||||
* ----------------------- |
||||
* UIC0 UICB0 |
||||
* UIC1 UIC0 |
||||
* UIC2 UIC1 |
||||
* UIC3 UIC2 |
||||
*/ |
||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */ |
||||
mtdcr (UIC1ER, 0x00000000); /* disable all */ |
||||
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */ |
||||
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */ |
||||
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */ |
||||
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */ |
||||
mtdcr (UIC2ER, 0x00000000); /* disable all */ |
||||
mtdcr (UIC2CR, 0x00000000); /* all non-critical */ |
||||
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */ |
||||
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */ |
||||
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */ |
||||
mtdcr (UIC3ER, 0x00000000); /* disable all */ |
||||
mtdcr (UIC3CR, 0x00000000); /* all non-critical */ |
||||
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */ |
||||
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */ |
||||
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */ |
||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */ |
||||
|
||||
mtdcr (UIC0SR, 0xfc000000); /* clear all */ |
||||
mtdcr (UIC0ER, 0x00000000); /* disable all */ |
||||
mtdcr (UIC0CR, 0x00000000); /* all non-critical */ |
||||
mtdcr (UIC0PR, 0xfc000000); /* */ |
||||
mtdcr (UIC0TR, 0x00000000); /* */ |
||||
mtdcr (UIC0VR, 0x00000001); /* */ |
||||
mfsdr (SDR0_MFR, mfr); |
||||
mfr &= ~SDR0_MFR_ECS_MASK; |
||||
/* mtsdr(SDR0_MFR, mfr); */ |
||||
fpga_init(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int checkboard (void) |
||||
{ |
||||
char buf[64]; |
||||
int i = getenv_f("serial#", buf, sizeof(buf)); |
||||
|
||||
printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board"); |
||||
if (i > 0) { |
||||
puts(", serial# "); |
||||
puts(buf); |
||||
} |
||||
putc ('\n'); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
phys_size_t initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
dram_size = spd_sdram (); |
||||
#else |
||||
dram_size = fixed_sdram (); |
||||
#endif |
||||
return dram_size; |
||||
} |
||||
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect. |
||||
* |
||||
* Assumes: 128 MB, non-ECC, non-registered |
||||
* PLB @ 133 MHz |
||||
* |
||||
************************************************************************/ |
||||
long int fixed_sdram (void) |
||||
{ |
||||
uint reg; |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup some default |
||||
*------------------------------------------------------------------*/ |
||||
mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ |
||||
mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ |
||||
mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ |
||||
mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ |
||||
mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup for board-specific specific mem |
||||
*------------------------------------------------------------------*/ |
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB |
||||
*/ |
||||
mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ |
||||
mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ |
||||
/* RA=10 RD=3 */ |
||||
mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ |
||||
mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ |
||||
mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ |
||||
udelay (400); /* Delay 200 usecs (min) */ |
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Enable the controller, then wait for DCEN to complete |
||||
*------------------------------------------------------------------*/ |
||||
mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ |
||||
for (;;) { |
||||
mfsdram (SDRAM0_MCSTS, reg); |
||||
if (reg & 0x80000000) |
||||
break; |
||||
} |
||||
|
||||
return (128 * 1024 * 1024); /* 128 MB */ |
||||
} |
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */ |
||||
|
||||
void fpga_init(void) |
||||
{ |
||||
unsigned long group; |
||||
unsigned long sdr0_pfc0; |
||||
unsigned long sdr0_pfc1; |
||||
unsigned long sdr0_cust0; |
||||
unsigned long pvr; |
||||
|
||||
mfsdr (SDR0_PFC0, sdr0_pfc0); |
||||
mfsdr (SDR0_PFC1, sdr0_pfc1); |
||||
group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); |
||||
pvr = get_pvr (); |
||||
|
||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE; |
||||
if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) { |
||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE; |
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; |
||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | |
||||
FPGA_REG2_EXT_INTFACE_ENABLE); |
||||
mtsdr (SDR0_PFC0, sdr0_pfc0); |
||||
mtsdr (SDR0_PFC1, sdr0_pfc1); |
||||
} else { |
||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; |
||||
switch (group) |
||||
{ |
||||
case 0: |
||||
case 1: |
||||
case 2: |
||||
/* CPU trace A */ |
||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | |
||||
FPGA_REG2_EXT_INTFACE_ENABLE); |
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; |
||||
mtsdr (SDR0_PFC0, sdr0_pfc0); |
||||
mtsdr (SDR0_PFC1, sdr0_pfc1); |
||||
break; |
||||
case 3: |
||||
case 4: |
||||
case 5: |
||||
case 6: |
||||
/* CPU trace B - Over EBMI */ |
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; |
||||
mtsdr (SDR0_PFC0, sdr0_pfc0); |
||||
mtsdr (SDR0_PFC1, sdr0_pfc1); |
||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | |
||||
FPGA_REG2_EXT_INTFACE_DISABLE); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
/* Initialize the ethernet specific functions in the fpga */ |
||||
mfsdr(SDR0_PFC1, sdr0_pfc1); |
||||
mfsdr(SDR0_CUST0, sdr0_cust0); |
||||
if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && |
||||
((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || |
||||
(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) |
||||
{ |
||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | |
||||
FPGA_REG3_ENET_GROUP7); |
||||
} |
||||
else |
||||
{ |
||||
if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | |
||||
FPGA_REG3_ENET_GROUP7); |
||||
} |
||||
else |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | |
||||
FPGA_REG3_ENET_GROUP8); |
||||
} |
||||
} |
||||
} |
||||
else |
||||
{ |
||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) | |
||||
FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); |
||||
} |
||||
else |
||||
{ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) | |
||||
FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1))); |
||||
} |
||||
} |
||||
out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 | |
||||
FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 | |
||||
FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS); |
||||
|
||||
/* reset the gigabyte phy if necessary */ |
||||
if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3) |
||||
{ |
||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1) |
||||
{ |
||||
out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE); |
||||
udelay(10000); |
||||
out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE); |
||||
} |
||||
else |
||||
{ |
||||
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE); |
||||
udelay(10000); |
||||
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE); |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* new Ocotea with Rev. F (pass 3) chips has SMII PHY reset |
||||
*/ |
||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) { |
||||
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE); |
||||
udelay(10000); |
||||
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE); |
||||
} |
||||
|
||||
/* Turn off the LED's */ |
||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) | |
||||
FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB | |
||||
FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB); |
||||
|
||||
return; |
||||
} |
||||
@ -1,125 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Board specific FPGA stuff ... */ |
||||
#define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00) |
||||
#define FPGA_REG0_SSCG_MASK 0x80 |
||||
#define FPGA_REG0_SSCG_DISABLE 0x00 |
||||
#define FPGA_REG0_SSCG_ENABLE 0x80 |
||||
#define FPGA_REG0_BOOT_MASK 0x40 |
||||
#define FPGA_REG0_BOOT_LARGE_FLASH 0x00 |
||||
#define FPGA_REG0_BOOT_SMALL_FLASH 0x40 |
||||
#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */ |
||||
#define FPGA_REG0_ARBITER_MASK 0x04 |
||||
#define FPGA_REG0_ARBITER_EXT 0x00 |
||||
#define FPGA_REG0_ARBITER_INT 0x04 |
||||
#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02 |
||||
#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 |
||||
#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 |
||||
#define FPGA_REG0_FLASH 0x01 |
||||
#define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01) |
||||
#define FPGA_REG1_9772_FSELFBX_MASK 0x80 |
||||
#define FPGA_REG1_9772_FSELFBX_6 0x00 |
||||
#define FPGA_REG1_9772_FSELFBX_10 0x80 |
||||
#define FPGA_REG1_9531_SX_MASK 0x60 |
||||
#define FPGA_REG1_9531_SX_33MHZ 0x00 |
||||
#define FPGA_REG1_9531_SX_100MHZ 0x20 |
||||
#define FPGA_REG1_9531_SX_66MHZ 0x40 |
||||
#define FPGA_REG1_9531_SX_133MHZ 0x60 |
||||
#define FPGA_REG1_9772_FSELBX_MASK 0x18 |
||||
#define FPGA_REG1_9772_FSELBX_4 0x00 |
||||
#define FPGA_REG1_9772_FSELBX_6 0x08 |
||||
#define FPGA_REG1_9772_FSELBX_8 0x10 |
||||
#define FPGA_REG1_9772_FSELBX_10 0x18 |
||||
#define FPGA_REG1_SOURCE_MASK 0x07 |
||||
#define FPGA_REG1_SOURCE_TC 0x00 |
||||
#define FPGA_REG1_SOURCE_66MHZ 0x01 |
||||
#define FPGA_REG1_SOURCE_50MHZ 0x02 |
||||
#define FPGA_REG1_SOURCE_33MHZ 0x03 |
||||
#define FPGA_REG1_SOURCE_25MHZ 0x04 |
||||
#define FPGA_REG1_SOURCE_SSDIV1 0x05 |
||||
#define FPGA_REG1_SOURCE_SSDIV2 0x06 |
||||
#define FPGA_REG1_SOURCE_SSDIV4 0x07 |
||||
#define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02) |
||||
#define FPGA_REG2_TC0 0x80 |
||||
#define FPGA_REG2_TC1 0x40 |
||||
#define FPGA_REG2_TC2 0x20 |
||||
#define FPGA_REG2_TC3 0x10 |
||||
#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/ |
||||
#define FPGA_REG2_EXT_INTFACE_MASK 0x04 |
||||
#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 |
||||
#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 |
||||
#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ |
||||
#define FPGA_REG2_DEFAULT_UART1_N 0x01 |
||||
#define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03) |
||||
#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ |
||||
#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ |
||||
#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ |
||||
#define FPGA_REG3_ENET_GROUP0 0x00 |
||||
#define FPGA_REG3_ENET_GROUP1 0x10 |
||||
#define FPGA_REG3_ENET_GROUP2 0x20 |
||||
#define FPGA_REG3_ENET_GROUP3 0x30 |
||||
#define FPGA_REG3_ENET_GROUP4 0x40 |
||||
#define FPGA_REG3_ENET_GROUP5 0x50 |
||||
#define FPGA_REG3_ENET_GROUP6 0x60 |
||||
#define FPGA_REG3_ENET_GROUP7 0x70 |
||||
#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/ |
||||
#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/ |
||||
#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/ |
||||
#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/ |
||||
#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/ |
||||
#define FPGA_REG3_STAT_MASK 0x0F |
||||
#define FPGA_REG3_STAT_LED8_ENAB 0x08 |
||||
#define FPGA_REG3_STAT_LED4_ENAB 0x04 |
||||
#define FPGA_REG3_STAT_LED2_ENAB 0x02 |
||||
#define FPGA_REG3_STAT_LED1_ENAB 0x01 |
||||
#define FPGA_REG3_STAT_LED8_DISAB 0x00 |
||||
#define FPGA_REG3_STAT_LED4_DISAB 0x00 |
||||
#define FPGA_REG3_STAT_LED2_DISAB 0x00 |
||||
#define FPGA_REG3_STAT_LED1_DISAB 0x00 |
||||
#define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04) |
||||
#define FPGA_REG4_GPHY_MODE10 0x80 |
||||
#define FPGA_REG4_GPHY_MODE100 0x40 |
||||
#define FPGA_REG4_GPHY_MODE1000 0x20 |
||||
#define FPGA_REG4_GPHY_FRC_DPLX 0x10 |
||||
#define FPGA_REG4_GPHY_ANEG_DIS 0x08 |
||||
#define FPGA_REG4_CONNECT_PHYS 0x04 |
||||
|
||||
|
||||
#define SDR0_CUST0_ENET3_MASK 0x00000080 |
||||
#define SDR0_CUST0_ENET3_COPPER 0x00000000 |
||||
#define SDR0_CUST0_ENET3_FIBER 0x00000080 |
||||
#define SDR0_CUST0_RGMII3_MASK 0x00000070 |
||||
#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) |
||||
#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) |
||||
#define SDR0_CUST0_RGMII3_DISAB 0x00000000 |
||||
#define SDR0_CUST0_RGMII3_RTBI 0x00000040 |
||||
#define SDR0_CUST0_RGMII3_RGMII 0x00000050 |
||||
#define SDR0_CUST0_RGMII3_TBI 0x00000060 |
||||
#define SDR0_CUST0_RGMII3_GMII 0x00000070 |
||||
#define SDR0_CUST0_ENET2_MASK 0x00000008 |
||||
#define SDR0_CUST0_ENET2_COPPER 0x00000000 |
||||
#define SDR0_CUST0_ENET2_FIBER 0x00000008 |
||||
#define SDR0_CUST0_RGMII2_MASK 0x00000007 |
||||
#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) |
||||
#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) |
||||
#define SDR0_CUST0_RGMII2_DISAB 0x00000000 |
||||
#define SDR0_CUST0_RGMII2_RTBI 0x00000004 |
||||
#define SDR0_CUST0_RGMII2_RGMII 0x00000005 |
||||
#define SDR0_CUST0_RGMII2_TBI 0x00000006 |
||||
#define SDR0_CUST0_RGMII2_GMII 0x00000007 |
||||
@ -1,3 +0,0 @@ |
||||
CONFIG_PPC=y |
||||
CONFIG_4xx=y |
||||
CONFIG_TARGET_OCOTEA=y |
||||
@ -1,194 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> |
||||
* |
||||
* (C) Copyright 2005 |
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/************************************************************************
|
||||
* 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com> |
||||
* Adapted to current Das U-Boot source |
||||
***********************************************************************/ |
||||
|
||||
|
||||
/************************************************************************
|
||||
* OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea) |
||||
***********************************************************************/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_OCOTEA 1 /* Board is ebony */ |
||||
#define CONFIG_440GX 1 /* Specifc GX support */ |
||||
#define CONFIG_440 1 /* ... PPC440 family */ |
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
||||
|
||||
/*
|
||||
* Include common defines/options for all AMCC eval boards |
||||
*/ |
||||
#define CONFIG_HOSTNAME ocotea |
||||
#include "amcc-common.h" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ |
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
||||
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ |
||||
|
||||
#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000) |
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM) |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
||||
#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment |
||||
*----------------------------------------------------------------------*/ |
||||
/*
|
||||
* Define here the location of the environment variables (FLASH or NVRAM). |
||||
* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only |
||||
* supported for backward compatibility. |
||||
*/ |
||||
#if 1 |
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
||||
#endif |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC |
||||
* |
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. |
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base |
||||
* address for the RTC registers is: |
||||
* |
||||
* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE |
||||
* |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ |
||||
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_NVRAM |
||||
#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
||||
#define CONFIG_ENV_ADDR \ |
||||
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) |
||||
#endif /* CONFIG_ENV_IS_IN_NVRAM */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ |
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 |
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2aaa |
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char |
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
||||
#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ |
||||
#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C |
||||
*----------------------------------------------------------------------*/ |
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
||||
|
||||
#define CONFIG_SYS_I2C_MULTI_EEPROMS |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
|
||||
/*
|
||||
* Default environment variables |
||||
*/ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
CONFIG_AMCC_DEF_ENV \
|
||||
CONFIG_AMCC_DEF_ENV_PPC \
|
||||
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
||||
"kernel_addr=fff00000\0" \
|
||||
"ramdisk_addr=fff10000\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
||||
#define CONFIG_PHY1_ADDR 2 |
||||
#define CONFIG_PHY2_ADDR 0x10 |
||||
#define CONFIG_PHY3_ADDR 0x18 |
||||
#define CONFIG_HAS_ETH0 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_HAS_ETH2 |
||||
#define CONFIG_HAS_ETH3 |
||||
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ |
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
||||
#define CONFIG_PHY_RESET_DELAY 1000 |
||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h |
||||
*/ |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_SDRAM |
||||
#define CONFIG_CMD_SNTP |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
/* General PCI */ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
||||
|
||||
/* Board-specific PCI */ |
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue