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@ -3,7 +3,7 @@ |
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* This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core |
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* DDR2 controller, specifically the 440EPx/GRx. |
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* |
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* (C) Copyright 2007 |
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* (C) Copyright 2007-2008 |
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* Larry Johnson, lrj@acm.org. |
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* |
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* Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... |
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@ -77,10 +77,10 @@ |
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* memory. |
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* |
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* If at some time this restriction doesn't apply anymore, just define |
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* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup |
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* CONFIG_4xx_DCACHE in the board config file and this code should setup |
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* everything correctly. |
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*/ |
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#if defined(CFG_ENABLE_SDRAM_CACHE) |
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#if defined(CONFIG_4xx_DCACHE) |
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#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ |
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#else |
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ |
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