PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>master
Timur Tabi
19 years ago
committed by
Kim Phillips
parent
183da6d9b4
commit
2ad6b513b3
@ -0,0 +1,48 @@ |
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#
|
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# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,33 @@ |
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#
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# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# MPC8349ITX
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#
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TEXT_BASE = 0xFEF00000
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ifneq ($(OBJTREE),$(SRCTREE)) |
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# We are building u-boot in a separate directory, use generated
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# .lds script from OBJTREE directory.
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LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
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endif |
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@ -0,0 +1,461 @@ |
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <i2c.h> |
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#include <spd.h> |
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#include <miiphy.h> |
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#ifdef CONFIG_PCI |
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#include <asm/mpc8349_pci.h> |
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#include <pci.h> |
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#endif |
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#ifdef CONFIG_SPD_EEPROM |
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#include <spd_sdram.h> |
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#else |
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#include <asm/mmu.h> |
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#endif |
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#ifndef CONFIG_SPD_EEPROM |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMRBAR; |
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u32 ddr_size; /* The size of RAM, in bytes */ |
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u32 ddr_size_log2 = 0; |
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for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { |
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if (ddr_size & 1) { |
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return -1; |
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} |
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ddr_size_log2++; |
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} |
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im->sysconf.ddrlaw[0].ar = |
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
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im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; |
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|
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/* Only one CS0 for DDR */ |
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im->ddr.csbnds[0].csbnds = 0x0000000f; |
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im->ddr.cs_config[0] = CFG_DDR_CONFIG; |
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|
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debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); |
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debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); |
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debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); |
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debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); |
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ |
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im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR; |
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im->ddr.sdram_mode = |
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(0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); |
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im->ddr.sdram_interval = |
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(0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << |
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SDRAM_INTERVAL_BSTOPRE_SHIFT); |
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im->ddr.sdram_clk_cntl = |
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DDR_SDRAM_CLK_CNTL_SS_EN | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; |
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udelay(200); |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); |
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debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); |
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debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode); |
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debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); |
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debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); |
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return CFG_DDR_SIZE; |
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} |
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#endif |
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#ifdef CONFIG_PCI |
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/*
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* Initialize PCI Devices, report devices found |
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*/ |
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#ifndef CONFIG_PCI_PNP |
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static struct pci_config_table pci_mpc83xxmitx_config_table[] = { |
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{ |
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PCI_ANY_ID, |
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PCI_ANY_ID, |
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PCI_ANY_ID, |
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PCI_ANY_ID, |
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0x0f, |
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PCI_ANY_ID, |
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pci_cfgfunc_config_device, |
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{ |
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PCI_ENET0_IOADDR, |
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PCI_ENET0_MEMADDR, |
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} |
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}, |
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{} |
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} |
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#endif |
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volatile static struct pci_controller hose[] = { |
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{ |
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#ifndef CONFIG_PCI_PNP |
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config_table:pci_mpc83xxmitx_config_table, |
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#endif |
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}, |
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{ |
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#ifndef CONFIG_PCI_PNP |
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config_table:pci_mpc83xxmitx_config_table, |
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#endif |
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} |
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}; |
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#endif /* CONFIG_PCI */ |
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/* If MPC8349E-mITX is soldered with SDRAM, then initialize it.
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*/ |
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void sdram_init(void) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; |
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volatile lbus83xx_t *lbc = &immap->lbus; |
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#if defined(CFG_BR2_PRELIM) \ |
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&& defined(CFG_OR2_PRELIM) \
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&& defined(CFG_LBLAWBAR2_PRELIM) \
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&& defined(CFG_LBLAWAR2_PRELIM) \
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&& !defined(CONFIG_COMPACT_FLASH) |
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uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; |
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puts("\n SDRAM on Local Bus: "); |
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print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c |
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*/ |
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/*setup mtrpt, lsrt and lbcr for LB bus */ |
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lbc->lbcr = CFG_LBC_LBCR; |
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lbc->mrtpr = CFG_LBC_MRTPR; |
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lbc->lsrt = CFG_LBC_LSRT; |
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asm("sync"); |
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/*
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* Configure the SDRAM controller Machine Mode register. |
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*/ |
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ |
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lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733; precharge all the banks */ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_2; /*0x48636733; auto refresh */ |
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asm("sync"); |
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*sdram_addr = 0xff; /*1 time*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*2 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*3 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*4 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*5 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*6 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*7 times*/ |
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udelay(100); |
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*sdram_addr = 0xff; /*8 times*/ |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation */ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation */ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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#else |
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puts("SDRAM on Local Bus is NOT available!\n"); |
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#ifdef CFG_BR2_PRELIM |
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lbc->bank[2].br = CFG_BR2_PRELIM; |
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lbc->bank[2].or = CFG_OR2_PRELIM; |
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#endif |
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#ifdef CFG_BR3_PRELIM |
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lbc->bank[3].br = CFG_BR3_PRELIM; |
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lbc->bank[3].or = CFG_OR3_PRELIM; |
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#endif |
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#endif |
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} |
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long int initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *) CFG_IMMRBAR; |
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u32 msize = 0; |
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#ifdef CONFIG_DDR_ECC |
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volatile ddr83xx_t *ddr = &im->ddr; |
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#endif |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
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#ifdef CONFIG_SPD_EEPROM |
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msize = spd_sdram(); |
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#else |
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msize = fixed_sdram(); |
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#endif |
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|
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#ifdef CONFIG_DDR_ECC |
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if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) |
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/* Unlike every other board, on the 83xx spd_sdram() returns
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megabytes instead of just bytes. That's why we need to |
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multiple by 1MB when calling ddr_enable_ecc(). */ |
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ddr_enable_ecc(msize * 1048576); |
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#endif |
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|
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/*
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* Initialize SDRAM if it is on local bus. |
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*/ |
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sdram_init(); |
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puts(" DDR RAM: "); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return msize * 1024 * 1024; |
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} |
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|
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int checkboard(void) |
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{ |
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#ifdef CONFIG_HARD_I2C |
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u8 i2c_data; |
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#endif |
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|
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puts("Board: Freescale MPC8349E-mITX"); |
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|
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#ifdef CONFIG_HARD_I2C |
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i2c_set_bus_num(I2C_BUS_2); |
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if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == |
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0) |
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printf(" %u.%u (PCF8475A)", (i2c_data & 0x02) >> 1, |
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i2c_data & 0x01); |
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else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) |
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== 0) |
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printf(" %u.%u (PCF8475)", (i2c_data & 0x02) >> 1, |
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i2c_data & 0x01); |
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else |
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printf(" ?.?"); |
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#endif |
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|
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puts("\n"); |
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|
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return 0; |
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} |
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|
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/**
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* Implement a work-around for a hardware problem with compact |
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* flash. |
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* |
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* Program the UPM if compact flash is enabled. |
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*/ |
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int misc_init_f(void) |
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{ |
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volatile u32 *vsc7385_cpuctrl; |
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|
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/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
|
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default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That |
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means it is 0 when the IRQ is not active. This makes the wire-AND |
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logic always assert IRQ7 to CPU even if there is no request from the |
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switch. Since the compact flash and the switch share the same IRQ, |
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the Linux kernel will think that the compact flash is requesting irq |
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and get stuck when it tries to clear the IRQ. Thus we need to set |
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the L2_IRQ0 and L2_IRQ1 to active low. |
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|
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The following code sets the L1_IRQ and L2_IRQ polarity to active low. |
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Without this code, compact flash will not work in Linux because |
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unlike U-Boot, Linux uses the IRQ, so this code is necessary if we |
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don't enable compact flash for U-Boot. |
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*/ |
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|
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vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); |
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*vsc7385_cpuctrl |= 0x0c; |
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|
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#ifdef CONFIG_COMPACT_FLASH |
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/* UPM Table Configuration Code */ |
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static uint UPMATable[] = { |
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0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00, |
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0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00, |
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0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, |
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 |
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}; |
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volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; |
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volatile lbus83xx_t *lbus = &immap->lbus; |
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|
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lbus->bank[3].br = CFG_BR3_PRELIM; |
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lbus->bank[3].or = CFG_OR3_PRELIM; |
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|
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/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
|
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GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 |
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*/ |
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lbus->mamr = 0x08404440; |
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|
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upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); |
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|
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puts("UPMA: Configured for compact flash\n"); |
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#endif |
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|
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return 0; |
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} |
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|
||||
/**
|
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* Make sure the EEPROM has the HRCW correctly programmed. |
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* Make sure the RTC is correctly programmed. |
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* |
||||
* The MPC8349E-mITX can be configured to load the HRCW from |
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* EEPROM instead of flash. This is controlled via jumpers |
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* LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all |
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* jumpered), but if they're set to 001 or 010, then the HRCW is |
||||
* read from the "I2C EEPROM". |
||||
* |
||||
* This function makes sure that the I2C EEPROM is programmed |
||||
* correctly. |
||||
*/ |
||||
int misc_init_r(void) |
||||
{ |
||||
int rc = 0; |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
|
||||
uchar orig_bus = i2c_get_bus_num();; |
||||
|
||||
#ifdef CFG_I2C_RTC_ADDR |
||||
char ds1339_data[17]; |
||||
#endif |
||||
|
||||
#ifdef CFG_I2C_EEPROM_ADDR |
||||
static u8 eeprom_data[] = /* HRCW data */ |
||||
{ |
||||
0xaa, 0x55, 0xaa, |
||||
0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, |
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0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, |
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}; |
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|
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u8 data[sizeof(eeprom_data)]; |
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|
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i2c_set_bus_num(I2C_BUS_1); |
||||
|
||||
if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { |
||||
if (memcmp(data, eeprom_data, sizeof(data)) != 0) { |
||||
if (i2c_write |
||||
(CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, |
||||
sizeof(eeprom_data)) != 0) { |
||||
puts("Failure writing the HRCW to EEPROM via I2C.\n"); |
||||
rc = 1; |
||||
} |
||||
} |
||||
} else { |
||||
puts("Failure reading the HRCW from EEPROM via I2C.\n"); |
||||
rc = 1; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CFG_I2C_RTC_ADDR |
||||
i2c_set_bus_num(I2C_BUS_2); |
||||
|
||||
if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) |
||||
== 0) { |
||||
|
||||
/* Work-around for MPC8349E-mITX bug #13601.
|
||||
If the RTC does not contain valid register values, the DS1339 |
||||
Linux driver will not work. |
||||
*/ |
||||
|
||||
/* Make sure status register bits 6-2 are zero */ |
||||
ds1339_data[0x0f] &= ~0x7c; |
||||
|
||||
/* Check for a valid day register value */ |
||||
ds1339_data[0x03] &= ~0xf8; |
||||
if (ds1339_data[0x03] == 0) { |
||||
ds1339_data[0x03] = 1; |
||||
} |
||||
|
||||
/* Check for a valid date register value */ |
||||
ds1339_data[0x04] &= ~0xc0; |
||||
if ((ds1339_data[0x04] == 0) || |
||||
((ds1339_data[0x04] & 0x0f) > 9) || |
||||
(ds1339_data[0x04] >= 0x32)) { |
||||
ds1339_data[0x04] = 1; |
||||
} |
||||
|
||||
/* Check for a valid month register value */ |
||||
ds1339_data[0x05] &= ~0x60; |
||||
|
||||
if ((ds1339_data[0x05] == 0) || |
||||
((ds1339_data[0x05] & 0x0f) > 9) || |
||||
((ds1339_data[0x05] >= 0x13) |
||||
&& (ds1339_data[0x05] <= 0x19))) { |
||||
ds1339_data[0x05] = 1; |
||||
} |
||||
|
||||
/* Enable Oscillator and rate select */ |
||||
ds1339_data[0x0e] = 0x1c; |
||||
|
||||
/* Work-around for MPC8349E-mITX bug #13330.
|
||||
Ensure that the RTC control register contains the value 0x1c. |
||||
This affects SATA performance. |
||||
*/ |
||||
|
||||
if (i2c_write |
||||
(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, |
||||
sizeof(ds1339_data))) { |
||||
puts("Failure writing to the RTC via I2C.\n"); |
||||
rc = 1; |
||||
} |
||||
} else { |
||||
puts("Failure reading from the RTC via I2C.\n"); |
||||
rc = 1; |
||||
} |
||||
#endif |
||||
|
||||
i2c_set_bus_num(orig_bus); |
||||
#endif |
||||
|
||||
return rc; |
||||
} |
||||
@ -0,0 +1,337 @@ |
||||
/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
#include <asm/mmu.h> |
||||
#include <asm/global_data.h> |
||||
#include <pci.h> |
||||
#include <asm/mpc8349_pci.h> |
||||
#include <i2c.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* System RAM mapped to PCI space */ |
||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE |
||||
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc8349itx_config_table[] = { |
||||
{ |
||||
PCI_ANY_ID, |
||||
PCI_ANY_ID, |
||||
PCI_ANY_ID, |
||||
PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, |
||||
PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, |
||||
{ |
||||
PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} |
||||
}, |
||||
{} |
||||
}; |
||||
#endif |
||||
|
||||
static struct pci_controller pci_hose[] = { |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc8349itx_config_table, |
||||
#endif |
||||
}, |
||||
{ |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table:pci_mpc8349itx_config_table, |
||||
#endif |
||||
} |
||||
}; |
||||
|
||||
/**************************************************************************
|
||||
* pci_init_board() |
||||
* |
||||
* NOTICE: PCI2 is not currently supported |
||||
* |
||||
*/ |
||||
void pci_init_board(void) |
||||
{ |
||||
volatile immap_t *immr; |
||||
volatile clk83xx_t *clk; |
||||
volatile law83xx_t *pci_law; |
||||
volatile pot83xx_t *pci_pot; |
||||
volatile pcictrl83xx_t *pci_ctrl; |
||||
volatile pciconf83xx_t *pci_conf; |
||||
u8 reg8; |
||||
u16 reg16; |
||||
u32 reg32; |
||||
u32 dev; |
||||
struct pci_controller *hose; |
||||
|
||||
immr = (immap_t *) CFG_IMMRBAR; |
||||
clk = (clk83xx_t *) & immr->clk; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
pci_pot = immr->ios.pot; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_conf = immr->pci_conf; |
||||
|
||||
hose = &pci_hose[0]; |
||||
|
||||
/*
|
||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
||||
*/ |
||||
|
||||
reg32 = clk->occr; |
||||
udelay(2000); |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
i2c_set_bus_num(I2C_BUS_2); |
||||
/* Read the PCI_M66EN jumper setting */ |
||||
if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || |
||||
(i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { |
||||
if (reg8 & I2C_8574_PCI66) |
||||
clk->occr = 0xff000000; /* 66 MHz PCI */ |
||||
else |
||||
clk->occr = 0xff600001; /* 33 MHz PCI */ |
||||
} else { |
||||
clk->occr = 0xff600001; /* 33 MHz PCI */ |
||||
} |
||||
#else |
||||
clk->occr = 0xff000000; /* 66 MHz PCI */ |
||||
#endif |
||||
|
||||
udelay(2000); |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal |
||||
*/ |
||||
pci_ctrl[0].gcr = 0; |
||||
udelay(2000); |
||||
pci_ctrl[0].gcr = 1; |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
pci_ctrl[1].gcr = 0; |
||||
udelay(2000); |
||||
pci_ctrl[1].gcr = 1; |
||||
#endif |
||||
|
||||
/* We need to wait at least a 1sec based on PCI specs */ |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < 1000; i++) |
||||
udelay(1000); |
||||
} |
||||
|
||||
/*
|
||||
* Configure PCI Local Access Windows |
||||
*/ |
||||
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; |
||||
|
||||
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
|
||||
/* PCI1 mem space - prefetch */ |
||||
pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[0].pocmr = |
||||
POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/* PCI1 IO space */ |
||||
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); |
||||
|
||||
/* PCI1 mmio - non-prefetch mem space */ |
||||
pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
|
||||
/* we need RAM mapped to PCI space for the devices to
|
||||
* access main memory */ |
||||
pci_ctrl[0].pitar1 = 0x0; |
||||
pci_ctrl[0].pibar1 = 0x0; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | |
||||
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); |
||||
|
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI1_MEM_BASE, |
||||
CFG_PCI1_MEM_PHYS, |
||||
CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI1_MMIO_BASE, |
||||
CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI1_IO_BASE, |
||||
CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose->regions + 3, |
||||
CONFIG_PCI_SYS_MEM_BUS, |
||||
CONFIG_PCI_SYS_MEM_PHYS, |
||||
gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose->region_count = 4; |
||||
|
||||
pci_setup_indirect(hose, |
||||
(CFG_IMMRBAR + 0x8300), (CFG_IMMRBAR + 0x8304)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write to Command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(hose->first_busno, 0, 0); |
||||
pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
#ifdef CONFIG_PCI_SCAN_SHOW |
||||
printf("PCI: Bus Dev VenId DevId Class Int\n"); |
||||
#endif |
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
hose = &pci_hose[1]; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
|
||||
/* PCI2 mem space - prefetch */ |
||||
pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[3].pocmr = |
||||
POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & |
||||
POCMR_CM_MASK); |
||||
|
||||
/* PCI2 IO space */ |
||||
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[4].pocmr = |
||||
POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); |
||||
|
||||
/* PCI2 mmio - non-prefetch mem space */ |
||||
pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[5].pocmr = |
||||
POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); |
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
|
||||
/* we need RAM mapped to PCI space for the devices to
|
||||
* access main memory */ |
||||
pci_ctrl[1].pitar1 = 0x0; |
||||
pci_ctrl[1].pibar1 = 0x0; |
||||
pci_ctrl[1].piebar1 = 0x0; |
||||
pci_ctrl[1].piwar1 = |
||||
PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | |
||||
(__ilog2(gd->ram_size) - 1); |
||||
|
||||
hose->first_busno = pci_hose[0].last_busno + 1; |
||||
hose->last_busno = 0xff; |
||||
|
||||
/* PCI memory prefetch space */ |
||||
pci_set_region(hose->regions + 0, |
||||
CFG_PCI2_MEM_BASE, |
||||
CFG_PCI2_MEM_PHYS, |
||||
CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose->regions + 1, |
||||
CFG_PCI2_MMIO_BASE, |
||||
CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose->regions + 2, |
||||
CFG_PCI2_IO_BASE, |
||||
CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); |
||||
|
||||
/* System memory space */ |
||||
pci_set_region(hose->regions + 3, |
||||
CONFIG_PCI_SYS_MEM_BUS, |
||||
CONFIG_PCI_SYS_MEM_PHYS, |
||||
gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); |
||||
|
||||
hose->region_count = 4; |
||||
|
||||
pci_setup_indirect(hose, |
||||
(CFG_IMMRBAR + 0x8380), (CFG_IMMRBAR + 0x8384)); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write to Command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(hose->first_busno, 0, 0); |
||||
pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
#endif |
||||
} |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
@ -0,0 +1,120 @@ |
||||
/* |
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc83xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -0,0 +1,753 @@ |
||||
/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
MPC8349E-mITX board configuration file |
||||
|
||||
Memory map: |
||||
|
||||
0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) |
||||
0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) |
||||
0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) |
||||
0xE000_0000-0xEFFF_FFFF IMMR (1 MB) |
||||
0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) |
||||
0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) |
||||
0xF000_0000-0xF000_FFFF Compact Flash |
||||
0xF001_0000-0xF001_FFFF Local bus expansion slot |
||||
0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 |
||||
0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) |
||||
0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) |
||||
|
||||
I2C address list: |
||||
Align. Board |
||||
Bus Addr Part No. Description Length Location |
||||
---------------------------------------------------------------- |
||||
I2C1 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
||||
|
||||
I2C2 0x20 PCF8574 I2C Expander 0 U8 |
||||
I2C2 0x21 PCF8574 I2C Expander 0 U10 |
||||
I2C2 0x38 PCF8574A I2C Expander 0 U8 |
||||
I2C2 0x39 PCF8574A I2C Expander 0 U10 |
||||
I2C2 0x51 (DDR) DDR EEPROM 1 U1 |
||||
I2C2 0x68 DS1339 RTC 1 U68 |
||||
|
||||
Note that a given board has *either* a pair of 8574s or a pair of 8574As. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ |
||||
#define CONFIG_MPC8349 /* MPC8349 specific */ |
||||
|
||||
#define CONFIG_PCI |
||||
|
||||
#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ |
||||
#define CONFIG_RTC_DS1337 |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
|
||||
#define CONFIG_MISC_INIT_F |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
#define CFG_I2C2_OFFSET 0x3100 |
||||
#define CFG_SPD_BUS_NUM I2C_2 |
||||
|
||||
#define CFG_I2C_8574_ADDR1 0x20 /* I2C2, PCF8574 */ |
||||
#define CFG_I2C_8574_ADDR2 0x21 /* I2C2, PCF8574 */ |
||||
#define CFG_I2C_8574A_ADDR1 0x38 /* I2C2, PCF8574A */ |
||||
#define CFG_I2C_8574A_ADDR2 0x39 /* I2C2, PCF8574A */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C1, Board EEPROM */ |
||||
#define CFG_I2C_RTC_ADDR 0x68 /* I2C2, DS1339 RTC*/ |
||||
#define SPD_EEPROM_ADDRESS 0x51 /* I2C2, DDR */ |
||||
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/* Don't probe these addresses: */ |
||||
#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ |
||||
{1, CFG_I2C_8574_ADDR2}, \
|
||||
{1, CFG_I2C_8574A_ADDR1}, \
|
||||
{1, CFG_I2C_8574A_ADDR2}} |
||||
/* Bit definitions for the 8574[A] I2C expander */ |
||||
#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ |
||||
#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ |
||||
#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ |
||||
#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ |
||||
#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ |
||||
|
||||
#undef CONFIG_SOFT_I2C |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define PCI_66M |
||||
#ifdef PCI_66M |
||||
#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#ifdef PCI_66M |
||||
#define CONFIG_SYS_CLK_FREQ 66666666 |
||||
#else |
||||
#define CONFIG_SYS_CLK_FREQ 33333333 |
||||
#endif |
||||
#endif |
||||
|
||||
#define CFG_IMMRBAR 0xE0000000 /* The IMMR is relocated to here */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00003000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
||||
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
||||
|
||||
/*
|
||||
* 32-bit data path mode. |
||||
* |
||||
* Please note that using this mode for devices with the real density of 64-bit |
||||
* effectively reduces the amount of available memory due to the effect of |
||||
* wrapping around while translating address to row/columns, for example in the |
||||
* 256MB module the upper 128MB get aliased with contents of the lower |
||||
* 128MB); normally this define should be used for devices with real 32-bit |
||||
* data path. |
||||
*/ |
||||
#undef CONFIG_DDR_32BIT |
||||
|
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
||||
#undef CONFIG_DDR_2T_TIMING |
||||
#define CFG_83XX_DDR_USES_CS0 |
||||
|
||||
#ifndef CONFIG_SPD_EEPROM |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
#define CFG_DDR_SIZE 256 /* Mb */ |
||||
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
||||
|
||||
#define CFG_DDR_TIMING_1 0x26242321 |
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ |
||||
#endif |
||||
|
||||
/* FLASH on the Local Bus */ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ |
||||
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) |
||||
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
||||
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ |
||||
|
||||
/* VSC7385 on the Local Bus */ |
||||
#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ |
||||
|
||||
#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) |
||||
#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ |
||||
OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
|
||||
OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
||||
|
||||
#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ |
||||
#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ |
||||
|
||||
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ |
||||
#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) |
||||
#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ |
||||
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \
|
||||
OR_GPCM_SCY_9 | \
|
||||
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
||||
|
||||
#ifdef CONFIG_COMPACT_FLASH |
||||
|
||||
#define CFG_CF_BASE 0xF0000000 |
||||
|
||||
#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) |
||||
#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) |
||||
|
||||
#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ |
||||
#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ |
||||
|
||||
#undef CONFIG_IDE_RESET |
||||
#undef CONFIG_IDE_PREINIT |
||||
|
||||
#define CFG_IDE_MAXBUS 1 |
||||
#define CFG_IDE_MAXDEVICE 1 |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
#define CFG_ATA_BASE_ADDR CFG_CF_BASE |
||||
#define CFG_ATA_DATA_OFFSET 0x0000 |
||||
#define CFG_ATA_REG_OFFSET 0 |
||||
#define CFG_ATA_ALT_OFFSET 0x0200 |
||||
#define CFG_ATA_STRIDE 2 |
||||
|
||||
#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ |
||||
|
||||
#endif |
||||
|
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CFG_MID_FLASH_JUMP 0x7F000000 |
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK |
||||
#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs |
||||
* LCRR: DLL bypass, Clock divider is 4 |
||||
* External Local Bus rate is |
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
|
||||
#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ |
||||
|
||||
#ifdef CFG_LB_SDRAM |
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port-size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 |
||||
*/ |
||||
|
||||
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
#define CFG_LBLAWBAR2_PRELIM 0xF0000000 |
||||
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ |
||||
|
||||
#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) |
||||
#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ |
||||
OR_SDRAM_XAM | \
|
||||
((9 - 7) << OR_SDRAM_COLS_SHIFT) | \
|
||||
((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \
|
||||
OR_SDRAM_EAD) |
||||
|
||||
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
||||
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) |
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ |
||||
| CFG_LBC_LSDMR_BSMA1516 \
|
||||
| CFG_LBC_LSDMR_RFCR8 \
|
||||
| CFG_LBC_LSDMR_PRETOACT6 \
|
||||
| CFG_LBC_LSDMR_ACTTORW3 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC3 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
) |
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_PCHALL) |
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_MRW) |
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_NORMAL) |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
|
||||
#ifdef CONFIG_PCI |
||||
|
||||
#define CONFIG_MPC83XX_PCI2 |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) |
||||
#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE |
||||
#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_IO_BASE 0x00000000 |
||||
#define CFG_PCI1_IO_PHYS 0xE2000000 |
||||
#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
#define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) |
||||
#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE |
||||
#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI2_IO_BASE 0x00000000 |
||||
#define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) |
||||
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ |
||||
#endif |
||||
|
||||
#define _IO_BASE 0x00000000 /* points to PCI I/O space */ |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#ifdef CONFIG_RTL8139 |
||||
/* This macro is used by RTL8139 but not defined in PPC architecture */ |
||||
#define KSEG1ADDR(x) (x) |
||||
#endif |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
#define PCI_ENET0_IOADDR 0x00000000 |
||||
#define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE |
||||
#define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
||||
#endif |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
|
||||
#endif |
||||
|
||||
/* TSEC */ |
||||
|
||||
#ifdef CONFIG_TSEC_ENET |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI |
||||
#endif |
||||
|
||||
#define CONFIG_MII |
||||
#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ |
||||
|
||||
#define CONFIG_MPC83XX_TSEC1 |
||||
|
||||
#ifdef CONFIG_MPC83XX_TSEC1 |
||||
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" |
||||
#define CFG_TSEC1_OFFSET 0x24000 |
||||
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
||||
#define TSEC1_PHYIDX 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC83XX_TSEC2 |
||||
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" |
||||
#define CFG_TSEC2_OFFSET 0x25000 |
||||
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ |
||||
#define TSEC2_PHY_ADDR 4 |
||||
#define TSEC2_PHYIDX 0 |
||||
#endif |
||||
|
||||
#define CONFIG_ETHPRIME "Freescale TSEC" |
||||
|
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||
|
||||
/* CONFIG_COMMANDS */ |
||||
|
||||
#ifdef CONFIG_COMPACT_FLASH |
||||
#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) |
||||
#else |
||||
#define CONFIG_COMMANDS_CF 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_COMMANDS_PCI CFG_CMD_PCI |
||||
#else |
||||
#define CONFIG_COMMANDS_PCI 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
#define CONFIG_COMMANDS_I2C CFG_CMD_I2C |
||||
#else |
||||
#define CONFIG_COMMANDS_I2C 0 |
||||
#endif |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CONFIG_COMMANDS_CF | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_PING | \
|
||||
CONFIG_COMMANDS_I2C | \
|
||||
CONFIG_COMMANDS_PCI | \
|
||||
CFG_CMD_SDRAM | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_IRQ) |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/* Watchdog */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#ifdef CONFIG_WATCHDOG |
||||
#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ |
||||
#endif |
||||
|
||||
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
||||
|
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
|
||||
#ifdef PCI_64BIT |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_64_BIT_PCI |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCI2_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_TSEC1M_IN_GMII |\
|
||||
HRCWH_TSEC2M_IN_GMII ) |
||||
#else |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_32_BIT_PCI |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCI2_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_TSEC1M_IN_GMII |\
|
||||
HRCWH_TSEC2M_IN_GMII ) |
||||
#endif |
||||
|
||||
/* System performance */ |
||||
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
||||
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
||||
#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
||||
#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ |
||||
#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ |
||||
#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C1 clock mode (0-3) */ |
||||
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ |
||||
|
||||
/* System IO Config */ |
||||
#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ |
||||
#define CFG_SICRL SICRL_LDP_A |
||||
|
||||
#define CFG_HID0_INIT 0x000000000 |
||||
|
||||
#define CFG_HID0_FINAL CFG_HID0_INIT |
||||
|
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/* DDR @ 0x00000000 */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* PCI @ 0x80000000 */ |
||||
#ifdef CONFIG_PCI |
||||
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#else |
||||
#define CFG_IBAT1L 0 |
||||
#define CFG_IBAT1U 0 |
||||
#define CFG_IBAT2L 0 |
||||
#define CFG_IBAT2U 0 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC83XX_PCI2 |
||||
#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#else |
||||
#define CFG_IBAT3L 0 |
||||
#define CFG_IBAT3U 0 |
||||
#define CFG_IBAT4L 0 |
||||
#define CFG_IBAT4U 0 |
||||
#endif |
||||
|
||||
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
||||
#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
||||
#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT7L 0 |
||||
#define CFG_IBAT7U 0 |
||||
|
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#ifdef CONFIG_MPC83XX_TSEC1 |
||||
#define CONFIG_ETHADDR 00:E0:0C:00:8C:01 |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC83XX_TSEC2 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 |
||||
#endif |
||||
|
||||
#define CONFIG_IPADDR 10.82.19.159 |
||||
#define CONFIG_SERVERIP 10.82.48.106 |
||||
#define CONFIG_GATEWAYIP 10.82.19.254 |
||||
#define CONFIG_NETMASK 255.255.252.0 |
||||
|
||||
|
||||
#define CONFIG_HOSTNAME mpc8349emitx |
||||
#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs |
||||
#define CONFIG_BOOTFILE timur/uImage |
||||
|
||||
#define CONFIG_UBOOTPATH timur/u-boot.bin |
||||
#define CONFIG_UBOOTSTART fe700000 |
||||
#define CONFIG_UBOOTEND fe77ffff |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#undef CONFIG_BOOTCOMMAND |
||||
#ifdef CONFIG_BOOTCOMMAND |
||||
#define CONFIG_BOOTDELAY 6 |
||||
#else |
||||
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTARGS \ |
||||
"root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=ttyS0,$baudrate $othbootargs" |
||||
|
||||
#define XMK_STR(x) #x |
||||
#define MK_STR(x) XMK_STR(x) |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
|
||||
"erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
|
||||
"cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \
|
||||
"tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
|
||||
"protect off FEF00000 FEF7FFFF; " \
|
||||
"erase FEF00000 FEF7FFFF; " \
|
||||
"cp.b $loadaddr FEF00000 $filesize; " \
|
||||
"protect on FEF00000 FEF7FFFF; " \
|
||||
"cmp.b $loadaddr FEF00000 $filesize\0" \
|
||||
"tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \
|
||||
"copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
|
||||
"cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" |
||||
|
||||
|
||||
#undef MK_STR |
||||
#undef XMK_STR |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue