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@ -135,7 +135,7 @@ __attribute__((weak, alias("__get_spd"))) |
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void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); |
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void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
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unsigned int ctrl_num) |
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unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) |
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{ |
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unsigned int i; |
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unsigned int i2c_address = 0; |
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@ -145,14 +145,14 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
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return; |
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} |
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { |
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for (i = 0; i < dimm_slots_per_ctrl; i++) { |
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i2c_address = spd_i2c_addr[ctrl_num][i]; |
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get_spd(&(ctrl_dimms_spd[i]), i2c_address); |
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} |
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} |
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#else |
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void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
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unsigned int ctrl_num) |
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unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) |
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{ |
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} |
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#endif /* SPD_EEPROM_ADDRESSx */ |
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@ -231,9 +231,11 @@ const char * step_to_string(unsigned int step) { |
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static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, |
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unsigned int dbw_cap_adj[]) |
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{ |
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int i, j; |
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unsigned int i, j; |
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unsigned long long total_mem, current_mem_base, total_ctlr_mem; |
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unsigned long long rank_density, ctlr_density = 0; |
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unsigned int first_ctrl = pinfo->first_ctrl; |
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unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
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/*
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* If a reduced data width is requested, but the SPD |
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@ -241,7 +243,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, |
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* computed dimm capacities accordingly before |
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* assigning addresses. |
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*/ |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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unsigned int found = 0; |
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switch (pinfo->memctl_opts[i].data_bus_width) { |
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@ -295,12 +297,12 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, |
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debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); |
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} |
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current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; |
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current_mem_base = pinfo->mem_base; |
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total_mem = 0; |
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if (pinfo->memctl_opts[0].memctl_interleaving) { |
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rank_density = pinfo->dimm_params[0][0].rank_density >> |
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dbw_cap_adj[0]; |
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switch (pinfo->memctl_opts[0].ba_intlv_ctl & |
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if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) { |
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rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >> |
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dbw_cap_adj[first_ctrl]; |
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switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl & |
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FSL_DDR_CS0_CS1_CS2_CS3) { |
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case FSL_DDR_CS0_CS1_CS2_CS3: |
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ctlr_density = 4 * rank_density; |
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@ -316,7 +318,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, |
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} |
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debug("rank density is 0x%llx, ctlr density is 0x%llx\n", |
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rank_density, ctlr_density); |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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if (pinfo->memctl_opts[i].memctl_interleaving) { |
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switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { |
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case FSL_DDR_256B_INTERLEAVING: |
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@ -372,7 +374,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, |
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* Simple linear assignment if memory |
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* controllers are not interleaved. |
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*/ |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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total_ctlr_mem = 0; |
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pinfo->common_timing_params[i].base_address = |
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current_mem_base; |
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@ -408,18 +410,23 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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{ |
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unsigned int i, j; |
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unsigned long long total_mem = 0; |
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int assert_reset; |
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int assert_reset = 0; |
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unsigned int first_ctrl = pinfo->first_ctrl; |
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unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
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__maybe_unused int retval; |
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__maybe_unused bool goodspd = false; |
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__maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl; |
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fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; |
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common_timing_params_t *timing_params = pinfo->common_timing_params; |
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assert_reset = board_need_mem_reset(); |
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if (pinfo->board_need_mem_reset) |
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assert_reset = pinfo->board_need_mem_reset(); |
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/* data bus width capacity adjust shift amount */ |
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unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) |
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dbw_capacity_adjust[i] = 0; |
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} |
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debug("starting at step %u (%s)\n", |
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start_step, step_to_string(start_step)); |
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@ -428,28 +435,28 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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case STEP_GET_SPD: |
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#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) |
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/* STEP 1: Gather all DIMM SPD data */ |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i, |
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dimm_slots_per_ctrl); |
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} |
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case STEP_COMPUTE_DIMM_PARMS: |
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/* STEP 2: Compute DIMM parameters from SPD data */ |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
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unsigned int retval; |
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generic_spd_eeprom_t *spd = |
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&(pinfo->spd_installed_dimms[i][j]); |
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dimm_params_t *pdimm = |
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&(pinfo->dimm_params[i][j]); |
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retval = compute_dimm_parameters(spd, pdimm, i); |
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#ifdef CONFIG_SYS_DDR_RAW_TIMING |
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if (!i && !j && retval) { |
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printf("SPD error on controller %d! " |
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"Trying fallback to raw timing " |
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"calculation\n", i); |
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fsl_ddr_get_dimm_params(pdimm, i, j); |
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retval = fsl_ddr_get_dimm_params(pdimm, |
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i, j); |
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} |
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#else |
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if (retval == 2) { |
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@ -463,13 +470,26 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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debug("Warning: compute_dimm_parameters" |
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" non-zero return value for memctl=%u " |
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"dimm=%u\n", i, j); |
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} else { |
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goodspd = true; |
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} |
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} |
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} |
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if (!goodspd) { |
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/*
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* No valid SPD found |
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* Throw an error if this is for main memory, i.e. |
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* first_ctrl == 0. Otherwise, siliently return 0 |
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* as the memory size. |
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*/ |
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if (first_ctrl == 0) |
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printf("Error: No valid SPD detected.\n"); |
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return 0; |
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} |
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#elif defined(CONFIG_SYS_DDR_RAW_TIMING) |
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case STEP_COMPUTE_DIMM_PARMS: |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
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dimm_params_t *pdimm = |
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&(pinfo->dimm_params[i][j]); |
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@ -483,7 +503,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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* STEP 3: Compute a common set of timing parameters |
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* suitable for all of the DIMMs on each memory controller |
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*/ |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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debug("Computing lowest common DIMM" |
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" parameters for memctl=%u\n", i); |
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compute_lowest_common_dimm_parameters( |
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@ -494,7 +514,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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case STEP_GATHER_OPTS: |
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/* STEP 4: Gather configuration requirements from user */ |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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debug("Reloading memory controller " |
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"configuration options for memctl=%u\n", i); |
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/*
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@ -516,9 +536,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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if (timing_params[i].all_dimms_registered) |
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assert_reset = 1; |
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} |
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if (assert_reset) { |
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debug("Asserting mem reset\n"); |
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board_assert_mem_reset(); |
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if (assert_reset && !size_only) { |
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if (pinfo->board_mem_reset) { |
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debug("Asserting mem reset\n"); |
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pinfo->board_mem_reset(); |
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} else { |
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debug("Asserting mem reset missing\n"); |
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} |
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} |
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case STEP_ASSIGN_ADDRESSES: |
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@ -530,7 +554,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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case STEP_COMPUTE_REGS: |
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/* STEP 6: compute controller register values */ |
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debug("FSL Memory ctrl register computation\n"); |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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if (timing_params[i].ndimms_present == 0) { |
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memset(&ddr_reg[i], 0, |
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sizeof(fsl_ddr_cfg_regs_t)); |
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@ -558,7 +582,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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*/ |
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unsigned int max_end = 0; |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { |
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fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; |
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if (reg->cs[j].config & 0x80000000) { |
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@ -578,53 +602,45 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
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} |
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total_mem = 1 + (((unsigned long long)max_end << 24ULL) | |
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0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; |
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0xFFFFFFULL) - pinfo->mem_base; |
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} |
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return total_mem; |
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} |
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/*
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* fsl_ddr_sdram() -- this is the main function to be called by |
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* initdram() in the board file. |
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* |
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* It returns amount of memory configured in bytes. |
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*/ |
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phys_size_t fsl_ddr_sdram(void) |
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phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) |
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{ |
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unsigned int i; |
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unsigned int i, first_ctrl, last_ctrl; |
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#ifdef CONFIG_PPC |
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unsigned int law_memctl = LAW_TRGT_IF_DDR_1; |
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#endif |
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unsigned long long total_memory; |
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fsl_ddr_info_t info; |
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int deassert_reset; |
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int deassert_reset = 0; |
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/* Reset info structure. */ |
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memset(&info, 0, sizeof(fsl_ddr_info_t)); |
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first_ctrl = pinfo->first_ctrl; |
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last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
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/* Compute it once normally. */ |
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#ifdef CONFIG_FSL_DDR_INTERACTIVE |
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if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ |
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total_memory = fsl_ddr_interactive(&info, 0); |
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total_memory = fsl_ddr_interactive(pinfo, 0); |
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} else if (fsl_ddr_interactive_env_var_exists()) { |
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total_memory = fsl_ddr_interactive(&info, 1); |
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total_memory = fsl_ddr_interactive(pinfo, 1); |
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} else |
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#endif |
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total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); |
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total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0); |
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/* setup 3-way interleaving before enabling DDRC */ |
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if (info.memctl_opts[0].memctl_interleaving) { |
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switch (info.memctl_opts[0].memctl_interleaving_mode) { |
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case FSL_DDR_3WAY_1KB_INTERLEAVING: |
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case FSL_DDR_3WAY_4KB_INTERLEAVING: |
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case FSL_DDR_3WAY_8KB_INTERLEAVING: |
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fsl_ddr_set_intl3r( |
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info.memctl_opts[0].memctl_interleaving_mode); |
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break; |
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default: |
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break; |
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} |
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switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) { |
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case FSL_DDR_3WAY_1KB_INTERLEAVING: |
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case FSL_DDR_3WAY_4KB_INTERLEAVING: |
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case FSL_DDR_3WAY_8KB_INTERLEAVING: |
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fsl_ddr_set_intl3r( |
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pinfo->memctl_opts[first_ctrl]. |
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memctl_interleaving_mode); |
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break; |
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default: |
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break; |
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} |
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/*
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@ -637,14 +653,15 @@ phys_size_t fsl_ddr_sdram(void) |
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* For non-registered DIMMs, initialization can go through but it is |
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* also OK to follow the same flow. |
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*/ |
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deassert_reset = board_need_mem_reset(); |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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if (info.common_timing_params[i].all_dimms_registered) |
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if (pinfo->board_need_mem_reset) |
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deassert_reset = pinfo->board_need_mem_reset(); |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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if (pinfo->common_timing_params[i].all_dimms_registered) |
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deassert_reset = 1; |
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} |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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debug("Programming controller %u\n", i); |
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if (info.common_timing_params[i].ndimms_present == 0) { |
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if (pinfo->common_timing_params[i].ndimms_present == 0) { |
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debug("No dimms present on controller %u; " |
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"skipping programming\n", i); |
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continue; |
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@ -653,45 +670,58 @@ phys_size_t fsl_ddr_sdram(void) |
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* The following call with step = 1 returns before enabling |
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* the controller. It has to finish with step = 2 later. |
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*/ |
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fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i, |
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fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i, |
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deassert_reset ? 1 : 0); |
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} |
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if (deassert_reset) { |
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/* Use board FPGA or GPIO to deassert reset signal */ |
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debug("Deasserting mem reset\n"); |
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board_deassert_mem_reset(); |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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if (pinfo->board_mem_de_reset) { |
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debug("Deasserting mem reset\n"); |
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pinfo->board_mem_de_reset(); |
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} else { |
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debug("Deasserting mem reset missing\n"); |
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} |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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/* Call with step = 2 to continue initialization */ |
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fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), |
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fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), |
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i, 2); |
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} |
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} |
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#ifdef CONFIG_PPC |
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/* program LAWs */ |
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { |
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if (info.memctl_opts[i].memctl_interleaving) { |
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switch (info.memctl_opts[i].memctl_interleaving_mode) { |
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for (i = first_ctrl; i <= last_ctrl; i++) { |
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if (pinfo->memctl_opts[i].memctl_interleaving) { |
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switch (pinfo->memctl_opts[i]. |
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memctl_interleaving_mode) { |
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case FSL_DDR_CACHE_LINE_INTERLEAVING: |
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case FSL_DDR_PAGE_INTERLEAVING: |
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case FSL_DDR_BANK_INTERLEAVING: |
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case FSL_DDR_SUPERBANK_INTERLEAVING: |
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if (i % 2) |
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break; |
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if (i == 0) { |
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law_memctl = LAW_TRGT_IF_DDR_INTRLV; |
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fsl_ddr_set_lawbar(&info.common_timing_params[i], |
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fsl_ddr_set_lawbar( |
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&pinfo->common_timing_params[i], |
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law_memctl, i); |
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} else if (i == 2) { |
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} |
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#if CONFIG_NUM_DDR_CONTROLLERS > 3 |
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else if (i == 2) { |
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law_memctl = LAW_TRGT_IF_DDR_INTLV_34; |
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fsl_ddr_set_lawbar(&info.common_timing_params[i], |
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fsl_ddr_set_lawbar( |
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&pinfo->common_timing_params[i], |
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law_memctl, i); |
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} |
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#endif |
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break; |
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case FSL_DDR_3WAY_1KB_INTERLEAVING: |
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case FSL_DDR_3WAY_4KB_INTERLEAVING: |
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case FSL_DDR_3WAY_8KB_INTERLEAVING: |
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law_memctl = LAW_TRGT_IF_DDR_INTLV_123; |
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if (i == 0) { |
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fsl_ddr_set_lawbar(&info.common_timing_params[i], |
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fsl_ddr_set_lawbar( |
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&pinfo->common_timing_params[i], |
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law_memctl, i); |
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} |
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break; |
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@ -700,7 +730,8 @@ phys_size_t fsl_ddr_sdram(void) |
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case FSL_DDR_4WAY_8KB_INTERLEAVING: |
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law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; |
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if (i == 0) |
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fsl_ddr_set_lawbar(&info.common_timing_params[i], |
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fsl_ddr_set_lawbar( |
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&pinfo->common_timing_params[i], |
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law_memctl, i); |
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/* place holder for future 4-way interleaving */ |
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break; |
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@ -724,8 +755,8 @@ phys_size_t fsl_ddr_sdram(void) |
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default: |
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break; |
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} |
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fsl_ddr_set_lawbar(&info.common_timing_params[i], |
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law_memctl, i); |
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fsl_ddr_set_lawbar(&pinfo->common_timing_params[i], |
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law_memctl, i); |
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} |
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} |
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#endif |
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@ -734,7 +765,7 @@ phys_size_t fsl_ddr_sdram(void) |
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#if !defined(CONFIG_PHYS_64BIT) |
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/* Check for 4G or more. Bad. */ |
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if (total_memory >= (1ull << 32)) { |
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if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) { |
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puts("Detected "); |
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|
print_size(total_memory, " of memory\n"); |
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|
printf(" This U-Boot only supports < 4G of DDR\n"); |
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|
@ -748,8 +779,56 @@ phys_size_t fsl_ddr_sdram(void) |
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} |
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|
/*
|
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|
|
* fsl_ddr_sdram_size() - This function only returns the size of the total |
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|
* memory without setting ddr control registers. |
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|
* fsl_ddr_sdram(void) -- this is the main function to be |
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|
* called by initdram() in the board file. |
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|
* |
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|
* It returns amount of memory configured in bytes. |
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|
*/ |
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|
|
phys_size_t fsl_ddr_sdram(void) |
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|
{ |
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|
fsl_ddr_info_t info; |
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|
/* Reset info structure. */ |
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|
memset(&info, 0, sizeof(fsl_ddr_info_t)); |
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|
info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; |
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info.first_ctrl = 0; |
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info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; |
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info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; |
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info.board_need_mem_reset = board_need_mem_reset; |
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info.board_mem_reset = board_assert_mem_reset; |
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info.board_mem_de_reset = board_deassert_mem_reset; |
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|
return __fsl_ddr_sdram(&info); |
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|
} |
|
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|
|
|
#ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS |
|
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|
|
phys_size_t fsl_other_ddr_sdram(unsigned long long base, |
|
|
|
|
unsigned int first_ctrl, |
|
|
|
|
unsigned int num_ctrls, |
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|
|
unsigned int dimm_slots_per_ctrl, |
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|
|
int (*board_need_reset)(void), |
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|
|
void (*board_reset)(void), |
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|
|
void (*board_de_reset)(void)) |
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|
|
{ |
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|
|
fsl_ddr_info_t info; |
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|
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|
|
/* Reset info structure. */ |
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|
|
memset(&info, 0, sizeof(fsl_ddr_info_t)); |
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|
|
info.mem_base = base; |
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|
|
info.first_ctrl = first_ctrl; |
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|
|
info.num_ctrls = num_ctrls; |
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|
|
info.dimm_slots_per_ctrl = dimm_slots_per_ctrl; |
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|
|
info.board_need_mem_reset = board_need_reset; |
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|
|
info.board_mem_reset = board_reset; |
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|
|
info.board_mem_de_reset = board_de_reset; |
|
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|
|
return __fsl_ddr_sdram(&info); |
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|
|
} |
|
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|
|
#endif |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the |
|
|
|
|
* size of the total memory without setting ddr control registers. |
|
|
|
|
*/ |
|
|
|
|
phys_size_t |
|
|
|
|
fsl_ddr_sdram_size(void) |
|
|
|
@ -758,6 +837,11 @@ fsl_ddr_sdram_size(void) |
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|
|
unsigned long long total_memory = 0; |
|
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|
|
|
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|
|
memset(&info, 0 , sizeof(fsl_ddr_info_t)); |
|
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|
|
info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; |
|
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|
|
info.first_ctrl = 0; |
|
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|
|
info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; |
|
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|
|
info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; |
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|
|
info.board_need_mem_reset = NULL; |
|
|
|
|
|
|
|
|
|
/* Compute it once normally. */ |
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|
|
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); |
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|
|