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@ -18,6 +18,7 @@ |
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#include <malloc.h> |
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#include <asm/io.h> |
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#include <asm/mach-common/bits/spi.h> |
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#include <asm/mach-common/bits/dma.h> |
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/* Forcibly phase out these */ |
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#ifdef CONFIG_SPI_FLASH_NUM_SECTORS |
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@ -32,53 +33,65 @@ |
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struct flash_info { |
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char *name; |
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uint16_t id; |
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uint16_t ext_id; |
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unsigned sector_size; |
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unsigned num_sectors; |
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}; |
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/* SPI Speeds: 50 MHz / 33 MHz */ |
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static struct flash_info flash_spansion_serial_flash[] = { |
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{ "S25FL016", 0x0215, 64 * 1024, 32 }, |
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{ "S25FL032", 0x0216, 64 * 1024, 64 }, |
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{ "S25FL064", 0x0217, 64 * 1024, 128 }, |
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{ "S25FL0128", 0x0218, 256 * 1024, 64 }, |
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{ NULL, 0, 0, 0 } |
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{ "S25FL016", 0x0215, 0, 64 * 1024, 32 }, |
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{ "S25FL032", 0x0216, 0, 64 * 1024, 64 }, |
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{ "S25FL064", 0x0217, 0, 64 * 1024, 128 }, |
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{ "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */ |
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{ "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */ |
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{ NULL, 0, 0, 0, 0 } |
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}; |
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/* SPI Speeds: 50 MHz / 20 MHz */ |
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static struct flash_info flash_st_serial_flash[] = { |
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{ "m25p05", 0x2010, 32 * 1024, 2 }, |
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{ "m25p10", 0x2011, 32 * 1024, 4 }, |
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{ "m25p20", 0x2012, 64 * 1024, 4 }, |
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{ "m25p40", 0x2013, 64 * 1024, 8 }, |
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{ "m25p16", 0x2015, 64 * 1024, 32 }, |
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{ "m25p32", 0x2016, 64 * 1024, 64 }, |
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{ "m25p64", 0x2017, 64 * 1024, 128 }, |
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{ "m25p128", 0x2018, 256 * 1024, 64 }, |
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{ NULL, 0, 0, 0 } |
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{ "m25p05", 0x2010, 0, 32 * 1024, 2 }, |
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{ "m25p10", 0x2011, 0, 32 * 1024, 4 }, |
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{ "m25p20", 0x2012, 0, 64 * 1024, 4 }, |
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{ "m25p40", 0x2013, 0, 64 * 1024, 8 }, |
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{ "m25p80", 0x20FF, 0, 64 * 1024, 16 }, |
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{ "m25p16", 0x2015, 0, 64 * 1024, 32 }, |
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{ "m25p32", 0x2016, 0, 64 * 1024, 64 }, |
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{ "m25p64", 0x2017, 0, 64 * 1024, 128 }, |
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{ "m25p128", 0x2018, 0, 256 * 1024, 64 }, |
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{ NULL, 0, 0, 0, 0 } |
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}; |
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/* SPI Speeds: 20 MHz / 40 MHz */ |
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static struct flash_info flash_sst_serial_flash[] = { |
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{ "SST25WF512", 0x2501, 0, 4 * 1024, 128 }, |
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{ "SST25WF010", 0x2502, 0, 4 * 1024, 256 }, |
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{ "SST25WF020", 0x2503, 0, 4 * 1024, 512 }, |
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{ "SST25WF040", 0x2504, 0, 4 * 1024, 1024 }, |
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{ NULL, 0, 0, 0, 0 } |
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}; |
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/* SPI Speeds: 66 MHz / 33 MHz */ |
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static struct flash_info flash_atmel_dataflash[] = { |
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{ "AT45DB011x", 0x0c, 264, 512 }, |
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{ "AT45DB021x", 0x14, 264, 1025 }, |
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{ "AT45DB041x", 0x1c, 264, 2048 }, |
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{ "AT45DB081x", 0x24, 264, 4096 }, |
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{ "AT45DB161x", 0x2c, 528, 4096 }, |
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{ "AT45DB321x", 0x34, 528, 8192 }, |
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{ "AT45DB642x", 0x3c, 1056, 8192 }, |
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{ NULL, 0, 0, 0 } |
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{ "AT45DB011x", 0x0c, 0, 264, 512 }, |
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{ "AT45DB021x", 0x14, 0, 264, 1025 }, |
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{ "AT45DB041x", 0x1c, 0, 264, 2048 }, |
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{ "AT45DB081x", 0x24, 0, 264, 4096 }, |
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{ "AT45DB161x", 0x2c, 0, 528, 4096 }, |
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{ "AT45DB321x", 0x34, 0, 528, 8192 }, |
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{ "AT45DB642x", 0x3c, 0, 1056, 8192 }, |
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{ NULL, 0, 0, 0, 0 } |
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}; |
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/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */ |
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static struct flash_info flash_winbond_serial_flash[] = { |
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{ "W25X10", 0x3011, 16 * 256, 32 }, |
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{ "W25X20", 0x3012, 16 * 256, 64 }, |
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{ "W25X40", 0x3013, 16 * 256, 128 }, |
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{ "W25X80", 0x3014, 16 * 256, 256 }, |
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{ "W25P80", 0x2014, 256 * 256, 16 }, |
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{ "W25P16", 0x2015, 256 * 256, 32 }, |
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{ NULL, 0, 0, 0 } |
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{ "W25X10", 0x3011, 0, 16 * 256, 32 }, |
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{ "W25X20", 0x3012, 0, 16 * 256, 64 }, |
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{ "W25X40", 0x3013, 0, 16 * 256, 128 }, |
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{ "W25X80", 0x3014, 0, 16 * 256, 256 }, |
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{ "W25P80", 0x2014, 0, 256 * 256, 16 }, |
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{ "W25P16", 0x2015, 0, 256 * 256, 32 }, |
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{ NULL, 0, 0, 0, 0 } |
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}; |
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struct flash_ops { |
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@ -97,6 +110,13 @@ static struct flash_ops flash_st_ops = { |
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.status = 0x05, |
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}; |
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static struct flash_ops flash_sst_ops = { |
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.read = OP_READ, |
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.write = 0x02, |
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.erase = 0x20, |
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.status = 0x05, |
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}; |
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static struct flash_ops flash_atmel_ops = { |
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.read = OP_READ, |
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.write = 0x82, |
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@ -122,7 +142,7 @@ static struct { |
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struct manufacturer_info *manufacturer; |
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struct flash_info *flash; |
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struct flash_ops *ops; |
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uint8_t manufacturer_id, device_id1, device_id2; |
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uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2; |
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unsigned int write_length; |
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unsigned long sector_size, num_sectors; |
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} flash; |
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@ -130,6 +150,7 @@ static struct { |
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enum { |
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JED_MANU_SPANSION = 0x01, |
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JED_MANU_ST = 0x20, |
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JED_MANU_SST = 0xBF, |
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JED_MANU_ATMEL = 0x1F, |
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JED_MANU_WINBOND = 0xEF, |
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}; |
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@ -148,6 +169,12 @@ static struct manufacturer_info flash_manufacturers[] = { |
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.ops = &flash_st_ops, |
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}, |
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{ |
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.name = "SST", |
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.id = JED_MANU_SST, |
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.flashes = flash_sst_serial_flash, |
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.ops = &flash_sst_ops, |
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}, |
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{ |
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.name = "Atmel", |
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.id = JED_MANU_ATMEL, |
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.flashes = flash_atmel_dataflash, |
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@ -161,7 +188,7 @@ static struct manufacturer_info flash_manufacturers[] = { |
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}, |
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}; |
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#define TIMEOUT 5000 /* timeout of 5 seconds */ |
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#define TIMEOUT 5000 /* timeout of 5 seconds */ |
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/* If part has multiple SPI flashes, assume SPI0 as that is
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* the one we can boot off of ... |
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@ -189,6 +216,7 @@ static void SPI_INIT(void) |
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/* [#3541] This delay appears to be necessary, but not sure
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* exactly why as the history behind it is non-existant. |
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*/ |
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*pSPI_CTL = 0; |
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udelay(CONFIG_CCLK_HZ / 25000000); |
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/* enable SPI pins: SSEL, MOSI, MISO, SCK */ |
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@ -205,14 +233,13 @@ static void SPI_INIT(void) |
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#endif |
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/* initate communication upon write of TDBR */ |
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*pSPI_CTL = (SPE|MSTR|CPHA|CPOL|0x01); |
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*pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); |
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*pSPI_BAUD = CONFIG_SPI_BAUD; |
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} |
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static void SPI_DEINIT(void) |
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{ |
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/* put SPI settings back to reset state */ |
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*pSPI_CTL = 0x0400; |
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*pSPI_CTL = 0; |
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*pSPI_BAUD = 0; |
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SSYNC(); |
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} |
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@ -275,6 +302,7 @@ static int wait_for_ready_status(void) |
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switch (flash.manufacturer_id) { |
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case JED_MANU_SPANSION: |
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case JED_MANU_ST: |
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case JED_MANU_SST: |
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case JED_MANU_WINBOND: |
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if (!(read_status_register() & 0x01)) |
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return 0; |
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@ -296,19 +324,68 @@ static int wait_for_ready_status(void) |
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return -1; |
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} |
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static int enable_writing(void) |
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{ |
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ulong start; |
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if (flash.manufacturer_id == JED_MANU_ATMEL) |
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return 0; |
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/* A write enable instruction must previously have been executed */ |
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SPI_ON(); |
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spi_write_read_byte(0x06); |
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SPI_OFF(); |
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/* The status register will be polled to check the write enable latch "WREN" */ |
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start = get_timer(0); |
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while (get_timer(0) - start < TIMEOUT) { |
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if (read_status_register() & 0x02) |
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return 0; |
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if (ctrlc()) { |
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puts("\nAbort\n"); |
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return -1; |
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} |
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} |
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puts("Timeout\n"); |
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return -1; |
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} |
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static void write_status_register(uint8_t val) |
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{ |
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if (flash.manufacturer_id != JED_MANU_SST) |
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hang(); |
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if (enable_writing()) |
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return; |
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/* send instruction to write status register */ |
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SPI_ON(); |
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spi_write_read_byte(0x01); |
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/* and clear it! */ |
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spi_write_read_byte(val); |
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SPI_OFF(); |
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} |
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/* Request and read the manufacturer and device id of parts which
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* are compatible with the JEDEC standard (JEP106) and use that to |
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* setup other operating conditions. |
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*/ |
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static int spi_detect_part(void) |
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{ |
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uint16_t dev_id; |
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uint16_t dev_id, dev_extid; |
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size_t i; |
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static char called_init; |
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if (called_init) |
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return 0; |
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#ifdef CONFIG_SPI_FLASH_M25P80 |
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flash.manufacturer_id = JED_MANU_ST; |
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flash.device_id1 = 0x20; |
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flash.device_id2 = 0xFF; |
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#else |
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SPI_ON(); |
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/* Send the request for the part identification */ |
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@ -327,9 +404,15 @@ static int spi_detect_part(void) |
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/* Now read in the second device id byte */ |
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flash.device_id2 = spi_write_read_byte(0); |
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/* Read extended device ids */ |
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flash.device_extid1 = spi_write_read_byte(0); |
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flash.device_extid2 = spi_write_read_byte(0); |
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SPI_OFF(); |
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#endif |
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dev_id = (flash.device_id1 << 8) | flash.device_id2; |
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dev_extid = (flash.device_extid1 << 8) | flash.device_extid2; |
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for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) { |
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if (flash.manufacturer_id == flash_manufacturers[i].id) |
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@ -344,9 +427,12 @@ static int spi_detect_part(void) |
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switch (flash.manufacturer_id) { |
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case JED_MANU_SPANSION: |
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case JED_MANU_ST: |
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case JED_MANU_SST: |
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case JED_MANU_WINBOND: |
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for (i = 0; flash.manufacturer->flashes[i].name; ++i) { |
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if (dev_id == flash.manufacturer->flashes[i].id) |
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if (dev_id == flash.manufacturer->flashes[i].id && |
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(flash.manufacturer->flashes[i].ext_id == 0 || |
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flash.manufacturer->flashes[i].ext_id == dev_extid)) |
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break; |
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} |
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if (!flash.manufacturer->flashes[i].name) |
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@ -355,7 +441,11 @@ static int spi_detect_part(void) |
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flash.flash = &flash.manufacturer->flashes[i]; |
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flash.sector_size = flash.flash->sector_size; |
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flash.num_sectors = flash.flash->num_sectors; |
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flash.write_length = 256; |
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if (flash.manufacturer_id == JED_MANU_SST) |
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flash.write_length = 1; /* pwnt :( */ |
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else |
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flash.write_length = 256; |
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break; |
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case JED_MANU_ATMEL: { |
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@ -381,6 +471,10 @@ static int spi_detect_part(void) |
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} |
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} |
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/* the SST parts power up with software protection enabled by default */ |
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if (flash.manufacturer_id == JED_MANU_SST) |
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write_status_register(0); |
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called_init = 1; |
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return 0; |
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@ -538,9 +632,10 @@ static void transmit_address(uint32_t addr) |
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* int pnData - pointer to store value read from flash |
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* long lCount - number of elements to read |
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*/ |
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#ifdef CONFIG_SPI_READFLASH_NODMA |
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static int read_flash(unsigned long address, long count, uchar *buffer) |
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{ |
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size_t i; |
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size_t i, j; |
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/* Send the read command to SPI device */ |
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SPI_ON(); |
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@ -554,44 +649,134 @@ static int read_flash(unsigned long address, long count, uchar *buffer) |
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/* After the SPI device address has been placed on the MOSI pin the data can be */ |
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/* received on the MISO pin. */ |
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j = flash.sector_size << 1; |
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for (i = 1; i <= count; ++i) { |
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*buffer++ = spi_write_read_byte(0); |
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if (i % flash.sector_size == 0) |
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if (!j--) { |
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puts("."); |
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j = flash.sector_size; |
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} |
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} |
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SPI_OFF(); |
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return 0; |
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} |
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#else |
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static int enable_writing(void) |
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#ifdef __ADSPBF54x__ |
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#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS |
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#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS |
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#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR |
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#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG |
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#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \ |
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defined(__ADSPBF538__) || defined(__ADSPBF539__) |
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#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS |
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#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS |
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#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR |
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#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG |
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#elif defined(__ADSPBF561__) |
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#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS |
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#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS |
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#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR |
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#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG |
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#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \ |
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defined(__ADSPBF52x__) || defined(__ADSPBF51x__) |
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#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS |
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#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS |
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#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR |
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#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG |
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#else |
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#error "Please provide SPI DMA channel defines" |
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#endif |
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struct dmadesc_array { |
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unsigned long start_addr; |
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unsigned short cfg; |
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unsigned short x_count; |
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short x_modify; |
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unsigned short y_count; |
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short y_modify; |
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} __attribute__((packed)); |
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/*
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* Read a value from flash for verify purpose |
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* Inputs: unsigned long ulStart - holds the SPI start address |
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* int pnData - pointer to store value read from flash |
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* long lCount - number of elements to read |
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*/ |
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static int read_flash(unsigned long address, long count, uchar *buffer) |
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{ |
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ulong start; |
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unsigned int ndsize; |
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struct dmadesc_array dma[2]; |
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/* Send the read command to SPI device */ |
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if (flash.manufacturer_id == JED_MANU_ATMEL) |
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if (!count) |
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return 0; |
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/* A write enable instruction must previously have been executed */ |
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dma[0].start_addr = (unsigned long)buffer; |
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dma[0].x_modify = 1; |
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if (count <= 65536) { |
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blackfin_dcache_flush_invalidate_range(buffer, buffer + count); |
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ndsize = NDSIZE_5; |
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dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; |
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dma[0].x_count = count; |
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} else { |
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blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1); |
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ndsize = NDSIZE_7; |
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dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D; |
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dma[0].x_count = 0; /* 2^16 */ |
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dma[0].y_count = count >> 16; /* count / 2^16 */ |
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dma[0].y_modify = 1; |
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dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF)); |
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dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; |
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dma[1].x_count = count & 0xFFFF; /* count % 2^16 */ |
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dma[1].x_modify = 1; |
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} |
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bfin_write_DMA_SPI_CONFIG(0); |
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bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR); |
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bfin_write_DMA_SPI_CURR_DESC_PTR(dma); |
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SPI_ON(); |
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spi_write_read_byte(0x06); |
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spi_write_read_byte(flash.ops->read); |
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transmit_address(address); |
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#ifndef CONFIG_SPI_FLASH_SLOW_READ |
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/* Send dummy byte when doing SPI fast reads */ |
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spi_write_read_byte(0); |
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#endif |
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bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN); |
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*pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ); |
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SSYNC(); |
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/*
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* We already invalidated the first 64k, |
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* now while we just wait invalidate the remaining part. |
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* Its not likely that the DMA is going to overtake |
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*/ |
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if (count > 65536) |
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blackfin_dcache_flush_invalidate_range(buffer + 65536, |
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buffer + count); |
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while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE)) |
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if (ctrlc()) |
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break; |
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SPI_OFF(); |
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/* The status register will be polled to check the write enable latch "WREN" */ |
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start = get_timer(0); |
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while (get_timer(0) - start < TIMEOUT) { |
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if (read_status_register() & 0x02) |
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return 0; |
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*pSPI_CTL = 0; |
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if (ctrlc()) { |
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puts("\nAbort\n"); |
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return -1; |
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} |
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} |
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bfin_write_DMA_SPI_CONFIG(0); |
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puts("Timeout\n"); |
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return -1; |
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*pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); |
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return 0; |
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} |
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#endif |
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static long address_to_sector(unsigned long address) |
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{ |
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Wolfgang Denk
16 years ago