Wolfgang Denk
17 years ago
commit
2c78febd11
@ -0,0 +1,112 @@ |
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/*
|
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* (C) Copyright 2000-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/immap.h> |
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#define PERIOD 13 /* system bus period in ns */ |
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#define SDRAM_TREFI 7800 /* in ns */ |
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int checkboard(void) |
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{ |
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puts("Board: "); |
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puts("Freescale MCF5275 EVB\n"); |
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return 0; |
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}; |
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|
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long int initdram(int board_type) |
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{ |
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volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM); |
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volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); |
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gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */ |
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|
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/* Set up chip select */ |
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sdp->sdbar0 = CFG_SDRAM_BASE; |
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sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V; |
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|
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/* Set up timing */ |
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sdp->sdcfg1 = 0x83711630; |
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sdp->sdcfg2 = 0x46770000; |
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|
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/* Enable clock */ |
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sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE; |
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/* Set precharge */ |
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sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; |
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/* Dummy write to start SDRAM */ |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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/* Send LEMR */ |
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sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR |
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| MCF_SDRAMC_SDMR_AD(0x0) |
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| MCF_SDRAMC_SDMR_CMD; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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|
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/* Send LMR */ |
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sdp->sdmr = 0x058d0000; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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/* Stop sending commands */ |
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sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); |
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/* Set precharge */ |
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sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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|
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/* Stop manual precharge, send 2 IREF */ |
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sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL); |
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sdp->sdcr |= MCF_SDRAMC_SDCR_IREF; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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|
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/* Write mode register, clear reset DLL */ |
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sdp->sdmr = 0x018d0000; |
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*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; |
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|
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/* Stop sending commands */ |
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sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); |
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sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN); |
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/* Turn on auto refresh, lock SDMR */ |
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sdp->sdcr = |
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MCF_SDRAMC_SDCR_CKE |
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| MCF_SDRAMC_SDCR_REF |
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| MCF_SDRAMC_SDCR_MUX(1) |
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/* 1 added to round up */ |
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| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) |
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| MCF_SDRAMC_SDCR_DQS_OE(0x3); |
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return CFG_SDRAM_SIZE * 1024 * 1024; |
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}; |
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int testdram(void) |
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{ |
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/* TODO: XXX XXX XXX */ |
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printf("DRAM test not implemented!\n"); |
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return (0); |
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} |
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@ -1,124 +0,0 @@ |
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/*
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* (C) Copyright 2000-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/m5271.h> |
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#include <asm/immap_5271.h> |
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int checkboard (void) { |
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puts ("Board: R5200 Ethernet Module\n"); |
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return 0; |
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}; |
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|
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long int initdram (int board_type) { |
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int i; |
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/*
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* Set CS2 pin to be SD_CS0 |
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*/ |
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mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS) |
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| MCF_GPIO_PAR_CS_PAR_CS2); |
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mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM) |
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| MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01)); |
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|
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/*
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* Check to see if the SDRAM has already been initialized |
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* by a run control tool |
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*/ |
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if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { |
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/*
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* Initialize DRAM Control Register: DCR |
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*/ |
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mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01) |
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| MCF_SDRAMC_DCR_RC(0x30)); |
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/*
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* Initialize DACR0 |
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*/ |
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mbar_writeLong(MCF_SDRAMC_DACR0, |
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MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
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| MCF_SDRAMC_DACRn_CASL(0) |
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| MCF_SDRAMC_DACRn_CBM(3) |
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| MCF_SDRAMC_DACRn_PS(2)); |
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/*
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* Initialize DMR0 |
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*/ |
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mbar_writeLong(MCF_SDRAMC_DMR0, |
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MCF_SDRAMC_DMRn_BAM_8M |
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| MCF_SDRAMC_DMRn_V); |
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/*
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* Set IP bit in DACR |
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*/ |
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) |
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| MCF_SDRAMC_DACRn_IP); |
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/*
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* Wait at least 20ns to allow banks to precharge |
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*/ |
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for (i = 0; i < 5; i++) |
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asm(" nop"); |
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/*
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* Write to this block to initiate precharge |
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*/ |
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*(u16 *)(CFG_SDRAM_BASE) = 0x9696; |
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/*
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* Set RE bit in DACR |
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*/ |
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) |
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| MCF_SDRAMC_DACRn_RE); |
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/*
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* Wait for at least 8 auto refresh cycles to occur |
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*/ |
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for (i = 0; i < 2000; i++) |
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asm(" nop"); |
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/*
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* Finish the configuration by issuing the MRS. |
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*/ |
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) |
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| MCF_SDRAMC_DACRn_MRS); |
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/*
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* Write to the SDRAM Mode Register |
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*/ |
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*(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696; |
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} |
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return CFG_SDRAM_SIZE * 1024 * 1024; |
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}; |
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int testdram (void) { |
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/* TODO: XXX XXX XXX */ |
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printf ("DRAM test not implemented!\n"); |
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return (0); |
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} |
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@ -0,0 +1,73 @@ |
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/*
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* |
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* (C) Copyright 2000-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <spi.h> |
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#if defined(CONFIG_CF_DSPI) |
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#include <asm/immap.h> |
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void dspi_init(void) |
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{ |
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; |
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gpio->par_dspi = GPIO_PAR_DSPI_PCS5_PCS5 | GPIO_PAR_DSPI_PCS2_PCS2 | |
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GPIO_PAR_DSPI_PCS1_PCS1 | GPIO_PAR_DSPI_PCS0_PCS0 | |
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GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | |
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GPIO_PAR_DSPI_SCK_SCK; |
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dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 | |
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DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 | |
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DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 | |
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DSPI_DMCR_CRXF | DSPI_DMCR_CTXF; |
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dspi->dctar0 = DSPI_DCTAR_TRSZ(7) | DSPI_DCTAR_CPOL | DSPI_DCTAR_CPHA | |
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DSPI_DCTAR_PCSSCK_1CLK | DSPI_DCTAR_PASC(0) | |
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DSPI_DCTAR_PDT(0) | DSPI_DCTAR_CSSCK(0) | |
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DSPI_DCTAR_ASC(0) | DSPI_DCTAR_PBR(0) | |
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DSPI_DCTAR_DT(1) | DSPI_DCTAR_BR(1); |
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} |
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void dspi_tx(int chipsel, u8 attrib, u16 data) |
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{ |
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; |
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while ((dspi->dsr & 0x0000F000) >= 4) ; |
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dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data; |
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} |
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u16 dspi_rx(void) |
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{ |
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volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; |
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while ((dspi->dsr & 0x000000F0) == 0) ; |
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return (dspi->drfr & 0xFFFF); |
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} |
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#endif /* CONFIG_HARD_SPI */ |
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@ -0,0 +1,469 @@ |
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/*
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* MCF5274/5 Internal Memory Map |
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* |
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* Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com> |
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* Based on work Copyright (c) 2003 Josef Baumgartner |
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* <josef.baumgartner@telex.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __IMMAP_5275__ |
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#define __IMMAP_5275__ |
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#define MMAP_SCM (CFG_MBAR + 0x00000000) |
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#define MMAP_SDRAM (CFG_MBAR + 0x00000040) |
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#define MMAP_FBCS (CFG_MBAR + 0x00000080) |
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#define MMAP_DMA0 (CFG_MBAR + 0x00000100) |
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#define MMAP_DMA1 (CFG_MBAR + 0x00000110) |
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#define MMAP_DMA2 (CFG_MBAR + 0x00000120) |
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#define MMAP_DMA3 (CFG_MBAR + 0x00000130) |
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#define MMAP_UART0 (CFG_MBAR + 0x00000200) |
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#define MMAP_UART1 (CFG_MBAR + 0x00000240) |
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#define MMAP_UART2 (CFG_MBAR + 0x00000280) |
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#define MMAP_I2C (CFG_MBAR + 0x00000300) |
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#define MMAP_QSPI (CFG_MBAR + 0x00000340) |
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000400) |
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000440) |
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#define MMAP_DTMR2 (CFG_MBAR + 0x00000480) |
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#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0) |
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#define MMAP_INTC0 (CFG_MBAR + 0x00000C00) |
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#define MMAP_INTC1 (CFG_MBAR + 0x00000D00) |
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#define MMAP_INTCACK (CFG_MBAR + 0x00000F00) |
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#define MMAP_FEC0 (CFG_MBAR + 0x00001000) |
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#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400) |
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#define MMAP_FEC1 (CFG_MBAR + 0x00001800) |
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#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00) |
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#define MMAP_GPIO (CFG_MBAR + 0x00100000) |
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#define MMAP_RCM (CFG_MBAR + 0x00110000) |
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#define MMAP_CCM (CFG_MBAR + 0x00110004) |
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#define MMAP_PLL (CFG_MBAR + 0x00120000) |
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#define MMAP_EPORT (CFG_MBAR + 0x00130000) |
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#define MMAP_WDOG (CFG_MBAR + 0x00140000) |
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#define MMAP_PIT0 (CFG_MBAR + 0x00150000) |
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#define MMAP_PIT1 (CFG_MBAR + 0x00160000) |
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#define MMAP_PIT2 (CFG_MBAR + 0x00170000) |
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#define MMAP_PIT3 (CFG_MBAR + 0x00180000) |
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#define MMAP_MDHA (CFG_MBAR + 0x00190000) |
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#define MMAP_RNG (CFG_MBAR + 0x001A0000) |
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#define MMAP_SKHA (CFG_MBAR + 0x001B0000) |
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#define MMAP_USB (CFG_MBAR + 0x001C0000) |
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#define MMAP_PWM0 (CFG_MBAR + 0x001D0000) |
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|
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/* System configuration registers
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*/ |
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typedef struct sys_ctrl { |
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u32 ipsbar; |
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u32 res1; |
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u32 rambar; |
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u32 res2; |
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u8 crsr; |
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u8 cwcr; |
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u8 lpicr; |
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u8 cwsr; |
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u8 res3[8]; |
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u32 mpark; |
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u8 mpr; |
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u8 res4[3]; |
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u8 pacr0; |
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u8 pacr1; |
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u8 pacr2; |
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u8 pacr3; |
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u8 pacr4; |
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u8 res5; |
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u8 pacr5; |
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u8 pacr6; |
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u8 pacr7; |
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u8 res6; |
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u8 pacr8; |
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u8 res7; |
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u8 gpacr; |
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u8 res8[3]; |
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} sysctrl_t; |
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/* SDRAM controller registers, offset: 0x040
|
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*/ |
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typedef struct sdram_ctrl { |
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u32 sdmr; |
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u32 sdcr; |
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u32 sdcfg1; |
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u32 sdcfg2; |
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u32 sdbar0; |
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u32 sdbmr0; |
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u32 sdbar1; |
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u32 sdbmr1; |
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} sdramctrl_t; |
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|
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/* Chip select module registers, offset: 0x080
|
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*/ |
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typedef struct cs_ctlr { |
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u16 ar0; |
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u16 res1; |
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u32 mr0; |
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u16 res2; |
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u16 cr0; |
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u16 ar1; |
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u16 res3; |
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u32 mr1; |
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u16 res4; |
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u16 cr1; |
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u16 ar2; |
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u16 res5; |
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u32 mr2; |
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u16 res6; |
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u16 cr2; |
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u16 ar3; |
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u16 res7; |
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u32 mr3; |
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u16 res8; |
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u16 cr3; |
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u16 ar4; |
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u16 res9; |
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u32 mr4; |
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u16 res10; |
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u16 cr4; |
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u16 ar5; |
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u16 res11; |
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u32 mr5; |
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u16 res12; |
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u16 cr5; |
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u16 ar6; |
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u16 res13; |
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u32 mr6; |
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u16 res14; |
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u16 cr6; |
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u16 ar7; |
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u16 res15; |
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u32 mr7; |
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u16 res16; |
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u16 cr7; |
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} csctrl_t; |
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|
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/* DMA module registers, offset 0x100
|
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*/ |
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typedef struct dma_ctrl { |
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u32 sar; |
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u32 dar; |
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u32 dsrbcr; |
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u32 dcr; |
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} dma_t; |
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|
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/* QSPI module registers, offset 0x340
|
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*/ |
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typedef struct qspi_ctrl { |
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u16 qmr; |
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u8 res1[2]; |
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u16 qdlyr; |
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u8 res2[2]; |
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u16 qwr; |
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u8 res3[2]; |
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u16 qir; |
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u8 res4[2]; |
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u16 qar; |
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u8 res5[2]; |
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u16 qdr; |
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u8 res6[2]; |
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} qspi_t; |
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|
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/* Interrupt module registers, offset 0xc00
|
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*/ |
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typedef struct int_ctrl { |
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u32 iprh0; |
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u32 iprl0; |
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u32 imrh0; |
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u32 imrl0; |
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u32 frch0; |
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u32 frcl0; |
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u8 irlr; |
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u8 iacklpr; |
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u8 res1[0x26]; |
||||
u8 icr0[64]; /* No ICR0, done this way for readability */ |
||||
u8 res2[0x60]; |
||||
u8 swiack0; |
||||
u8 res3[3]; |
||||
u8 Lniack0_1; |
||||
u8 res4[3]; |
||||
u8 Lniack0_2; |
||||
u8 res5[3]; |
||||
u8 Lniack0_3; |
||||
u8 res6[3]; |
||||
u8 Lniack0_4; |
||||
u8 res7[3]; |
||||
u8 Lniack0_5; |
||||
u8 res8[3]; |
||||
u8 Lniack0_6; |
||||
u8 res9[3]; |
||||
u8 Lniack0_7; |
||||
u8 res10[3]; |
||||
} int0_t; |
||||
|
||||
/* GPIO port registers
|
||||
*/ |
||||
typedef struct gpio_ctrl { |
||||
/* Port Output Data Registers */ |
||||
u8 podr_res1[4]; |
||||
u8 podr_busctl; |
||||
u8 podr_addr; |
||||
u8 podr_res2[2]; |
||||
u8 podr_cs; |
||||
u8 podr_res3; |
||||
u8 podr_fec0h; |
||||
u8 podr_fec0l; |
||||
u8 podr_feci2c; |
||||
u8 podr_qspi; |
||||
u8 podr_sdram; |
||||
u8 podr_timerh; |
||||
u8 podr_timerl; |
||||
u8 podr_uartl; |
||||
u8 podr_fec1h; |
||||
u8 podr_fec1l; |
||||
u8 podr_bs; |
||||
u8 podr_res4; |
||||
u8 podr_usbh; |
||||
u8 podr_usbl; |
||||
u8 podr_uarth; |
||||
u8 podr_res5[3]; |
||||
/* Port Data Direction Registers */ |
||||
u8 pddr_res1[4]; |
||||
u8 pddr_busctl; |
||||
u8 pddr_addr; |
||||
u8 pddr_res2[2]; |
||||
u8 pddr_cs; |
||||
u8 pddr_res3; |
||||
u8 pddr_fec0h; |
||||
u8 pddr_fec0l; |
||||
u8 pddr_feci2c; |
||||
u8 pddr_qspi; |
||||
u8 pddr_sdram; |
||||
u8 pddr_timerh; |
||||
u8 pddr_timerl; |
||||
u8 pddr_uartl; |
||||
u8 pddr_fec1h; |
||||
u8 pddr_fec1l; |
||||
u8 pddr_bs; |
||||
u8 pddr_res4; |
||||
u8 pddr_usbh; |
||||
u8 pddr_usbl; |
||||
u8 pddr_uarth; |
||||
u8 pddr_res5[3]; |
||||
/* Port Pin Data/Set Registers */ |
||||
u8 ppdsdr_res1[4]; |
||||
u8 ppdsdr_busctl; |
||||
u8 ppdsdr_addr; |
||||
u8 ppdsdr_res2[2]; |
||||
u8 ppdsdr_cs; |
||||
u8 ppdsdr_res3; |
||||
u8 ppdsdr_fec0h; |
||||
u8 ppdsdr_fec0l; |
||||
u8 ppdsdr_feci2c; |
||||
u8 ppdsdr_qspi; |
||||
u8 ppdsdr_sdram; |
||||
u8 ppdsdr_timerh; |
||||
u8 ppdsdr_timerl; |
||||
u8 ppdsdr_uartl; |
||||
u8 ppdsdr_fec1h; |
||||
u8 ppdsdr_fec1l; |
||||
u8 ppdsdr_bs; |
||||
u8 ppdsdr_res4; |
||||
u8 ppdsdr_usbh; |
||||
u8 ppdsdr_usbl; |
||||
u8 ppdsdr_uarth; |
||||
u8 ppdsdr_res5[3]; |
||||
/* Port Clear Output Data Registers */ |
||||
u8 pclrr_res1[4]; |
||||
u8 pclrr_busctl; |
||||
u8 pclrr_addr; |
||||
u8 pclrr_res2[2]; |
||||
u8 pclrr_cs; |
||||
u8 pclrr_res3; |
||||
u8 pclrr_fec0h; |
||||
u8 pclrr_fec0l; |
||||
u8 pclrr_feci2c; |
||||
u8 pclrr_qspi; |
||||
u8 pclrr_sdram; |
||||
u8 pclrr_timerh; |
||||
u8 pclrr_timerl; |
||||
u8 pclrr_uartl; |
||||
u8 pclrr_fec1h; |
||||
u8 pclrr_fec1l; |
||||
u8 pclrr_bs; |
||||
u8 pclrr_res4; |
||||
u8 pclrr_usbh; |
||||
u8 pclrr_usbl; |
||||
u8 pclrr_uarth; |
||||
u8 pclrr_res5[3]; |
||||
/* Pin Assignment Registers */ |
||||
u8 par_addr; |
||||
u8 par_cs; |
||||
u16 par_busctl; |
||||
u8 par_res1[2]; |
||||
u16 par_usb; |
||||
u8 par_fec0hl; |
||||
u8 par_fec1hl; |
||||
u16 par_timer; |
||||
u16 par_uart; |
||||
u16 par_qspi; |
||||
u16 par_sdram; |
||||
u16 par_feci2c; |
||||
u8 par_bs; |
||||
u8 par_res2[3]; |
||||
} gpio_t; |
||||
|
||||
|
||||
/* PWM module registers
|
||||
*/ |
||||
typedef struct pwm_ctrl { |
||||
u8 pwcr0; |
||||
u8 res1[3]; |
||||
u8 pwcr1; |
||||
u8 res2[3]; |
||||
u8 pwcr2; |
||||
u8 res3[7]; |
||||
u8 pwwd0; |
||||
u8 res4[3]; |
||||
u8 pwwd1; |
||||
u8 res5[3]; |
||||
u8 pwwd2; |
||||
u8 res6[7]; |
||||
} pwm_t; |
||||
|
||||
/* Watchdog registers
|
||||
*/ |
||||
typedef struct wdog_ctrl { |
||||
u16 wcr; |
||||
u16 wmr; |
||||
u16 wcntr; |
||||
u16 wsr; |
||||
u8 res4[114]; |
||||
} wdog_t; |
||||
|
||||
/* USB module registers
|
||||
*/ |
||||
typedef struct usb { |
||||
u16 res1; |
||||
u16 fnr; |
||||
u16 res2; |
||||
u16 fnmr; |
||||
u16 res3; |
||||
u16 rfmr; |
||||
u16 res4; |
||||
u16 rfmmr; |
||||
u8 res5[3]; |
||||
u8 far; |
||||
u32 asr; |
||||
u32 drr1; |
||||
u32 drr2; |
||||
u16 res6; |
||||
u16 specr; |
||||
u16 res7; |
||||
u16 ep0sr; |
||||
u32 iep0cfg; |
||||
u32 oep0cfg; |
||||
u32 ep1cfg; |
||||
u32 ep2cfg; |
||||
u32 ep3cfg; |
||||
u32 ep4cfg; |
||||
u32 ep5cfg; |
||||
u32 ep6cfg; |
||||
u32 ep7cfg; |
||||
u32 ep0ctl; |
||||
u16 res8; |
||||
u16 ep1ctl; |
||||
u16 res9; |
||||
u16 ep2ctl; |
||||
u16 res10; |
||||
u16 ep3ctl; |
||||
u16 res11; |
||||
u16 ep4ctl; |
||||
u16 res12; |
||||
u16 ep5ctl; |
||||
u16 res13; |
||||
u16 ep6ctl; |
||||
u16 res14; |
||||
u16 ep7ctl; |
||||
u32 ep0isr; |
||||
u16 res15; |
||||
u16 ep1isr; |
||||
u16 res16; |
||||
u16 ep2isr; |
||||
u16 res17; |
||||
u16 ep3isr; |
||||
u16 res18; |
||||
u16 ep4isr; |
||||
u16 res19; |
||||
u16 ep5isr; |
||||
u16 res20; |
||||
u16 ep6isr; |
||||
u16 res21; |
||||
u16 ep7isr; |
||||
u32 ep0imr; |
||||
u16 res22; |
||||
u16 ep1imr; |
||||
u16 res23; |
||||
u16 ep2imr; |
||||
u16 res24; |
||||
u16 ep3imr; |
||||
u16 res25; |
||||
u16 ep4imr; |
||||
u16 res26; |
||||
u16 ep5imr; |
||||
u16 res27; |
||||
u16 ep6imr; |
||||
u16 res28; |
||||
u16 ep7imr; |
||||
u32 ep0dr; |
||||
u32 ep1dr; |
||||
u32 ep2dr; |
||||
u32 ep3dr; |
||||
u32 ep4dr; |
||||
u32 ep5dr; |
||||
u32 ep6dr; |
||||
u32 ep7dr; |
||||
u16 res29; |
||||
u16 ep0dpr; |
||||
u16 res30; |
||||
u16 ep1dpr; |
||||
u16 res31; |
||||
u16 ep2dpr; |
||||
u16 res32; |
||||
u16 ep3dpr; |
||||
u16 res33; |
||||
u16 ep4dpr; |
||||
u16 res34; |
||||
u16 ep5dpr; |
||||
u16 res35; |
||||
u16 ep6dpr; |
||||
u16 res36; |
||||
u16 ep7dpr; |
||||
u8 res37[788]; |
||||
u8 cfgram[1024]; |
||||
} usb_t; |
||||
|
||||
/* PLL module registers
|
||||
*/ |
||||
typedef struct pll_ctrl { |
||||
u32 syncr; |
||||
u32 synsr; |
||||
} pll_t; |
||||
|
||||
typedef struct rcm { |
||||
u8 rcr; |
||||
u8 rsr; |
||||
} rcm_t; |
||||
|
||||
#endif /* __IMMAP_5275__ */ |
||||
@ -0,0 +1,241 @@ |
||||
/*
|
||||
* MCF5275 Internal Memory Map |
||||
* |
||||
* Copyright (C) 2003-2004, Greg Ungerer (gerg@snapgear.com) |
||||
* Copyright (C) 2004-2008 Arthur Shipkowski (art@videon-central.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __M5275_H__ |
||||
#define __M5275_H__ |
||||
|
||||
/*
|
||||
* Define the 5275 SIM register set addresses. These are similar, |
||||
* but not quite identical to the 5282 registers and offsets. |
||||
*/ |
||||
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ |
||||
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ |
||||
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
||||
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
||||
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
||||
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
||||
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
||||
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
||||
#define MCFINTC_IRLR 0x18 /* */ |
||||
#define MCFINTC_IACKL 0x19 /* */ |
||||
#define MCFINTC_ICR0 0x40 /* Base ICR register */ |
||||
|
||||
#define MCF_GPIO_PAR_UART 0x10007c |
||||
#define UART0_ENABLE_MASK 0x000f |
||||
#define UART1_ENABLE_MASK 0x00f0 |
||||
#define UART2_ENABLE_MASK 0x3f00 |
||||
|
||||
#define MCF_GPIO_PAR_FECI2C 0x100082 |
||||
#define PAR_SDA_ENABLE_MASK 0x0003 |
||||
#define PAR_SCL_ENABLE_MASK 0x000c |
||||
|
||||
#define MCFSIM_WRRR 0x140000 |
||||
#define MCFSIM_SDCR 0x40 |
||||
|
||||
/*********************************************************************
|
||||
* SDRAM Controller (SDRAMC) |
||||
*********************************************************************/ |
||||
|
||||
/* Register read/write macros */ |
||||
#define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040])) |
||||
#define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044])) |
||||
#define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) |
||||
#define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) |
||||
#define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) |
||||
#define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058])) |
||||
#define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) |
||||
#define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C])) |
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDMR */ |
||||
#define MCF_SDRAMC_SDMR_CMD (0x00010000) |
||||
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) |
||||
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) |
||||
#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) |
||||
#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) |
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCR */ |
||||
#define MCF_SDRAMC_SDCR_IPALL (0x00000002) |
||||
#define MCF_SDRAMC_SDCR_IREF (0x00000004) |
||||
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) |
||||
#define MCF_SDRAMC_SDCR_DQP_BP (0x00008000) |
||||
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) |
||||
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) |
||||
#define MCF_SDRAMC_SDCR_REF (0x10000000) |
||||
#define MCF_SDRAMC_SDCR_CKE (0x40000000) |
||||
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) |
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ |
||||
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) |
||||
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) |
||||
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) |
||||
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) |
||||
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) |
||||
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) |
||||
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) |
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ |
||||
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) |
||||
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) |
||||
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) |
||||
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) |
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDBARn */ |
||||
#define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18) |
||||
#define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000) |
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDMRn */ |
||||
#define MCF_SDRAMC_SDMRn_V (0x00000001) |
||||
#define MCF_SDRAMC_SDMRn_WP (0x00000080) |
||||
#define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18) |
||||
#define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000) |
||||
#define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000) |
||||
|
||||
/*********************************************************************
|
||||
* Interrupt Controller (INTC) |
||||
********************************************************************/ |
||||
#define INT0_LO_RSVD0 (0) |
||||
#define INT0_LO_EPORT1 (1) |
||||
#define INT0_LO_EPORT2 (2) |
||||
#define INT0_LO_EPORT3 (3) |
||||
#define INT0_LO_EPORT4 (4) |
||||
#define INT0_LO_EPORT5 (5) |
||||
#define INT0_LO_EPORT6 (6) |
||||
#define INT0_LO_EPORT7 (7) |
||||
#define INT0_LO_SCM (8) |
||||
#define INT0_LO_DMA0 (9) |
||||
#define INT0_LO_DMA1 (10) |
||||
#define INT0_LO_DMA2 (11) |
||||
#define INT0_LO_DMA3 (12) |
||||
#define INT0_LO_UART0 (13) |
||||
#define INT0_LO_UART1 (14) |
||||
#define INT0_LO_UART2 (15) |
||||
#define INT0_LO_RSVD1 (16) |
||||
#define INT0_LO_I2C (17) |
||||
#define INT0_LO_QSPI (18) |
||||
#define INT0_LO_DTMR0 (19) |
||||
#define INT0_LO_DTMR1 (20) |
||||
#define INT0_LO_DTMR2 (21) |
||||
#define INT0_LO_DTMR3 (22) |
||||
#define INT0_LO_FEC0_TXF (23) |
||||
#define INT0_LO_FEC0_TXB (24) |
||||
#define INT0_LO_FEC0_UN (25) |
||||
#define INT0_LO_FEC0_RL (26) |
||||
#define INT0_LO_FEC0_RXF (27) |
||||
#define INT0_LO_FEC0_RXB (28) |
||||
#define INT0_LO_FEC0_MII (29) |
||||
#define INT0_LO_FEC0_LC (30) |
||||
#define INT0_LO_FEC0_HBERR (31) |
||||
#define INT0_HI_FEC0_GRA (32) |
||||
#define INT0_HI_FEC0_EBERR (33) |
||||
#define INT0_HI_FEC0_BABT (34) |
||||
#define INT0_HI_FEC0_BABR (35) |
||||
#define INT0_HI_PIT0 (36) |
||||
#define INT0_HI_PIT1 (37) |
||||
#define INT0_HI_PIT2 (38) |
||||
#define INT0_HI_PIT3 (39) |
||||
#define INT0_HI_RNG (40) |
||||
#define INT0_HI_SKHA (41) |
||||
#define INT0_HI_MDHA (42) |
||||
#define INT0_HI_USB (43) |
||||
#define INT0_HI_USB_EP0 (44) |
||||
#define INT0_HI_USB_EP1 (45) |
||||
#define INT0_HI_USB_EP2 (46) |
||||
#define INT0_HI_USB_EP3 (47) |
||||
/* 48-63 Reserved */ |
||||
|
||||
/* 0-22 Reserved */ |
||||
#define INT1_LO_FEC1_TXF (23) |
||||
#define INT1_LO_FEC1_TXB (24) |
||||
#define INT1_LO_FEC1_UN (25) |
||||
#define INT1_LO_FEC1_RL (26) |
||||
#define INT1_LO_FEC1_RXF (27) |
||||
#define INT1_LO_FEC1_RXB (28) |
||||
#define INT1_LO_FEC1_MII (29) |
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#define INT1_LO_FEC1_LC (30) |
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#define INT1_LO_FEC1_HBERR (31) |
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#define INT1_HI_FEC1_GRA (32) |
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#define INT1_HI_FEC1_EBERR (33) |
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#define INT1_HI_FEC1_BABT (34) |
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#define INT1_HI_FEC1_BABR (35) |
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/* 36-63 Reserved */ |
||||
|
||||
/* Bit definitions and macros for INTC_IPRL */ |
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#define INTC_IPRL_INT31 (0x80000000) |
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#define INTC_IPRL_INT30 (0x40000000) |
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#define INTC_IPRL_INT29 (0x20000000) |
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#define INTC_IPRL_INT28 (0x10000000) |
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#define INTC_IPRL_INT27 (0x08000000) |
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#define INTC_IPRL_INT26 (0x04000000) |
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#define INTC_IPRL_INT25 (0x02000000) |
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#define INTC_IPRL_INT24 (0x01000000) |
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#define INTC_IPRL_INT23 (0x00800000) |
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#define INTC_IPRL_INT22 (0x00400000) |
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#define INTC_IPRL_INT21 (0x00200000) |
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#define INTC_IPRL_INT20 (0x00100000) |
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#define INTC_IPRL_INT19 (0x00080000) |
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#define INTC_IPRL_INT18 (0x00040000) |
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#define INTC_IPRL_INT17 (0x00020000) |
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#define INTC_IPRL_INT16 (0x00010000) |
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#define INTC_IPRL_INT15 (0x00008000) |
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#define INTC_IPRL_INT14 (0x00004000) |
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#define INTC_IPRL_INT13 (0x00002000) |
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#define INTC_IPRL_INT12 (0x00001000) |
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#define INTC_IPRL_INT11 (0x00000800) |
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#define INTC_IPRL_INT10 (0x00000400) |
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#define INTC_IPRL_INT9 (0x00000200) |
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#define INTC_IPRL_INT8 (0x00000100) |
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#define INTC_IPRL_INT7 (0x00000080) |
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#define INTC_IPRL_INT6 (0x00000040) |
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#define INTC_IPRL_INT5 (0x00000020) |
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#define INTC_IPRL_INT4 (0x00000010) |
||||
#define INTC_IPRL_INT3 (0x00000008) |
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#define INTC_IPRL_INT2 (0x00000004) |
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#define INTC_IPRL_INT1 (0x00000002) |
||||
#define INTC_IPRL_INT0 (0x00000001) |
||||
|
||||
/* Bit definitions and macros for RCR */ |
||||
#define RCM_RCR_FRCRSTOUT (0x40) |
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#define RCM_RCR_SOFTRST (0x80) |
||||
|
||||
#define FMPLL_SYNSR_LOCK (0x00000008) |
||||
|
||||
#endif /* __M5275_H__ */ |
||||
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Reference in new issue