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@ -81,6 +81,7 @@ |
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#include <common.h> |
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#include <net.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <commproc.h> |
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#include <ppc4xx.h> |
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#include <ppc4xx_enet.h> |
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@ -221,7 +222,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) |
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unsigned long mfr; |
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#endif |
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out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ |
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out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ |
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/* 1st reset MAL channel */ |
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/* Note: writing a 0 to a channel has no effect */ |
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@ -250,7 +251,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) |
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mtsdr(sdr_mfr, mfr); |
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#endif |
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out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
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out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
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#if defined(CONFIG_440SPE) || \ |
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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@ -353,8 +354,8 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
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/* Ensure we setup mdio for this devnum and ONLY this devnum */ |
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zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); |
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out32 (ZMII_FER, zmiifer); |
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out32 (RGMII_FER, rmiifer); |
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out_be32(ZMII_FER, zmiifer); |
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out_be32(RGMII_FER, rmiifer); |
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return ((int)pfc1); |
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} |
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@ -372,31 +373,31 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
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switch (pfc1) { |
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case SDR0_PFC1_SELECT_CONFIG_2: |
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/* 1 x GMII port */ |
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out32 (ZMII_FER, 0x00); |
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out32 (RGMII_FER, 0x00000037); |
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out_be32((void *)ZMII_FER, 0x00); |
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out_be32((void *)RGMII_FER, 0x00000037); |
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bis->bi_phymode[0] = BI_PHYMODE_GMII; |
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bis->bi_phymode[1] = BI_PHYMODE_NONE; |
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break; |
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case SDR0_PFC1_SELECT_CONFIG_4: |
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/* 2 x RGMII ports */ |
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out32 (ZMII_FER, 0x00); |
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out32 (RGMII_FER, 0x00000055); |
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out_be32((void *)ZMII_FER, 0x00); |
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out_be32((void *)RGMII_FER, 0x00000055); |
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bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
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bis->bi_phymode[1] = BI_PHYMODE_RGMII; |
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break; |
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case SDR0_PFC1_SELECT_CONFIG_6: |
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/* 2 x SMII ports */ |
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out32 (ZMII_FER, |
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((ZMII_FER_SMII) << ZMII_FER_V(0)) | |
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((ZMII_FER_SMII) << ZMII_FER_V(1))); |
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out32 (RGMII_FER, 0x00000000); |
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out_be32((void *)ZMII_FER, |
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((ZMII_FER_SMII) << ZMII_FER_V(0)) | |
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((ZMII_FER_SMII) << ZMII_FER_V(1))); |
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out_be32((void *)RGMII_FER, 0x00000000); |
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bis->bi_phymode[0] = BI_PHYMODE_SMII; |
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bis->bi_phymode[1] = BI_PHYMODE_SMII; |
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break; |
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case SDR0_PFC1_SELECT_CONFIG_1_2: |
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/* only 1 x MII supported */ |
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out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); |
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out32 (RGMII_FER, 0x00000000); |
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out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); |
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out_be32((void *)RGMII_FER, 0x00000000); |
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bis->bi_phymode[0] = BI_PHYMODE_MII; |
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bis->bi_phymode[1] = BI_PHYMODE_NONE; |
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break; |
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@ -405,9 +406,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
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} |
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/* Ensure we setup mdio for this devnum and ONLY this devnum */ |
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zmiifer = in32 (ZMII_FER); |
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zmiifer = in_be32((void *)ZMII_FER); |
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zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); |
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out32 (ZMII_FER, zmiifer); |
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out_be32((void *)ZMII_FER, zmiifer); |
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return ((int)0x0); |
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} |
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@ -425,7 +426,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
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switch (1) { |
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case 1: |
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/* 2 x RGMII ports */ |
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out32 (RGMII_FER, 0x00000055); |
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out_be32((void *)RGMII_FER, 0x00000055); |
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bis->bi_phymode[0] = BI_PHYMODE_RGMII; |
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bis->bi_phymode[1] = BI_PHYMODE_RGMII; |
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break; |
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@ -437,9 +438,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) |
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} |
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/* Ensure we setup mdio for this devnum and ONLY this devnum */ |
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gmiifer = in32(RGMII_FER); |
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gmiifer = in_be32((void *)RGMII_FER); |
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gmiifer |= (1 << (19-devnum)); |
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out32 (RGMII_FER, gmiifer); |
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out_be32((void *)RGMII_FER, gmiifer); |
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return ((int)0x0); |
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} |
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@ -535,27 +536,27 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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/* NOTE: Therefore, disable all other EMACS, since we handle */ |
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/* NOTE: only one emac at a time */ |
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reg = 0; |
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out32 (ZMII_FER, 0); |
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out_be32((void *)ZMII_FER, 0); |
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udelay (100); |
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
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out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
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out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
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#elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
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ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
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#elif defined(CONFIG_440GP) |
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/* set RMII mode */ |
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out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); |
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out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0); |
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#else |
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if ((devnum == 0) || (devnum == 1)) { |
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out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
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out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); |
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} else { /* ((devnum == 2) || (devnum == 3)) */ |
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out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); |
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out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | |
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(RGMII_FER_RGMII << RGMII_FER_V (3)))); |
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out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); |
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out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | |
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(RGMII_FER_RGMII << RGMII_FER_V (3)))); |
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} |
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#endif |
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out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); |
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out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); |
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#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
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#if defined(CONFIG_405EX) |
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ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); |
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@ -573,11 +574,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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mtsdr(sdr_mfr, mfr); |
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#endif |
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out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
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__asm__ volatile ("eieio"); |
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out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); |
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failsafe = 1000; |
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while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { |
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while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { |
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udelay (1000); |
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failsafe--; |
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} |
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@ -610,7 +610,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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else |
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mode_reg |= EMAC_M1_OBCI_GT100; |
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out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); |
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out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); |
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#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ |
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/* wait for PHY to complete auto negotiation */ |
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@ -768,11 +768,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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#endif |
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/* Set ZMII/RGMII speed according to the phy link speed */ |
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reg = in32 (ZMII_SSR); |
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reg = in_be32(ZMII_SSR); |
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if ( (speed == 100) || (speed == 1000) ) |
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out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); |
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out_be32(ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); |
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else |
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out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); |
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out_be32(ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); |
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if ((devnum == 2) || (devnum == 3)) { |
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if (speed == 1000) |
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@ -785,7 +785,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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printf("Error in RGMII Speed\n"); |
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return -1; |
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} |
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out32 (RGMII_SSR, reg); |
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out_be32(RGMII_SSR, reg); |
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} |
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#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ |
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@ -801,7 +801,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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printf("Error in RGMII Speed\n"); |
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return -1; |
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} |
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out32 (RGMII_SSR, reg); |
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out_be32((void *)RGMII_SSR, reg); |
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#endif |
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/* set the Mal configuration reg */ |
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@ -912,7 +912,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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reg = reg << 8; |
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reg |= dev->enetaddr[1]; |
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out32 (EMAC_IAH + hw_p->hw_addr, reg); |
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out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); |
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reg = 0x00000000; |
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reg |= dev->enetaddr[2]; /* set low address */ |
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@ -923,7 +923,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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reg = reg << 8; |
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reg |= dev->enetaddr[5]; |
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out32 (EMAC_IAL + hw_p->hw_addr, reg); |
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out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); |
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switch (devnum) { |
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case 1: |
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@ -984,10 +984,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); |
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/* set transmit enable & receive enable */ |
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out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); |
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out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); |
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/* set receive fifo to 4k and tx fifo to 2k */ |
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mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); |
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mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); |
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mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; |
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/* set speed */ |
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@ -1008,39 +1008,39 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) |
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if (duplex == FULL) |
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mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; |
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out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); |
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out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); |
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/* Enable broadcast and indvidual address */ |
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/* TBS: enabling runts as some misbehaved nics will send runts */ |
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out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); |
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out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); |
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/* we probably need to set the tx mode1 reg? maybe at tx time */ |
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/* set transmit request threshold register */ |
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out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ |
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out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ |
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/* set receive low/high water mark register */ |
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#if defined(CONFIG_440) |
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/* 440s has a 64 byte burst length */ |
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out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); |
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out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); |
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#else |
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/* 405s have a 16 byte burst length */ |
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out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); |
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out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); |
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#endif /* defined(CONFIG_440) */ |
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out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); |
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out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); |
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/* Set fifo limit entry in tx mode 0 */ |
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out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); |
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out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); |
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/* Frame gap set */ |
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out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); |
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out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); |
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/* Set EMAC IER */ |
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hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; |
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if (speed == _100BASET) |
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hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; |
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out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ |
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out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); |
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out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ |
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out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); |
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if (hw_p->first_init == 0) { |
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/*
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@ -1098,8 +1098,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, |
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__asm__ volatile ("eieio"); |
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out32 (EMAC_TXM0 + hw_p->hw_addr, |
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in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); |
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out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, |
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in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); |
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#ifdef INFO_4XX_ENET |
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hw_p->stats.pkts_tx++; |
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#endif |
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@ -1109,7 +1109,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, |
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*-----------------------------------------------------------------------*/ |
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time_start = get_timer (0); |
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while (1) { |
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temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); |
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temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); |
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/* loop until either TINT turns on or 3 seconds elapse */ |
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if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { |
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/* transmit is done, so now check for errors
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@ -1218,7 +1218,7 @@ int enetInt (struct eth_device *dev) |
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/* port by port dispatch of emac interrupts */ |
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if (hw_p->devnum == 0) { |
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if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ |
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emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
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emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
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if ((hw_p->emac_ier & emac_isr) != 0) { |
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emac_err (dev, emac_isr); |
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serviced = 1; |
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@ -1237,7 +1237,7 @@ int enetInt (struct eth_device *dev) |
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#if !defined(CONFIG_440SP) |
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if (hw_p->devnum == 1) { |
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if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ |
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emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
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emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
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if ((hw_p->emac_ier & emac_isr) != 0) { |
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emac_err (dev, emac_isr); |
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serviced = 1; |
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@ -1255,7 +1255,7 @@ int enetInt (struct eth_device *dev) |
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#if defined (CONFIG_440GX) |
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if (hw_p->devnum == 2) { |
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if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ |
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emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
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emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
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if ((hw_p->emac_ier & emac_isr) != 0) { |
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emac_err (dev, emac_isr); |
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serviced = 1; |
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@ -1273,7 +1273,7 @@ int enetInt (struct eth_device *dev) |
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if (hw_p->devnum == 3) { |
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if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ |
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emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
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emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
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if ((hw_p->emac_ier & emac_isr) != 0) { |
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emac_err (dev, emac_isr); |
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serviced = 1; |
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@ -1385,7 +1385,7 @@ int enetInt (struct eth_device *dev) |
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/* port by port dispatch of emac interrupts */ |
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if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ |
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emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); |
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emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); |
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if ((hw_p->emac_ier & emac_isr) != 0) { |
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emac_err (dev, emac_isr); |
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serviced = 1; |
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@ -1459,7 +1459,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr) |
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EMAC_4XX_HW_PST hw_p = dev->priv; |
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printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); |
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out32 (EMAC_ISR + hw_p->hw_addr, isr); |
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out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); |
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} |
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/*-----------------------------------------------------------------------------+
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