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@ -31,18 +31,32 @@ |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/sys_info.h> |
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#include <asm/arch/mem.h> |
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#include <i2c.h> |
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#include <asm/mach-types.h> |
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void wait_for_command_complete(unsigned int wd_base); |
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DECLARE_GLOBAL_DATA_PTR; |
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#define write_config_reg(reg, value) \ |
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do { \
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writeb(value, reg); \
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} while (0) |
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#define mask_config_reg(reg, mask) \ |
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do { \
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char value = readb(reg) & ~(mask); \
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writeb(value, reg); \
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} while (0) |
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/*******************************************************
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* Routine: delay |
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* Description: spinning delay to use before udelay works |
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******************************************************/ |
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static inline void delay(unsigned long loops) { |
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__asm__ volatile ("1:\n" "subs %0, %1, #1\n" |
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"bne 1b":"=r" (loops):"0"(loops)); } |
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******************************************************/ |
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static inline void delay(unsigned long loops) |
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{ |
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__asm__("1:\n" "subs %0, %1, #1\n" |
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"bne 1b":"=r" (loops):"0"(loops)); |
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} |
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/*****************************************
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* Routine: board_init |
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@ -50,8 +64,6 @@ static inline void delay(unsigned long loops) { |
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*****************************************/ |
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int board_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gpmc_init(); /* in SRAM or SDRM, finish GPMC */ |
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gd->bd->bi_arch_number = 919; |
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@ -68,7 +80,6 @@ int board_init(void) |
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**********************************************************/ |
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void s_init(void) |
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{ |
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watchdog_init(); |
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set_muxconf_regs(); |
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delay(100); |
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@ -80,7 +91,7 @@ void s_init(void) |
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/*******************************************************
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* Routine: misc_init_r |
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* Description: Init ethernet (done here so udelay works) |
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********************************************************/ |
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********************************************************/ |
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int misc_init_r(void) |
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{ |
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ether_init(); /* better done here so timers are init'ed */ |
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@ -102,22 +113,24 @@ void watchdog_init(void) |
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__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); |
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#define MPU_WD_CLOCKED 1 |
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#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */ |
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#if MPU_WD_CLOCKED |
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/* value 0x10 stick on aptix, BIT4 polarity seems oppsite */ |
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__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR); |
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wait_for_command_complete(WD3_BASE); |
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__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR); |
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__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR); |
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wait_for_command_complete(WD4_BASE); |
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__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
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#endif |
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__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR); |
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#endif |
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} |
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/******************************************************
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* Routine: wait_for_command_complete |
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* Description: Wait for posting to finish on watchdog |
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******************************************************/ |
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void wait_for_command_complete(unsigned int wd_base) { |
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******************************************************/ |
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void wait_for_command_complete(unsigned int wd_base) |
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{ |
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int pending = 1; |
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do { |
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pending = __raw_readl(wd_base + WWPS); |
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@ -160,7 +173,7 @@ void ether_init(void) |
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} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); |
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udelay(1000); |
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*((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; |
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mask_config_reg(ETH_CONTROL_REG, 0x01); |
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udelay(1000); |
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eth_reset_err_out: |
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@ -171,10 +184,9 @@ eth_reset_err_out: |
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/**********************************************
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* Routine: dram_init |
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* Description: sets uboots idea of sdram size |
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**********************************************/ |
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**********************************************/ |
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int dram_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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unsigned int size0 = 0, size1 = 0; |
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u32 mtype, btype, rev = 0, cpu = 0; |
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#define NOT_EARLY 0 |
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@ -187,8 +199,8 @@ int dram_init(void) |
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display_board_info(btype); |
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if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { |
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printf("ddr combo\n"); |
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do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */ |
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/* init other chip select */ |
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do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); |
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} |
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size0 = get_sdr_cs_size(SDRC_CS0_OSET); |
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@ -224,7 +236,7 @@ void set_muxconf_regs(void) |
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/*****************************************************************
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* Routine: peripheral_enable |
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* Description: Enable the clks & power for perifs (GPT2, UART1,...) |
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******************************************************************/ |
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******************************************************************/ |
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void peripheral_enable(void) |
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{ |
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unsigned int v, if_clks = 0, func_clks = 0; |
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@ -232,7 +244,8 @@ void peripheral_enable(void) |
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/* Enable GP2 timer. */ |
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if_clks |= BIT4 | BIT3; |
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func_clks |= BIT4 | BIT3; |
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v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2; /* Sys_clk input OMAP2420_GPT2 */ |
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/* Sys_clk input OMAP2420_GPT2 */ |
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v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2; |
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__raw_writel(v, CM_CLKSEL2_CORE); |
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__raw_writel(0x1, CM_CLKSEL_WKUP); |
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@ -241,9 +254,11 @@ void peripheral_enable(void) |
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func_clks |= BIT21; |
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if_clks |= BIT21; |
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#endif |
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v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ |
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/* Interface clocks on */ |
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v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; |
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__raw_writel(v, CM_ICLKEN1_CORE); |
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v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ |
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/* Functional Clocks on */ |
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v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; |
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__raw_writel(v, CM_FCLKEN1_CORE); |
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delay(1000); |
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@ -261,199 +276,110 @@ void peripheral_enable(void) |
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} |
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/****************************************
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* Routine: muxSetupUsb0 (ostboot) |
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* Routine: muxSetupUsb0 (ostboot) |
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* Description: Setup usb muxing |
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*****************************************/ |
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void muxSetupUsb0(void) |
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{ |
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volatile uint8 *MuxConfigReg; |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN; |
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*MuxConfigReg &= (uint8) (~0x1F); |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP; |
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*MuxConfigReg &= (uint8) (~0x1F); |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM; |
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*MuxConfigReg &= (uint8) (~0x1F); |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV; |
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*MuxConfigReg &= (uint8) (~0x1F); |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN; |
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*MuxConfigReg &= (uint8) (~0x1F); |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0; |
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*MuxConfigReg &= (uint8) (~0x1F); |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT; |
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*MuxConfigReg &= (uint8) (~0x1F); |
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mask_config_reg(CONTROL_PADCONF_USB0_PUEN, 0x1f); |
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mask_config_reg(CONTROL_PADCONF_USB0_VP, 0x1f); |
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mask_config_reg(CONTROL_PADCONF_USB0_VM, 0x1f); |
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mask_config_reg(CONTROL_PADCONF_USB0_RCV, 0x1f); |
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mask_config_reg(CONTROL_PADCONF_USB0_TXEN, 0x1f); |
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mask_config_reg(CONTROL_PADCONF_USB0_SE0, 0x1f); |
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mask_config_reg(CONTROL_PADCONF_USB0_DAT, 0x1f); |
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} |
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#define CONTROL_PADCONF_USB1_RCV ((volatile uint8 *)0x480000EB) |
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#define CONTROL_PADCONF_USB1_TXEN ((volatile uint8 *)0x480000EC) |
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#define CONTROL_PADCONF_GPIO69 ((volatile uint8 *)0x480000ED) |
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#define CONTROL_PADCONF_GPIO70 ((volatile uint8 *)0x480000EE) |
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#define CONTROL_PADCONF_GPIO102 ((volatile uint8 *)0x48000116) |
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#define CONTROL_PADCONF_GPIO103 ((volatile uint8 *)0x48000117) |
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#define CONTROL_PADCONF_GPIO104 ((volatile uint8 *)0x48000118) |
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#define CONTROL_PADCONF_GPIO105 ((volatile uint8 *)0x48000119) |
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/****************************************
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* Routine: muxSetupUSBHost (ostboot) |
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* Routine: muxSetupUSBHost (ostboot) |
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* Description: Setup USB Host muxing |
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*****************************************/ |
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void muxSetupUsbHost(void) |
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{ |
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volatile uint8 *MuxConfigReg; |
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/* V19 */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_RCV; |
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*MuxConfigReg = 1; |
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write_config_reg(CONTROL_PADCONF_USB1_RCV, 1); |
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/* W20 */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_TXEN; |
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*MuxConfigReg = 1; |
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write_config_reg(CONTROL_PADCONF_USB1_TXEN, 1); |
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/* N14 */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO69; |
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*MuxConfigReg = 3; |
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write_config_reg(CONTROL_PADCONF_GPIO69, 3); |
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/* P15 */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO70; |
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*MuxConfigReg = 3; |
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write_config_reg(CONTROL_PADCONF_GPIO70, 3); |
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/* L18 */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO102; |
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*MuxConfigReg = 3; |
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write_config_reg(CONTROL_PADCONF_GPIO102, 3); |
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/* L19 */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO103; |
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*MuxConfigReg = 3; |
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write_config_reg(CONTROL_PADCONF_GPIO103, 3); |
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/* K15 */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO104; |
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*MuxConfigReg = 3; |
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write_config_reg(CONTROL_PADCONF_GPIO104, 3); |
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/* K14 */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO105; |
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*MuxConfigReg = 3; |
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write_config_reg(CONTROL_PADCONF_GPIO105, 3); |
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} |
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/****************************************
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* Routine: muxSetupUART1 (ostboot) |
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* Routine: muxSetupUART1 (ostboot) |
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* Description: Set up uart1 muxing |
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*****************************************/ |
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void muxSetupUART1(void) |
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{ |
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volatile unsigned char *MuxConfigReg; |
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/* UART1_CTS pin configuration, PIN = D21 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
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/* UART1_RTS pin configuration, PIN = H21 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
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/* UART1_TX pin configuration, PIN = L20 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
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/* UART1_RX pin configuration, PIN = T21 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
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/* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */ |
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write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); |
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/* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */ |
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write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); |
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/* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */ |
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write_config_reg(CONTROL_PADCONF_UART1_TX, 0); |
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/* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */ |
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write_config_reg(CONTROL_PADCONF_UART1_RX, 0); |
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} |
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/****************************************
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* Routine: muxSetupLCD (ostboot) |
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* Routine: muxSetupLCD (ostboot) |
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* Description: Setup lcd muxing |
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*****************************************/ |
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void muxSetupLCD(void) |
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{ |
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volatile unsigned char *MuxConfigReg; |
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/* LCD_D0 pin configuration, PIN = Y7 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
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/* LCD_D1 pin configuration, PIN = P10 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
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/* LCD_D2 pin configuration, PIN = V8 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
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/* LCD_D3 pin configuration, PIN = Y8 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
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/* LCD_D4 pin configuration, PIN = W8 */ |
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4; |
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D5 pin configuration, PIN = R10 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D6 pin configuration, PIN = Y9 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D7 pin configuration, PIN = V9 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D8 pin configuration, PIN = W9 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D9 pin configuration, PIN = P11 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D10 pin configuration, PIN = V10 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D11 pin configuration, PIN = Y10 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D12 pin configuration, PIN = W10 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D13 pin configuration, PIN = R11 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D14 pin configuration, PIN = V11 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D15 pin configuration, PIN = W11 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D16 pin configuration, PIN = P12 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_D17 pin configuration, PIN = R12 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_PCLK pin configuration, PIN = W6 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_VSYNC pin configuration, PIN = V7 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_HSYNC pin configuration, PIN = Y6 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* LCD_ACBIAS pin configuration, PIN = W7 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
/* LCD_D0 pin configuration, PIN = Y7, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D0, 0); |
|
|
|
|
/* LCD_D1 pin configuration, PIN = P10 , Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D1, 0); |
|
|
|
|
/* LCD_D2 pin configuration, PIN = V8, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D2, 0); |
|
|
|
|
/* LCD_D3 pin configuration, PIN = Y8, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D3, 0); |
|
|
|
|
/* LCD_D4 pin configuration, PIN = W8, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D4, 0); |
|
|
|
|
/* LCD_D5 pin configuration, PIN = R10, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D5, 0); |
|
|
|
|
/* LCD_D6 pin configuration, PIN = Y9, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D6, 0); |
|
|
|
|
/* LCD_D7 pin configuration, PIN = V9, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D7, 0); |
|
|
|
|
/* LCD_D8 pin configuration, PIN = W9, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D8, 0); |
|
|
|
|
/* LCD_D9 pin configuration, PIN = P11, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D9, 0); |
|
|
|
|
/* LCD_D10 pin configuration, PIN = V10, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D10, 0); |
|
|
|
|
/* LCD_D11 pin configuration, PIN = Y10, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D11, 0); |
|
|
|
|
/* LCD_D12 pin configuration, PIN = W10, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D12, 0); |
|
|
|
|
/* LCD_D13 pin configuration, PIN = R11, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D13, 0); |
|
|
|
|
/* LCD_D14 pin configuration, PIN = V11, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D14, 0); |
|
|
|
|
/* LCD_D15 pin configuration, PIN = W11, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D15, 0); |
|
|
|
|
/* LCD_D16 pin configuration, PIN = P12, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D16, 0); |
|
|
|
|
/* LCD_D17 pin configuration, PIN = R12, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_D17, 0); |
|
|
|
|
/* LCD_PCLK pin configuration, PIN = W6, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_PCLK, 0); |
|
|
|
|
/* LCD_VSYNC pin configuration, PIN = V7, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_VSYNC, 0); |
|
|
|
|
/* LCD_HSYNC pin configuration, PIN = Y6, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_HSYNC, 0); |
|
|
|
|
/* LCD_ACBIAS pin configuration, PIN = W7, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_DSS_ACBIAS, 0); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/****************************************
|
|
|
|
@ -462,146 +388,84 @@ void muxSetupLCD(void) |
|
|
|
|
*****************************************/ |
|
|
|
|
void muxSetupMMCSD(void) |
|
|
|
|
{ |
|
|
|
|
volatile unsigned char *MuxConfigReg; |
|
|
|
|
|
|
|
|
|
/* SDMMC_CLKI pin configuration, PIN = H15 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_CLKO pin configuration, PIN = G19 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_CMD pin configuration, PIN = H18 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
/* External pull-ups are present. */ |
|
|
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_DAT0 pin configuration, PIN = F20 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
/* External pull-ups are present. */ |
|
|
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_DAT1 pin configuration, PIN = H14 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
/* External pull-ups are present. */ |
|
|
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_DAT2 pin configuration, PIN = E19 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
/* External pull-ups are present. */ |
|
|
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_DAT3 pin configuration, PIN = D19 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
/* External pull-ups are present. */ |
|
|
|
|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_DDIR0 pin configuration, PIN = F19 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_DDIR1 pin configuration, PIN = E20 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_DDIR2 pin configuration, PIN = F18 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_DDIR3 pin configuration, PIN = E18 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SDMMC_CDIR pin configuration, PIN = G18 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
/* SDMMC_CLKI pin configuration, PIN = H15, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_CLKI, 0); |
|
|
|
|
/* SDMMC_CLKO pin configuration, PIN = G19, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_CLKO, 0); |
|
|
|
|
/* SDMMC_CMD pin configuration, PIN = H18, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_CMD, 0); |
|
|
|
|
/* SDMMC_DAT0 pin configuration, PIN = F20, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_DAT0, 0); |
|
|
|
|
/* SDMMC_DAT1 pin configuration, PIN = H14, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_DAT1, 0); |
|
|
|
|
/* SDMMC_DAT2 pin configuration, PIN = E19, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_DAT2, 0); |
|
|
|
|
/* SDMMC_DAT3 pin configuration, PIN = D19, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_DAT3, 0); |
|
|
|
|
/* SDMMC_DDIR0 pin configuration, PIN = F19, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR0, 0); |
|
|
|
|
/* SDMMC_DDIR1 pin configuration, PIN = E20, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR1, 0); |
|
|
|
|
/* SDMMC_DDIR2 pin configuration, PIN = F18, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR2, 0); |
|
|
|
|
/* SDMMC_DDIR3 pin configuration, PIN = E18, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_DAT_DIR3, 0); |
|
|
|
|
/* SDMMC_CDIR pin configuration, PIN = G18, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_MMC_CMD_DIR, 0); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/******************************************
|
|
|
|
|
* Routine: muxSetupTouchScreen (ostboot) |
|
|
|
|
* Description: Set up touch screen muxing |
|
|
|
|
*******************************************/ |
|
|
|
|
* Description: Set up touch screen muxing |
|
|
|
|
*******************************************/ |
|
|
|
|
void muxSetupTouchScreen(void) |
|
|
|
|
{ |
|
|
|
|
volatile unsigned char *MuxConfigReg; |
|
|
|
|
|
|
|
|
|
/* SPI1_CLK pin configuration, PIN = U18 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SPI1_MOSI pin configuration, PIN = V20 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SPI1_MISO pin configuration, PIN = T18 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SPI1_nCS0 pin configuration, PIN = U19 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0; |
|
|
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */ |
|
|
|
|
|
|
|
|
|
/* SPI1_CLK pin configuration, PIN = U18, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_SPI1_CLK, 0); |
|
|
|
|
/* SPI1_MOSI pin configuration, PIN = V20, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_SPI1_SIMO, 0); |
|
|
|
|
/* SPI1_MISO pin configuration, PIN = T18, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_SPI1_SOMI, 0); |
|
|
|
|
/* SPI1_nCS0 pin configuration, PIN = U19, Mode = 0, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_SPI1_NCS0, 0); |
|
|
|
|
#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1 |
|
|
|
|
|
|
|
|
|
/* PEN_IRQ pin configuration, PIN = N15 */ |
|
|
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_GPIO85; |
|
|
|
|
*MuxConfigReg = 0x03; /* Mode = 3, PUPD=Disabled */ |
|
|
|
|
/* PEN_IRQ pin configuration, PIN = N15, Mode = 3, PUPD=Disabled */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_GPIO85, 3); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/***************************************************************
|
|
|
|
|
* Routine: muxSetupGPMC (ostboot) |
|
|
|
|
* Description: Configures balls which cam up in protected mode |
|
|
|
|
***************************************************************/ |
|
|
|
|
***************************************************************/ |
|
|
|
|
void muxSetupGPMC(void) |
|
|
|
|
{ |
|
|
|
|
volatile uint8 *MuxConfigReg; |
|
|
|
|
volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C; |
|
|
|
|
|
|
|
|
|
/* gpmc_io_dir */ |
|
|
|
|
*MCR = 0x19000000; |
|
|
|
|
/* gpmc_io_dir, MCR */ |
|
|
|
|
writel(0x4800008C, 0x19000000); |
|
|
|
|
|
|
|
|
|
/* NOR FLASH CS0 */ |
|
|
|
|
/* signal - Gpmc_clk;
|
|
|
|
|
pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */ |
|
|
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3; |
|
|
|
|
*MuxConfigReg = 0x00; |
|
|
|
|
|
|
|
|
|
/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */ |
|
|
|
|
write_config_reg(CONTROL_PADCONF_GPMC_D2_BYTE3, 0); |
|
|
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/* MPDB(Multi Port Debug Port) CS1 */ |
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/* signal - gpmc_ncs1;
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pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1; |
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*MuxConfigReg = 0x00; |
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/* signal - Gpmc_ncs2;
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pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2; |
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*MuxConfigReg = 0x00; |
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/* signal - Gpmc_ncs3;
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pin - N2; offset - 0x008C; mode - 0; Byte-3 Pull/up - N/A */ |
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3; |
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*MuxConfigReg = 0x00; |
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MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000090); |
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*MuxConfigReg = 0x00; |
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MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000091); |
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*MuxConfigReg = 0x00; |
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MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000092); |
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*MuxConfigReg = 0x00; |
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MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000093); |
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*MuxConfigReg = 0x00; |
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/* signal - gpmc_ncs1; pin - N8; offset - 0x008D; mode 0; Byte-1 */ |
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write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE1, 0); |
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/* signal - Gpmc_ncs2; pin - E2; offset - 0x008E; mode 0; Byte-2 */ |
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write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE2, 0); |
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/* signal - Gpmc_ncs3; pin - N2; offset - 0x008F; mode 0; Byte-3 */ |
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write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE3, 0); |
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/* signal - Gpmc_ncs4; pin - ??; offset - 0x0090; mode 0; Byte-4 */ |
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write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE4, 0); |
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/* signal - Gpmc_ncs5; pin - ??; offset - 0x0091; mode 0; Byte-5 */ |
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write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE5, 0); |
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/* signal - Gpmc_ncs6; pin - ??; offset - 0x0092; mode 0; Byte-6 */ |
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write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE6, 0); |
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/* signal - Gpmc_ncs7; pin - ??; offset - 0x0093; mode 0; Byte-7 */ |
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write_config_reg(CONTROL_PADCONF_GPMC_NCS0_BYTE7, 0); |
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} |
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/****************************************************************
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* Routine: muxSetupSDRC (ostboot) |
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* Routine: muxSetupSDRC (ostboot) |
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* Description: Configures balls which come up in protected mode |
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****************************************************************/ |
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****************************************************************/ |
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void muxSetupSDRC(void) |
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{ |
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/* It's set by IPL */ |
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