@ -25,6 +25,11 @@
# ifndef __CONFIG_H
# define __CONFIG_H
# ifdef CONFIG_MK_NAND
# define CONFIG_NAND_U_BOOT 1
# define CONFIG_RAMBOOT_TEXT_BASE 0x00100000
# endif
/*
* High Level Configuration Options
*/
@ -51,20 +56,29 @@
HRCWL_SVCOD_DIV_2 | \
HRCWL_CSB_TO_CLKIN_2X1 | \
HRCWL_CORE_TO_CSB_3X1 )
# define CONFIG_SYS_HRCW_HIGH (\
# define CONFIG_SYS_HRCW_HIGH_BASE (\
HRCWH_PCI_HOST | \
HRCWH_PCI1_ARBITER_ENABLE | \
HRCWH_CORE_ENABLE | \
HRCWH_FROM_0X00000100 | \
HRCWH_BOOTSEQ_DISABLE | \
HRCWH_SW_WATCHDOG_DISABLE | \
HRCWH_ROM_LOC_LOCAL_16BIT | \
HRCWH_RL_EXT_LEGACY | \
HRCWH_TSEC1M_IN_RGMII | \
HRCWH_TSEC2M_IN_RGMII | \
HRCWH_BIG_ENDIAN | \
HRCWH_LALE_NORMAL )
# ifdef CONFIG_NAND_SPL
# define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
HRCWH_FROM_0XFFF00100 | \
HRCWH_ROM_LOC_NAND_SP_8BIT | \
HRCWH_RL_EXT_NAND )
# else
# define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
HRCWH_FROM_0X00000100 | \
HRCWH_ROM_LOC_LOCAL_16BIT | \
HRCWH_RL_EXT_LEGACY )
# endif
/*
* System IO Config
*/
@ -79,6 +93,10 @@
*/
# define CONFIG_SYS_IMMR 0xE0000000
# if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
# define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
# endif
/*
* Arbiter Setup
*/
@ -161,12 +179,6 @@
*/
# define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
# if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT
# else
# undef CONFIG_SYS_RAMBOOT
# endif
# define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
# define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
@ -200,10 +212,10 @@
# define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
# define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
# define CONFIG_SYS_BR0 _PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
# define CONFIG_SYS_NOR_ BR_PRELIM (CONFIG_SYS_FLASH_BASE \
| ( 2 < < BR_PS_SHIFT ) /* 16 bit port size */ \
| BR_V ) /* valid */
# define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
# define CONFIG_SYS_NOR_OR_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
@ -223,18 +235,31 @@
/*
* NAND Flash on the Local Bus
*/
# define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
# ifdef CONFIG_NAND_SPL
# define CONFIG_SYS_NAND_BASE 0xFFF00000
# else
# define CONFIG_SYS_NAND_BASE 0xE0600000
# endif
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_MTD_NAND_VERIFY_WRITE 1
# define CONFIG_CMD_NAND 1
# define CONFIG_NAND_FSL_ELBC 1
# define CONFIG_SYS_NAND_BLOCK_SIZE 16384
# define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
# define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
# define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
# define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
# define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
# define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
# define CONFIG_SYS_NAND_ BR_PRELIM (CONFIG_SYS_NAND_BASE \
| ( 2 < < BR_DECC_SHIFT ) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */
# define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
# define CONFIG_SYS_NAND_ OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
@ -243,9 +268,31 @@
| OR_FCM_EHTR )
/* 0xFFFF8396 */
# ifdef CONFIG_NAND_U_BOOT
# define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
# define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
# define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
# define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
# else
# define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
# define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
# define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
# define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
# endif
# define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
# define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
# define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
# define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
# if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
! defined ( CONFIG_NAND_SPL )
# define CONFIG_SYS_RAMBOOT
# else
# undef CONFIG_SYS_RAMBOOT
# endif
/*
* Serial Port
*/
@ -254,7 +301,7 @@
# define CONFIG_SYS_NS16550
# define CONFIG_SYS_NS16550_SERIAL
# define CONFIG_SYS_NS16550_REG_SIZE 1
# define CONFIG_SYS_NS16550_CLK get_bus_freq(0 )
# define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2 )
# define CONFIG_SYS_BAUDRATE_TABLE \
{ 300 , 600 , 1200 , 2400 , 4800 , 9600 , 19200 , 38400 , 57600 , 115200 }
@ -408,7 +455,16 @@
/*
* Environment
*/
# ifndef CONFIG_SYS_RAMBOOT
# if defined(CONFIG_NAND_U_BOOT)
# define CONFIG_ENV_IS_IN_NAND 1
# define CONFIG_ENV_OFFSET (512 * 1024)
# define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
# define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
# define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
# define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_RANGE )
# elif !defined(CONFIG_SYS_RAMBOOT)
# define CONFIG_ENV_IS_IN_FLASH 1
# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
# define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
@ -442,7 +498,7 @@
# define CONFIG_CMD_DATE
# define CONFIG_CMD_PCI
# if defined(CONFIG_SYS_RAMBOOT)
# if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
# undef CONFIG_CMD_SAVEENV
# undef CONFIG_CMD_LOADS
# endif
@ -504,7 +560,8 @@
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
# define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
# define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
# define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \
BATU_VS | BATU_VP )
# define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE )
# define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U