Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>master
Tom Warren
12 years ago
committed by
Tom Warren
parent
d2f18f261b
commit
2fc65e2834
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/*
|
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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|
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/* Tegra114 clock PLL tables */ |
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#ifndef _TEGRA114_CLOCK_TABLES_H_ |
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#define _TEGRA114_CLOCK_TABLES_H_ |
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/* The PLLs supported by the hardware */ |
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enum clock_id { |
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CLOCK_ID_FIRST, |
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CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, |
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CLOCK_ID_MEMORY, |
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CLOCK_ID_PERIPH, |
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CLOCK_ID_AUDIO, |
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CLOCK_ID_USB, |
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CLOCK_ID_DISPLAY, |
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|
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/* now the simple ones */ |
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CLOCK_ID_FIRST_SIMPLE, |
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CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, |
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CLOCK_ID_EPCI, |
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CLOCK_ID_SFROM32KHZ, |
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|
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/* These are the base clocks (inputs to the Tegra SOC) */ |
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CLOCK_ID_32KHZ, |
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CLOCK_ID_OSC, |
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|
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CLOCK_ID_COUNT, /* number of PLLs */ |
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CLOCK_ID_DISPLAY2, /* placeholder */ |
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CLOCK_ID_NONE = -1, |
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}; |
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|
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/* The clocks supported by the hardware */ |
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enum periph_id { |
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PERIPH_ID_FIRST, |
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|
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/* Low word: 31:0 (DEVICES_L) */ |
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PERIPH_ID_CPU = PERIPH_ID_FIRST, |
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PERIPH_ID_COP, |
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PERIPH_ID_TRIGSYS, |
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PERIPH_ID_RESERVED3, |
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PERIPH_ID_RTC, |
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PERIPH_ID_TMR, |
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PERIPH_ID_UART1, |
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PERIPH_ID_UART2, |
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|
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/* 8 */ |
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PERIPH_ID_GPIO, |
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PERIPH_ID_SDMMC2, |
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PERIPH_ID_SPDIF, |
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PERIPH_ID_I2S1, |
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PERIPH_ID_I2C1, |
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PERIPH_ID_NDFLASH, |
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PERIPH_ID_SDMMC1, |
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PERIPH_ID_SDMMC4, |
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|
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/* 16 */ |
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PERIPH_ID_RESERVED16, |
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PERIPH_ID_PWM, |
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PERIPH_ID_I2S2, |
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PERIPH_ID_EPP, |
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PERIPH_ID_VI, |
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PERIPH_ID_2D, |
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PERIPH_ID_USBD, |
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PERIPH_ID_ISP, |
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|
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/* 24 */ |
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PERIPH_ID_3D, |
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PERIPH_ID_RESERVED24, |
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PERIPH_ID_DISP2, |
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PERIPH_ID_DISP1, |
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PERIPH_ID_HOST1X, |
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PERIPH_ID_VCP, |
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PERIPH_ID_I2S0, |
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PERIPH_ID_CACHE2, |
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|
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/* Middle word: 63:32 (DEVICES_H) */ |
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PERIPH_ID_MEM, |
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PERIPH_ID_AHBDMA, |
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PERIPH_ID_APBDMA, |
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PERIPH_ID_RESERVED35, |
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PERIPH_ID_KBC, |
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PERIPH_ID_STAT_MON, |
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PERIPH_ID_PMC, |
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PERIPH_ID_FUSE, |
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|
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/* 40 */ |
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PERIPH_ID_KFUSE, |
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PERIPH_ID_SBC1, |
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PERIPH_ID_SNOR, |
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PERIPH_ID_RESERVED43, |
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PERIPH_ID_SBC2, |
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PERIPH_ID_RESERVED45, |
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PERIPH_ID_SBC3, |
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PERIPH_ID_I2C5, |
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|
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/* 48 */ |
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PERIPH_ID_DSI, |
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PERIPH_ID_TVO, |
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PERIPH_ID_MIPI, |
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PERIPH_ID_HDMI, |
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PERIPH_ID_CSI, |
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PERIPH_ID_TVDAC, |
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PERIPH_ID_I2C2, |
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PERIPH_ID_UART3, |
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|
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/* 56 */ |
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PERIPH_ID_RESERVED56, |
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PERIPH_ID_EMC, |
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PERIPH_ID_USB2, |
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PERIPH_ID_USB3, |
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PERIPH_ID_MPE, |
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PERIPH_ID_VDE, |
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PERIPH_ID_BSEA, |
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PERIPH_ID_BSEV, |
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|
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/* Upper word 95:64 (DEVICES_U) */ |
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PERIPH_ID_SPEEDO, |
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PERIPH_ID_UART4, |
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PERIPH_ID_UART5, |
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PERIPH_ID_I2C3, |
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PERIPH_ID_SBC4, |
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PERIPH_ID_SDMMC3, |
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PERIPH_ID_PCIE, |
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PERIPH_ID_OWR, |
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|
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/* 72 */ |
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PERIPH_ID_AFI, |
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PERIPH_ID_CORESIGHT, |
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PERIPH_ID_PCIEXCLK, |
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PERIPH_ID_AVPUCQ, |
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PERIPH_ID_RESERVED76, |
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PERIPH_ID_RESERVED77, |
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PERIPH_ID_RESERVED78, |
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PERIPH_ID_DTV, |
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|
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/* 80 */ |
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PERIPH_ID_NANDSPEED, |
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PERIPH_ID_I2CSLOW, |
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PERIPH_ID_DSIB, |
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PERIPH_ID_RESERVED83, |
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PERIPH_ID_IRAMA, |
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PERIPH_ID_IRAMB, |
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PERIPH_ID_IRAMC, |
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PERIPH_ID_IRAMD, |
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|
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/* 88 */ |
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PERIPH_ID_CRAM2, |
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PERIPH_ID_RESERVED89, |
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PERIPH_ID_MDOUBLER, |
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PERIPH_ID_RESERVED91, |
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PERIPH_ID_SUSOUT, |
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PERIPH_ID_RESERVED93, |
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PERIPH_ID_RESERVED94, |
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PERIPH_ID_RESERVED95, |
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PERIPH_ID_VW_FIRST, |
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/* V word: 31:0 */ |
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PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST, |
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PERIPH_ID_CPULP, |
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PERIPH_ID_3D2, |
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PERIPH_ID_MSELECT, |
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PERIPH_ID_TSENSOR, |
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PERIPH_ID_I2S3, |
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PERIPH_ID_I2S4, |
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PERIPH_ID_I2C4, |
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|
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/* 104 */ |
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PERIPH_ID_SBC5, |
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PERIPH_ID_SBC6, |
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PERIPH_ID_AUDIO, |
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PERIPH_ID_APBIF, |
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PERIPH_ID_DAM0, |
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PERIPH_ID_DAM1, |
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PERIPH_ID_DAM2, |
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PERIPH_ID_HDA2CODEC2X, |
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|
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/* 112 */ |
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PERIPH_ID_ATOMICS, |
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PERIPH_ID_EX_RESERVED17, |
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PERIPH_ID_EX_RESERVED18, |
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PERIPH_ID_EX_RESERVED19, |
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PERIPH_ID_EX_RESERVED20, |
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PERIPH_ID_EX_RESERVED21, |
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PERIPH_ID_EX_RESERVED22, |
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PERIPH_ID_ACTMON, |
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/* 120 */ |
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PERIPH_ID_EX_RESERVED24, |
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PERIPH_ID_EX_RESERVED25, |
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PERIPH_ID_EX_RESERVED26, |
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PERIPH_ID_EX_RESERVED27, |
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PERIPH_ID_SATA, |
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PERIPH_ID_HDA, |
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PERIPH_ID_EX_RESERVED30, |
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PERIPH_ID_EX_RESERVED31, |
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|
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/* W word: 31:0 */ |
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PERIPH_ID_HDA2HDMICODEC, |
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PERIPH_ID_RESERVED1_SATACOLD, |
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PERIPH_ID_RESERVED2_PCIERX0, |
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PERIPH_ID_RESERVED3_PCIERX1, |
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PERIPH_ID_RESERVED4_PCIERX2, |
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PERIPH_ID_RESERVED5_PCIERX3, |
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PERIPH_ID_RESERVED6_PCIERX4, |
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PERIPH_ID_RESERVED7_PCIERX5, |
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|
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/* 136 */ |
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PERIPH_ID_CEC, |
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PERIPH_ID_PCIE2_IOBIST, |
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PERIPH_ID_EMC_IOBIST, |
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PERIPH_ID_HDMI_IOBIST, |
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PERIPH_ID_SATA_IOBIST, |
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PERIPH_ID_MIPI_IOBIST, |
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PERIPH_ID_EMC1_IOBIST, |
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PERIPH_ID_XUSB, |
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/* 144 */ |
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PERIPH_ID_CILAB, |
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PERIPH_ID_CILCD, |
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PERIPH_ID_CILE, |
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PERIPH_ID_DSIA_LP, |
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PERIPH_ID_DSIB_LP, |
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PERIPH_ID_RESERVED21_ENTROPY, |
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PERIPH_ID_RESERVED22_W, |
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PERIPH_ID_RESERVED23_W, |
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|
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/* 152 */ |
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PERIPH_ID_RESERVED24_W, |
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PERIPH_ID_AMX0, |
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PERIPH_ID_ADX0, |
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PERIPH_ID_DVFS, |
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PERIPH_ID_XUSB_SS, |
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PERIPH_ID_EMC_DLL, |
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PERIPH_ID_MC1, |
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PERIPH_ID_EMC1, |
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PERIPH_ID_COUNT, |
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PERIPH_ID_NONE = -1, |
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}; |
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enum pll_out_id { |
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PLL_OUT1, |
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PLL_OUT2, |
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PLL_OUT3, |
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PLL_OUT4 |
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}; |
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|
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/*
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* Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want |
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* callers to use the PERIPH_ID for all access to peripheral clocks to avoid |
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* confusion bewteen PERIPH_ID_... and PERIPHC_... |
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* |
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* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be |
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* confusing. |
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*/ |
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enum periphc_internal_id { |
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/* 0x00 */ |
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PERIPHC_I2S1, |
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PERIPHC_I2S2, |
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PERIPHC_SPDIF_OUT, |
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PERIPHC_SPDIF_IN, |
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PERIPHC_PWM, |
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PERIPHC_05h, |
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PERIPHC_SBC2, |
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PERIPHC_SBC3, |
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|
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/* 0x08 */ |
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PERIPHC_08h, |
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PERIPHC_I2C1, |
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PERIPHC_I2C5, |
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PERIPHC_0bh, |
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PERIPHC_0ch, |
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PERIPHC_SBC1, |
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PERIPHC_DISP1, |
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PERIPHC_DISP2, |
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|
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/* 0x10 */ |
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PERIPHC_CVE, |
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PERIPHC_11h, |
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PERIPHC_VI, |
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PERIPHC_13h, |
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PERIPHC_SDMMC1, |
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PERIPHC_SDMMC2, |
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PERIPHC_G3D, |
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PERIPHC_G2D, |
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|
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/* 0x18 */ |
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PERIPHC_NDFLASH, |
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PERIPHC_SDMMC4, |
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PERIPHC_VFIR, |
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PERIPHC_EPP, |
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PERIPHC_MPE, |
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PERIPHC_MIPI, |
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PERIPHC_UART1, |
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PERIPHC_UART2, |
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|
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/* 0x20 */ |
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PERIPHC_HOST1X, |
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PERIPHC_21h, |
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PERIPHC_TVO, |
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PERIPHC_HDMI, |
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PERIPHC_24h, |
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PERIPHC_TVDAC, |
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PERIPHC_I2C2, |
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PERIPHC_EMC, |
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|
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/* 0x28 */ |
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PERIPHC_UART3, |
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PERIPHC_29h, |
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PERIPHC_VI_SENSOR, |
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PERIPHC_2bh, |
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PERIPHC_2ch, |
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PERIPHC_SBC4, |
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PERIPHC_I2C3, |
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PERIPHC_SDMMC3, |
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|
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/* 0x30 */ |
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PERIPHC_UART4, |
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PERIPHC_UART5, |
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PERIPHC_VDE, |
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PERIPHC_OWR, |
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PERIPHC_NOR, |
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PERIPHC_CSITE, |
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PERIPHC_I2S0, |
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PERIPHC_37h, |
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PERIPHC_VW_FIRST, |
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/* 0x38 */ |
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PERIPHC_G3D2 = PERIPHC_VW_FIRST, |
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PERIPHC_MSELECT, |
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PERIPHC_TSENSOR, |
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PERIPHC_I2S3, |
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PERIPHC_I2S4, |
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PERIPHC_I2C4, |
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PERIPHC_SBC5, |
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PERIPHC_SBC6, |
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|
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/* 0x40 */ |
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PERIPHC_AUDIO, |
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PERIPHC_41h, |
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PERIPHC_DAM0, |
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PERIPHC_DAM1, |
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PERIPHC_DAM2, |
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PERIPHC_HDA2CODEC2X, |
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PERIPHC_ACTMON, |
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PERIPHC_EXTPERIPH1, |
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/* 0x48 */ |
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PERIPHC_EXTPERIPH2, |
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PERIPHC_EXTPERIPH3, |
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PERIPHC_NANDSPEED, |
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PERIPHC_I2CSLOW, |
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PERIPHC_SYS, |
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PERIPHC_SPEEDO, |
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PERIPHC_4eh, |
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PERIPHC_4fh, |
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/* 0x50 */ |
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PERIPHC_50h, |
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PERIPHC_51h, |
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PERIPHC_52h, |
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PERIPHC_53h, |
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PERIPHC_SATAOOB, |
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PERIPHC_SATA, |
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PERIPHC_HDA, |
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PERIPHC_COUNT, |
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PERIPHC_NONE = -1, |
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}; |
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/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */ |
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#define PERIPH_REG(id) \ |
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(id < PERIPH_ID_VW_FIRST) ? \
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((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5) |
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/* Mask value for a clock (within PERIPH_REG(id)) */ |
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#define PERIPH_MASK(id) (1 << ((id) & 0x1f)) |
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/* return 1 if a PLL ID is in range */ |
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#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) |
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/* return 1 if a peripheral ID is in range */ |
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#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ |
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(id) < PERIPH_ID_COUNT) |
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#endif /* _TEGRA114_CLOCK_TABLES_H_ */ |
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@ -0,0 +1,28 @@ |
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/ |
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|
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/* Tegra114 clock control functions */ |
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#ifndef _TEGRA114_CLOCK_H_ |
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#define _TEGRA114_CLOCK_H_ |
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#include <asm/arch-tegra/clock.h> |
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/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ |
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#define OSC_FREQ_SHIFT 28 |
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#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) |
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#endif /* _TEGRA114_CLOCK_H_ */ |
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@ -0,0 +1,35 @@ |
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/ |
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#ifndef _TEGRA114_FLOW_H_ |
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#define _TEGRA114_FLOW_H_ |
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struct flow_ctlr { |
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u32 halt_cpu_events; |
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u32 halt_cop_events; |
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u32 cpu_csr; |
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u32 cop_csr; |
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u32 xrq_events; |
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u32 halt_cpu1_events; |
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u32 cpu1_csr; |
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u32 halt_cpu2_events; |
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u32 cpu2_csr; |
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u32 halt_cpu3_events; |
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u32 cpu3_csr; |
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u32 cluster_control; |
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}; |
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#endif /* _TEGRA114_FLOW_H_ */ |
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@ -0,0 +1,31 @@ |
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/*
|
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/ |
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|
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/* Tegra114 high-level function multiplexing */ |
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|
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#ifndef _TEGRA114_FUNCMUX_H_ |
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#define _TEGRA114_FUNCMUX_H_ |
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#include <asm/arch-tegra/funcmux.h> |
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|
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/* Configs supported by the func mux */ |
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enum { |
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FUNCMUX_DEFAULT = 0, /* default config */ |
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|
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/* UART configs */ |
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FUNCMUX_UART4_GMI = 0, |
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}; |
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#endif /* _TEGRA114_FUNCMUX_H_ */ |
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@ -0,0 +1,59 @@ |
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/*
|
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/ |
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|
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#ifndef _TEGRA114_GP_PADCTRL_H_ |
||||
#define _TEGRA114_GP_PADCTRL_H_ |
||||
|
||||
#include <asm/arch-tegra/gp_padctrl.h> |
||||
|
||||
/* APB_MISC_GP and padctrl registers */ |
||||
struct apb_misc_gp_ctlr { |
||||
u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ |
||||
u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ |
||||
u32 reserved0[22]; /* 0x08 - 0x5C: */ |
||||
u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ |
||||
u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ |
||||
u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ |
||||
u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ |
||||
u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ |
||||
u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ |
||||
u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ |
||||
u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ |
||||
u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ |
||||
u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ |
||||
u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ |
||||
u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */ |
||||
u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ |
||||
u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ |
||||
u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ |
||||
u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ |
||||
u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ |
||||
u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */ |
||||
u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */ |
||||
u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */ |
||||
u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ |
||||
u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ |
||||
u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ |
||||
u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ |
||||
u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ |
||||
u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ |
||||
u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */ |
||||
u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */ |
||||
u32 reserved1[7]; /* 0xD0-0xE8: */ |
||||
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ |
||||
}; |
||||
|
||||
#endif /* _TEGRA114_GP_PADCTRL_H_ */ |
||||
@ -0,0 +1,30 @@ |
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef _TEGRA114_GPIO_H_ |
||||
#define _TEGRA114_GPIO_H_ |
||||
|
||||
/*
|
||||
* The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports, |
||||
* each with 8 GPIOs. |
||||
*/ |
||||
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */ |
||||
#define TEGRA_GPIO_BANKS 8 /* number of banks */ |
||||
|
||||
#include <asm/arch-tegra/gpio.h> |
||||
#include <asm/arch-tegra30/gpio.h> |
||||
|
||||
#endif /* _TEGRA114_GPIO_H_ */ |
||||
@ -0,0 +1,22 @@ |
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef _TEGRA114_HARDWARE_H_ |
||||
#define _TEGRA114_HARDWARE_H_ |
||||
|
||||
/* include tegra specific hardware definitions */ |
||||
|
||||
#endif /* _TEGRA114_HARDWARE_H_ */ |
||||
@ -0,0 +1,618 @@ |
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef _TEGRA114_PINMUX_H_ |
||||
#define _TEGRA114_PINMUX_H_ |
||||
|
||||
/*
|
||||
* Pin groups which we adjust. There are three basic attributes of each pin |
||||
* group which use this enum: |
||||
* |
||||
* - function |
||||
* - pullup / pulldown |
||||
* - tristate or normal |
||||
*/ |
||||
enum pmux_pingrp { |
||||
PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */ |
||||
PINGRP_ULPI_DATA1, |
||||
PINGRP_ULPI_DATA2, |
||||
PINGRP_ULPI_DATA3, |
||||
PINGRP_ULPI_DATA4, |
||||
PINGRP_ULPI_DATA5, |
||||
PINGRP_ULPI_DATA6, |
||||
PINGRP_ULPI_DATA7, |
||||
PINGRP_ULPI_CLK, |
||||
PINGRP_ULPI_DIR, |
||||
PINGRP_ULPI_NXT, |
||||
PINGRP_ULPI_STP, |
||||
PINGRP_DAP3_FS, |
||||
PINGRP_DAP3_DIN, |
||||
PINGRP_DAP3_DOUT, |
||||
PINGRP_DAP3_SCLK, |
||||
PINGRP_GPIO_PV0, |
||||
PINGRP_GPIO_PV1, |
||||
PINGRP_SDMMC1_CLK, |
||||
PINGRP_SDMMC1_CMD, |
||||
PINGRP_SDMMC1_DAT3, |
||||
PINGRP_SDMMC1_DAT2, |
||||
PINGRP_SDMMC1_DAT1, |
||||
PINGRP_SDMMC1_DAT0, |
||||
PINGRP_GPIO_PV2, |
||||
PINGRP_GPIO_PV3, |
||||
PINGRP_CLK2_OUT, |
||||
PINGRP_CLK2_REQ, |
||||
PINGRP_LCD_PWR1, |
||||
PINGRP_LCD_PWR2, |
||||
PINGRP_LCD_SDIN, |
||||
PINGRP_LCD_SDOUT, |
||||
PINGRP_LCD_WR_N, |
||||
PINGRP_LCD_CS0_N, |
||||
PINGRP_LCD_DC0, |
||||
PINGRP_LCD_SCK, |
||||
PINGRP_LCD_PWR0, |
||||
PINGRP_LCD_PCLK, |
||||
PINGRP_LCD_DE, |
||||
PINGRP_LCD_HSYNC, |
||||
PINGRP_LCD_VSYNC, |
||||
PINGRP_LCD_D0, |
||||
PINGRP_LCD_D1, |
||||
PINGRP_LCD_D2, |
||||
PINGRP_LCD_D3, |
||||
PINGRP_LCD_D4, |
||||
PINGRP_LCD_D5, |
||||
PINGRP_LCD_D6, |
||||
PINGRP_LCD_D7, |
||||
PINGRP_LCD_D8, |
||||
PINGRP_LCD_D9, |
||||
PINGRP_LCD_D10, |
||||
PINGRP_LCD_D11, |
||||
PINGRP_LCD_D12, |
||||
PINGRP_LCD_D13, |
||||
PINGRP_LCD_D14, |
||||
PINGRP_LCD_D15, |
||||
PINGRP_LCD_D16, |
||||
PINGRP_LCD_D17, |
||||
PINGRP_LCD_D18, |
||||
PINGRP_LCD_D19, |
||||
PINGRP_LCD_D20, |
||||
PINGRP_LCD_D21, |
||||
PINGRP_LCD_D22, |
||||
PINGRP_LCD_D23, |
||||
PINGRP_LCD_CS1_N, |
||||
PINGRP_LCD_M1, |
||||
PINGRP_LCD_DC1, |
||||
PINGRP_HDMI_INT, |
||||
PINGRP_DDC_SCL, |
||||
PINGRP_DDC_SDA, |
||||
PINGRP_CRT_HSYNC, |
||||
PINGRP_CRT_VSYNC, |
||||
PINGRP_VI_D0, |
||||
PINGRP_VI_D1, |
||||
PINGRP_VI_D2, |
||||
PINGRP_VI_D3, |
||||
PINGRP_VI_D4, |
||||
PINGRP_VI_D5, |
||||
PINGRP_VI_D6, |
||||
PINGRP_VI_D7, |
||||
PINGRP_VI_D8, |
||||
PINGRP_VI_D9, |
||||
PINGRP_VI_D10, |
||||
PINGRP_VI_D11, |
||||
PINGRP_VI_PCLK, |
||||
PINGRP_VI_MCLK, |
||||
PINGRP_VI_VSYNC, |
||||
PINGRP_VI_HSYNC, |
||||
PINGRP_UART2_RXD, |
||||
PINGRP_UART2_TXD, |
||||
PINGRP_UART2_RTS_N, |
||||
PINGRP_UART2_CTS_N, |
||||
PINGRP_UART3_TXD, |
||||
PINGRP_UART3_RXD, |
||||
PINGRP_UART3_CTS_N, |
||||
PINGRP_UART3_RTS_N, |
||||
PINGRP_GPIO_PU0, |
||||
PINGRP_GPIO_PU1, |
||||
PINGRP_GPIO_PU2, |
||||
PINGRP_GPIO_PU3, |
||||
PINGRP_GPIO_PU4, |
||||
PINGRP_GPIO_PU5, |
||||
PINGRP_GPIO_PU6, |
||||
PINGRP_GEN1_I2C_SDA, |
||||
PINGRP_GEN1_I2C_SCL, |
||||
PINGRP_DAP4_FS, |
||||
PINGRP_DAP4_DIN, |
||||
PINGRP_DAP4_DOUT, |
||||
PINGRP_DAP4_SCLK, |
||||
PINGRP_CLK3_OUT, |
||||
PINGRP_CLK3_REQ, |
||||
PINGRP_GMI_WP_N, |
||||
PINGRP_GMI_IORDY, |
||||
PINGRP_GMI_WAIT, |
||||
PINGRP_GMI_ADV_N, |
||||
PINGRP_GMI_CLK, |
||||
PINGRP_GMI_CS0_N, |
||||
PINGRP_GMI_CS1_N, |
||||
PINGRP_GMI_CS2_N, |
||||
PINGRP_GMI_CS3_N, |
||||
PINGRP_GMI_CS4_N, |
||||
PINGRP_GMI_CS6_N, |
||||
PINGRP_GMI_CS7_N, |
||||
PINGRP_GMI_AD0, |
||||
PINGRP_GMI_AD1, |
||||
PINGRP_GMI_AD2, |
||||
PINGRP_GMI_AD3, |
||||
PINGRP_GMI_AD4, |
||||
PINGRP_GMI_AD5, |
||||
PINGRP_GMI_AD6, |
||||
PINGRP_GMI_AD7, |
||||
PINGRP_GMI_AD8, |
||||
PINGRP_GMI_AD9, |
||||
PINGRP_GMI_AD10, |
||||
PINGRP_GMI_AD11, |
||||
PINGRP_GMI_AD12, |
||||
PINGRP_GMI_AD13, |
||||
PINGRP_GMI_AD14, |
||||
PINGRP_GMI_AD15, |
||||
PINGRP_GMI_A16, |
||||
PINGRP_GMI_A17, |
||||
PINGRP_GMI_A18, |
||||
PINGRP_GMI_A19, |
||||
PINGRP_GMI_WR_N, |
||||
PINGRP_GMI_OE_N, |
||||
PINGRP_GMI_DQS, |
||||
PINGRP_GMI_RST_N, |
||||
PINGRP_GEN2_I2C_SCL, |
||||
PINGRP_GEN2_I2C_SDA, |
||||
PINGRP_SDMMC4_CLK, |
||||
PINGRP_SDMMC4_CMD, |
||||
PINGRP_SDMMC4_DAT0, |
||||
PINGRP_SDMMC4_DAT1, |
||||
PINGRP_SDMMC4_DAT2, |
||||
PINGRP_SDMMC4_DAT3, |
||||
PINGRP_SDMMC4_DAT4, |
||||
PINGRP_SDMMC4_DAT5, |
||||
PINGRP_SDMMC4_DAT6, |
||||
PINGRP_SDMMC4_DAT7, |
||||
PINGRP_SDMMC4_RST_N, |
||||
PINGRP_CAM_MCLK, |
||||
PINGRP_GPIO_PCC1, |
||||
PINGRP_GPIO_PBB0, |
||||
PINGRP_CAM_I2C_SCL, |
||||
PINGRP_CAM_I2C_SDA, |
||||
PINGRP_GPIO_PBB3, |
||||
PINGRP_GPIO_PBB4, |
||||
PINGRP_GPIO_PBB5, |
||||
PINGRP_GPIO_PBB6, |
||||
PINGRP_GPIO_PBB7, |
||||
PINGRP_GPIO_PCC2, |
||||
PINGRP_JTAG_RTCK, |
||||
PINGRP_PWR_I2C_SCL, |
||||
PINGRP_PWR_I2C_SDA, |
||||
PINGRP_KB_ROW0, |
||||
PINGRP_KB_ROW1, |
||||
PINGRP_KB_ROW2, |
||||
PINGRP_KB_ROW3, |
||||
PINGRP_KB_ROW4, |
||||
PINGRP_KB_ROW5, |
||||
PINGRP_KB_ROW6, |
||||
PINGRP_KB_ROW7, |
||||
PINGRP_KB_ROW8, |
||||
PINGRP_KB_ROW9, |
||||
PINGRP_KB_ROW10, |
||||
PINGRP_KB_ROW11, |
||||
PINGRP_KB_ROW12, |
||||
PINGRP_KB_ROW13, |
||||
PINGRP_KB_ROW14, |
||||
PINGRP_KB_ROW15, |
||||
PINGRP_KB_COL0, |
||||
PINGRP_KB_COL1, |
||||
PINGRP_KB_COL2, |
||||
PINGRP_KB_COL3, |
||||
PINGRP_KB_COL4, |
||||
PINGRP_KB_COL5, |
||||
PINGRP_KB_COL6, |
||||
PINGRP_KB_COL7, |
||||
PINGRP_CLK_32K_OUT, |
||||
PINGRP_SYS_CLK_REQ, |
||||
PINGRP_CORE_PWR_REQ, |
||||
PINGRP_CPU_PWR_REQ, |
||||
PINGRP_PWR_INT_N, |
||||
PINGRP_CLK_32K_IN, |
||||
PINGRP_OWR, |
||||
PINGRP_DAP1_FS, |
||||
PINGRP_DAP1_DIN, |
||||
PINGRP_DAP1_DOUT, |
||||
PINGRP_DAP1_SCLK, |
||||
PINGRP_CLK1_REQ, |
||||
PINGRP_CLK1_OUT, |
||||
PINGRP_SPDIF_IN, |
||||
PINGRP_SPDIF_OUT, |
||||
PINGRP_DAP2_FS, |
||||
PINGRP_DAP2_DIN, |
||||
PINGRP_DAP2_DOUT, |
||||
PINGRP_DAP2_SCLK, |
||||
PINGRP_SPI2_MOSI, |
||||
PINGRP_SPI2_MISO, |
||||
PINGRP_SPI2_CS0_N, |
||||
PINGRP_SPI2_SCK, |
||||
PINGRP_SPI1_MOSI, |
||||
PINGRP_SPI1_SCK, |
||||
PINGRP_SPI1_CS0_N, |
||||
PINGRP_SPI1_MISO, |
||||
PINGRP_SPI2_CS1_N, |
||||
PINGRP_SPI2_CS2_N, |
||||
PINGRP_SDMMC3_CLK, |
||||
PINGRP_SDMMC3_CMD, |
||||
PINGRP_SDMMC3_DAT0, |
||||
PINGRP_SDMMC3_DAT1, |
||||
PINGRP_SDMMC3_DAT2, |
||||
PINGRP_SDMMC3_DAT3, |
||||
PINGRP_SDMMC3_DAT4, |
||||
PINGRP_SDMMC3_DAT5, |
||||
PINGRP_SDMMC3_DAT6, |
||||
PINGRP_SDMMC3_DAT7, |
||||
PINGRP_PEX_L0_PRSNT_N, |
||||
PINGRP_PEX_L0_RST_N, |
||||
PINGRP_PEX_L0_CLKREQ_N, |
||||
PINGRP_PEX_WAKE_N, |
||||
PINGRP_PEX_L1_PRSNT_N, |
||||
PINGRP_PEX_L1_RST_N, |
||||
PINGRP_PEX_L1_CLKREQ_N, |
||||
PINGRP_PEX_L2_PRSNT_N, |
||||
PINGRP_PEX_L2_RST_N, |
||||
PINGRP_PEX_L2_CLKREQ_N, |
||||
PINGRP_HDMI_CEC, /* offset 0x33e0 */ |
||||
PINGRP_SDMMC1_WP_N, |
||||
PINGRP_SDMMC3_CD_N, |
||||
PINGRP_SPI1_CS1_N, |
||||
PINGRP_SPI1_CS2_N, |
||||
PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */ |
||||
PINGRP_USB_VBUS_EN1, |
||||
PINGRP_SDMMC3_CLK_LB_IN, |
||||
PINGRP_SDMMC3_CLK_LB_OUT, |
||||
PINGRP_NAND_GMI_CLK_LB, |
||||
PINGRP_RESET_OUT_N, |
||||
PINGRP_COUNT, |
||||
}; |
||||
|
||||
enum pdrive_pingrp { |
||||
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */ |
||||
PDRIVE_PINGROUP_AO2, |
||||
PDRIVE_PINGROUP_AT1, |
||||
PDRIVE_PINGROUP_AT2, |
||||
PDRIVE_PINGROUP_AT3, |
||||
PDRIVE_PINGROUP_AT4, |
||||
PDRIVE_PINGROUP_AT5, |
||||
PDRIVE_PINGROUP_CDEV1, |
||||
PDRIVE_PINGROUP_CDEV2, |
||||
PDRIVE_PINGROUP_CSUS, |
||||
PDRIVE_PINGROUP_DAP1, |
||||
PDRIVE_PINGROUP_DAP2, |
||||
PDRIVE_PINGROUP_DAP3, |
||||
PDRIVE_PINGROUP_DAP4, |
||||
PDRIVE_PINGROUP_DBG, |
||||
PDRIVE_PINGROUP_LCD1, |
||||
PDRIVE_PINGROUP_LCD2, |
||||
PDRIVE_PINGROUP_SDIO2, |
||||
PDRIVE_PINGROUP_SDIO3, |
||||
PDRIVE_PINGROUP_SPI, |
||||
PDRIVE_PINGROUP_UAA, |
||||
PDRIVE_PINGROUP_UAB, |
||||
PDRIVE_PINGROUP_UART2, |
||||
PDRIVE_PINGROUP_UART3, |
||||
PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */ |
||||
PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */ |
||||
PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */ |
||||
PDRIVE_PINGROUP_DDC, |
||||
PDRIVE_PINGROUP_GMA, |
||||
PDRIVE_PINGROUP_GMB, |
||||
PDRIVE_PINGROUP_GMC, |
||||
PDRIVE_PINGROUP_GMD, |
||||
PDRIVE_PINGROUP_GME, |
||||
PDRIVE_PINGROUP_GMF, |
||||
PDRIVE_PINGROUP_GMG, |
||||
PDRIVE_PINGROUP_GMH, |
||||
PDRIVE_PINGROUP_OWR, |
||||
PDRIVE_PINGROUP_UAD, |
||||
PDRIVE_PINGROUP_GPV, |
||||
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */ |
||||
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */ |
||||
PDRIVE_PINGROUP_AT6, |
||||
PDRIVE_PINGROUP_DAP5, |
||||
PDRIVE_PINGROUP_VBUS, |
||||
PDRIVE_PINGROUP_COUNT, |
||||
}; |
||||
|
||||
/*
|
||||
* Functions which can be assigned to each of the pin groups. The values here |
||||
* bear no relation to the values programmed into pinmux registers and are |
||||
* purely a convenience. The translation is done through a table search. |
||||
*/ |
||||
enum pmux_func { |
||||
PMUX_FUNC_AHB_CLK, |
||||
PMUX_FUNC_APB_CLK, |
||||
PMUX_FUNC_AUDIO_SYNC, |
||||
PMUX_FUNC_CRT, |
||||
PMUX_FUNC_DAP1, |
||||
PMUX_FUNC_DAP2, |
||||
PMUX_FUNC_DAP3, |
||||
PMUX_FUNC_DAP4, |
||||
PMUX_FUNC_DAP5, |
||||
PMUX_FUNC_DISPA, |
||||
PMUX_FUNC_DISPB, |
||||
PMUX_FUNC_EMC_TEST0_DLL, |
||||
PMUX_FUNC_EMC_TEST1_DLL, |
||||
PMUX_FUNC_GMI, |
||||
PMUX_FUNC_GMI_INT, |
||||
PMUX_FUNC_HDMI, |
||||
PMUX_FUNC_I2C1, |
||||
PMUX_FUNC_I2C2, |
||||
PMUX_FUNC_I2C3, |
||||
PMUX_FUNC_IDE, |
||||
PMUX_FUNC_KBC, |
||||
PMUX_FUNC_MIO, |
||||
PMUX_FUNC_MIPI_HS, |
||||
PMUX_FUNC_NAND, |
||||
PMUX_FUNC_OSC, |
||||
PMUX_FUNC_OWR, |
||||
PMUX_FUNC_PCIE, |
||||
PMUX_FUNC_PLLA_OUT, |
||||
PMUX_FUNC_PLLC_OUT1, |
||||
PMUX_FUNC_PLLM_OUT1, |
||||
PMUX_FUNC_PLLP_OUT2, |
||||
PMUX_FUNC_PLLP_OUT3, |
||||
PMUX_FUNC_PLLP_OUT4, |
||||
PMUX_FUNC_PWM, |
||||
PMUX_FUNC_PWR_INTR, |
||||
PMUX_FUNC_PWR_ON, |
||||
PMUX_FUNC_RTCK, |
||||
PMUX_FUNC_SDMMC1, |
||||
PMUX_FUNC_SDMMC2, |
||||
PMUX_FUNC_SDMMC3, |
||||
PMUX_FUNC_SDMMC4, |
||||
PMUX_FUNC_SFLASH, |
||||
PMUX_FUNC_SPDIF, |
||||
PMUX_FUNC_SPI1, |
||||
PMUX_FUNC_SPI2, |
||||
PMUX_FUNC_SPI2_ALT, |
||||
PMUX_FUNC_SPI3, |
||||
PMUX_FUNC_SPI4, |
||||
PMUX_FUNC_TRACE, |
||||
PMUX_FUNC_TWC, |
||||
PMUX_FUNC_UARTA, |
||||
PMUX_FUNC_UARTB, |
||||
PMUX_FUNC_UARTC, |
||||
PMUX_FUNC_UARTD, |
||||
PMUX_FUNC_UARTE, |
||||
PMUX_FUNC_ULPI, |
||||
PMUX_FUNC_VI, |
||||
PMUX_FUNC_VI_SENSOR_CLK, |
||||
PMUX_FUNC_XIO, |
||||
PMUX_FUNC_BLINK, |
||||
PMUX_FUNC_CEC, |
||||
PMUX_FUNC_CLK12, |
||||
PMUX_FUNC_DAP, |
||||
PMUX_FUNC_DAPSDMMC2, |
||||
PMUX_FUNC_DDR, |
||||
PMUX_FUNC_DEV3, |
||||
PMUX_FUNC_DTV, |
||||
PMUX_FUNC_VI_ALT1, |
||||
PMUX_FUNC_VI_ALT2, |
||||
PMUX_FUNC_VI_ALT3, |
||||
PMUX_FUNC_EMC_DLL, |
||||
PMUX_FUNC_EXTPERIPH1, |
||||
PMUX_FUNC_EXTPERIPH2, |
||||
PMUX_FUNC_EXTPERIPH3, |
||||
PMUX_FUNC_GMI_ALT, |
||||
PMUX_FUNC_HDA, |
||||
PMUX_FUNC_HSI, |
||||
PMUX_FUNC_I2C4, |
||||
PMUX_FUNC_I2C5, |
||||
PMUX_FUNC_I2CPWR, |
||||
PMUX_FUNC_I2S0, |
||||
PMUX_FUNC_I2S1, |
||||
PMUX_FUNC_I2S2, |
||||
PMUX_FUNC_I2S3, |
||||
PMUX_FUNC_I2S4, |
||||
PMUX_FUNC_NAND_ALT, |
||||
PMUX_FUNC_POPSDIO4, |
||||
PMUX_FUNC_POPSDMMC4, |
||||
PMUX_FUNC_PWM0, |
||||
PMUX_FUNC_PWM1, |
||||
PMUX_FUNC_PWM2, |
||||
PMUX_FUNC_PWM3, |
||||
PMUX_FUNC_SATA, |
||||
PMUX_FUNC_SPI5, |
||||
PMUX_FUNC_SPI6, |
||||
PMUX_FUNC_SYSCLK, |
||||
PMUX_FUNC_VGP1, |
||||
PMUX_FUNC_VGP2, |
||||
PMUX_FUNC_VGP3, |
||||
PMUX_FUNC_VGP4, |
||||
PMUX_FUNC_VGP5, |
||||
PMUX_FUNC_VGP6, |
||||
|
||||
PMUX_FUNC_USB, |
||||
PMUX_FUNC_SOC, |
||||
PMUX_FUNC_CPU, |
||||
PMUX_FUNC_CLK, |
||||
PMUX_FUNC_PWRON, |
||||
PMUX_FUNC_PMI, |
||||
PMUX_FUNC_CLDVFS, |
||||
PMUX_FUNC_RESET_OUT_N, |
||||
|
||||
PMUX_FUNC_SAFE, |
||||
PMUX_FUNC_MAX, |
||||
|
||||
PMUX_FUNC_RSVD1 = 0x8000, |
||||
PMUX_FUNC_RSVD2 = 0x8001, |
||||
PMUX_FUNC_RSVD3 = 0x8002, |
||||
PMUX_FUNC_RSVD4 = 0x8003, |
||||
}; |
||||
|
||||
/* return 1 if a pmux_func is in range */ |
||||
#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \ |
||||
|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) |
||||
|
||||
/* return 1 if a pingrp is in range */ |
||||
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT)) |
||||
|
||||
/* The pullup/pulldown state of a pin group */ |
||||
enum pmux_pull { |
||||
PMUX_PULL_NORMAL = 0, |
||||
PMUX_PULL_DOWN, |
||||
PMUX_PULL_UP, |
||||
}; |
||||
/* return 1 if a pin_pupd_is in range */ |
||||
#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \ |
||||
((pupd) <= PMUX_PULL_UP)) |
||||
|
||||
/* Defines whether a pin group is tristated or in normal operation */ |
||||
enum pmux_tristate { |
||||
PMUX_TRI_NORMAL = 0, |
||||
PMUX_TRI_TRISTATE = 1, |
||||
}; |
||||
/* return 1 if a pin_tristate_is in range */ |
||||
#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \ |
||||
&& ((tristate) <= PMUX_TRI_TRISTATE)) |
||||
|
||||
enum pmux_pin_io { |
||||
PMUX_PIN_OUTPUT = 0, |
||||
PMUX_PIN_INPUT = 1, |
||||
}; |
||||
/* return 1 if a pin_io_is in range */ |
||||
#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \ |
||||
((io) <= PMUX_PIN_INPUT)) |
||||
|
||||
enum pmux_pin_lock { |
||||
PMUX_PIN_LOCK_DEFAULT = 0, |
||||
PMUX_PIN_LOCK_DISABLE, |
||||
PMUX_PIN_LOCK_ENABLE, |
||||
}; |
||||
/* return 1 if a pin_lock is in range */ |
||||
#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \ |
||||
((lock) <= PMUX_PIN_LOCK_ENABLE)) |
||||
|
||||
enum pmux_pin_od { |
||||
PMUX_PIN_OD_DEFAULT = 0, |
||||
PMUX_PIN_OD_DISABLE, |
||||
PMUX_PIN_OD_ENABLE, |
||||
}; |
||||
/* return 1 if a pin_od is in range */ |
||||
#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \ |
||||
((od) <= PMUX_PIN_OD_ENABLE)) |
||||
|
||||
enum pmux_pin_ioreset { |
||||
PMUX_PIN_IO_RESET_DEFAULT = 0, |
||||
PMUX_PIN_IO_RESET_DISABLE, |
||||
PMUX_PIN_IO_RESET_ENABLE, |
||||
}; |
||||
/* return 1 if a pin_ioreset_is in range */ |
||||
#define pmux_pin_ioreset_isvalid(ioreset) \ |
||||
(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
|
||||
((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) |
||||
|
||||
/* Available power domains used by pin groups */ |
||||
enum pmux_vddio { |
||||
PMUX_VDDIO_BB = 0, |
||||
PMUX_VDDIO_LCD, |
||||
PMUX_VDDIO_VI, |
||||
PMUX_VDDIO_UART, |
||||
PMUX_VDDIO_DDR, |
||||
PMUX_VDDIO_NAND, |
||||
PMUX_VDDIO_SYS, |
||||
PMUX_VDDIO_AUDIO, |
||||
PMUX_VDDIO_SD, |
||||
PMUX_VDDIO_CAM, |
||||
PMUX_VDDIO_GMI, |
||||
PMUX_VDDIO_PEXCTL, |
||||
PMUX_VDDIO_SDMMC1, |
||||
PMUX_VDDIO_SDMMC3, |
||||
PMUX_VDDIO_SDMMC4, |
||||
|
||||
PMUX_VDDIO_NONE |
||||
}; |
||||
|
||||
/* T114 pin drive group and pin mux registers */ |
||||
#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2) |
||||
#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \ |
||||
PDRIVE_PINGROUP_COUNT) |
||||
struct pmux_tri_ctlr { |
||||
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ |
||||
uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ |
||||
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ |
||||
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ |
||||
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ |
||||
uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */ |
||||
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ |
||||
|
||||
uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */ |
||||
|
||||
uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */ |
||||
uint pmt_reserved5[PMUX_OFFSET]; |
||||
uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */ |
||||
}; |
||||
|
||||
/*
|
||||
* This defines the configuration for a pin, including the function assigned, |
||||
* pull up/down settings and tristate settings. Having set up one of these |
||||
* you can call pinmux_config_pingroup() to configure a pin in one step. Also |
||||
* available is pinmux_config_table() to configure a list of pins. |
||||
*/ |
||||
struct pingroup_config { |
||||
enum pmux_pingrp pingroup; /* pin group PINGRP_... */ |
||||
enum pmux_func func; /* function to assign FUNC_... */ |
||||
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ |
||||
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ |
||||
enum pmux_pin_io io; /* input or output PMUX_PIN_... */ |
||||
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ |
||||
enum pmux_pin_od od; /* open-drain or push-pull driver */ |
||||
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ |
||||
}; |
||||
|
||||
/* Set a pin group to tristate */ |
||||
void pinmux_tristate_enable(enum pmux_pingrp pin); |
||||
|
||||
/* Set a pin group to normal (non tristate) */ |
||||
void pinmux_tristate_disable(enum pmux_pingrp pin); |
||||
|
||||
/* Set the pull up/down feature for a pin group */ |
||||
void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); |
||||
|
||||
/* Set the mux function for a pin group */ |
||||
void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); |
||||
|
||||
/* Set the complete configuration for a pin group */ |
||||
void pinmux_config_pingroup(struct pingroup_config *config); |
||||
|
||||
/* Set a pin group to tristate or normal */ |
||||
void pinmux_set_tristate(enum pmux_pingrp pin, int enable); |
||||
|
||||
/* Set a pin group as input or output */ |
||||
void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); |
||||
|
||||
/**
|
||||
* Configure a list of pin groups |
||||
* |
||||
* @param config List of config items |
||||
* @param len Number of config items in list |
||||
*/ |
||||
void pinmux_config_table(struct pingroup_config *config, int len); |
||||
|
||||
/* Set a group of pins from a table */ |
||||
void pinmux_init(void); |
||||
|
||||
#endif /* _TEGRA114_PINMUX_H_ */ |
||||
@ -0,0 +1,23 @@ |
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef _TEGRA114_PMU_H_ |
||||
#define _TEGRA114_PMU_H_ |
||||
|
||||
/* Set core and CPU voltages to nominal levels */ |
||||
int pmu_set_nominal(void); |
||||
|
||||
#endif /* _TEGRA114_PMU_H_ */ |
||||
@ -0,0 +1,22 @@ |
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_ |
||||
#define _ASM_ARCH_SPL_H_ |
||||
|
||||
#define BOOT_DEVICE_RAM 1 |
||||
|
||||
#endif |
||||
@ -0,0 +1,33 @@ |
||||
/*
|
||||
* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef _TEGRA114_H_ |
||||
#define _TEGRA114_H_ |
||||
|
||||
#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ |
||||
|
||||
#include <asm/arch-tegra/tegra.h> |
||||
|
||||
#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */ |
||||
|
||||
#undef NVBOOTINFOTABLE_BCTSIZE |
||||
#undef NVBOOTINFOTABLE_BCTPTR |
||||
#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */ |
||||
#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ |
||||
|
||||
#define MAX_NUM_CPU 4 |
||||
|
||||
#endif /* TEGRA114_H */ |
||||
Loading…
Reference in new issue