@ -111,17 +111,53 @@
/* Manually set up DDR parameters
*/
# define CONFIG_SYS_DDR_SIZE 128 /* MB */
# define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102
# define CONFIG_SYS_DDR_TIMING_0 0x00220802
# define CONFIG_SYS_DDR_TIMING_1 0x3935d322
# define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca
# define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_AP \
| CSCONFIG_ODT_WR_CFG \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10 )
/* 0x80840102 */
# define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| ( 0 < < TIMING_CFG0_WRT_SHIFT ) \
| ( 0 < < TIMING_CFG0_RRT_SHIFT ) \
| ( 0 < < TIMING_CFG0_WWT_SHIFT ) \
| ( 2 < < TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
| ( 2 < < TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
| ( 8 < < TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
| ( 2 < < TIMING_CFG0_MRS_CYC_SHIFT ) )
/* 0x00220802 */
# define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| ( 9 < < TIMING_CFG1_ACTTOPRE_SHIFT ) \
| ( 3 < < TIMING_CFG1_ACTTORW_SHIFT ) \
| ( 5 < < TIMING_CFG1_CASLAT_SHIFT ) \
| ( 13 < < TIMING_CFG1_REFREC_SHIFT ) \
| ( 3 < < TIMING_CFG1_WRREC_SHIFT ) \
| ( 2 < < TIMING_CFG1_ACTTOACT_SHIFT ) \
| ( 2 < < TIMING_CFG1_WRTORD_SHIFT ) )
/* 0x3935D322 */
# define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
| ( 31 < < TIMING_CFG2_CPO_SHIFT ) \
| ( 2 < < TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
| ( 2 < < TIMING_CFG2_RD_TO_PRE_SHIFT ) \
| ( 2 < < TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
| ( 3 < < TIMING_CFG2_CKE_PLS_SHIFT ) \
| ( 10 < < TIMING_CFG2_FOUR_ACT_SHIFT ) )
/* 0x0F9048CA */
# define CONFIG_SYS_DDR_TIMING_3 0x00000000
# define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
# define CONFIG_SYS_DDR_MODE 0x44400232
# define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
/* 0x02000000 */
# define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
| ( 0x0232 < < SDRAM_MODE_SD_SHIFT ) )
/* 0x44400232 */
# define CONFIG_SYS_DDR_MODE2 0x8000c000
# define CONFIG_SYS_DDR_INTERVAL 0x03200064
# define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
| ( 100 < < SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
/* 0x03200064 */
# define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
# define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000
# define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE )
/* 0x43080000 */
# define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
# endif