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@ -68,25 +68,78 @@ enum { |
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* TCKE = 2 |
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* XSR = 120/6 = 20 |
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*/ |
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#define TDAL_165 6 |
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#define TDPL_165 3 |
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#define TRRD_165 2 |
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#define TRCD_165 3 |
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#define TRP_165 3 |
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#define TRAS_165 7 |
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#define TRC_165 10 |
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#define TRFC_165 21 |
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#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \ |
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(TRAS_165 << 18) | (TRP_165 << 15) | \
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(TRCD_165 << 12) | (TRRD_165 << 9) | \
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(TDPL_165 << 6) | (TDAL_165)) |
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#define TWTR_165 1 |
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#define TCKE_165 1 |
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#define TXP_165 5 |
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#define XSR_165 23 |
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#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ |
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(TXP_165 << 8) | (TWTR_165 << 16)) |
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#define INFINEON_TDAL_165 6 |
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#define INFINEON_TDPL_165 3 |
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#define INFINEON_TRRD_165 2 |
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#define INFINEON_TRCD_165 3 |
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#define INFINEON_TRP_165 3 |
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#define INFINEON_TRAS_165 7 |
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#define INFINEON_TRC_165 10 |
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#define INFINEON_TRFC_165 12 |
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#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \ |
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(INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
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(INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
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(INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
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(INFINEON_TDAL_165)) |
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#define INFINEON_TWTR_165 1 |
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#define INFINEON_TCKE_165 2 |
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#define INFINEON_TXP_165 2 |
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#define INFINEON_XSR_165 20 |
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#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \ |
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(INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
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(INFINEON_TWTR_165 << 16)) |
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/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
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* ACTIMA |
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* TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6 |
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* TDPL (Twr) = 15/6 = 2.5 -> 3 |
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* TRRD = 12/6 = 2 |
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* TRCD = 18/6 = 3 |
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* TRP = 18/6 = 3 |
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* TRAS = 42/6 = 7 |
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* TRC = 60/6 = 10 |
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* TRFC = 125/6 = 21 |
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* ACTIMB |
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* TWTR = 1 |
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* TCKE = 1 |
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* TXSR = 138/6 = 23 |
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* TXP = 25/6 = 4.1 ~5 |
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*/ |
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#define MICRON_TDAL_165 6 |
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#define MICRON_TDPL_165 3 |
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#define MICRON_TRRD_165 2 |
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#define MICRON_TRCD_165 3 |
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#define MICRON_TRP_165 3 |
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#define MICRON_TRAS_165 7 |
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#define MICRON_TRC_165 10 |
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#define MICRON_TRFC_165 21 |
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#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \ |
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(MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
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(MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
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(MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
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(MICRON_TDAL_165)) |
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#define MICRON_TWTR_165 1 |
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#define MICRON_TCKE_165 1 |
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#define MICRON_XSR_165 23 |
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#define MICRON_TXP_165 5 |
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#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \ |
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(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
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(MICRON_TWTR_165 << 16)) |
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#ifdef CONFIG_OMAP3_INFINEON_DDR |
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#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 |
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#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 |
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#endif |
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#ifdef CONFIG_OMAP3_MICRON_DDR |
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#define V_ACTIMA_165 MICRON_V_ACTIMA_165 |
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#define V_ACTIMB_165 MICRON_V_ACTIMB_165 |
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#endif |
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#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) |
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#error "Please choose the right DDR type in config header" |
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#endif |
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/*
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* GPMC settings - |
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