Albert ARIBAUD
12 years ago
commit
3285d4ca19
@ -1,6 +1,6 @@ |
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SECTION 0x0 BOOTABLE |
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TAG LAST |
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LOAD 0x0 spl/u-boot-spl.bin |
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LOAD 0x0 OBJTREE/spl/u-boot-spl.bin |
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CALL 0x14 0x0 |
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LOAD 0x40000100 u-boot.bin |
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LOAD 0x40000100 OBJTREE/u-boot.bin |
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CALL 0x40000100 0x0 |
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@ -1,8 +1,8 @@ |
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SECTION 0x0 BOOTABLE |
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TAG LAST |
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LOAD 0x0 spl/u-boot-spl.bin |
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LOAD 0x0 OBJTREE/spl/u-boot-spl.bin |
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LOAD IVT 0x8000 0x14 |
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CALL HAB 0x8000 0x0 |
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LOAD 0x40000100 u-boot.bin |
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LOAD 0x40000100 OBJTREE/u-boot.bin |
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LOAD IVT 0x8000 0x40000100 |
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CALL HAB 0x8000 0x0 |
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@ -0,0 +1,31 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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ifndef CONFIG_SPL_BUILD |
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COBJS := bg0900.o
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else |
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COBJS := spl_boot.o
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endif |
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,86 @@ |
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/*
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* PPC-AG BG0900 board |
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* |
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* Copyright (C) 2013 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/gpio.h> |
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#include <asm/io.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux-mx28.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/sys_proto.h> |
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#include <linux/mii.h> |
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#include <miiphy.h> |
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#include <netdev.h> |
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#include <errno.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* Functions |
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*/ |
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int board_early_init_f(void) |
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{ |
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/* IO0 clock at 480MHz */ |
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mxs_set_ioclk(MXC_IOCLK0, 480000); |
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/* IO1 clock at 480MHz */ |
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mxs_set_ioclk(MXC_IOCLK1, 480000); |
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/* SSP2 clock at 160MHz */ |
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mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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return mxs_dram_init(); |
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} |
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int board_init(void) |
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{ |
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/* Adress of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
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return 0; |
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} |
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#ifdef CONFIG_CMD_NET |
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int board_eth_init(bd_t *bis) |
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{ |
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struct mxs_clkctrl_regs *clkctrl_regs = |
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; |
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struct eth_device *dev; |
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int ret; |
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ret = cpu_eth_init(bis); |
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/* BG0900 uses ENET_CLK PAD to drive FEC clock */ |
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writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, |
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&clkctrl_regs->hw_clkctrl_enet); |
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/* Reset FEC PHYs */ |
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gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); |
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udelay(200); |
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gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); |
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); |
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if (ret) { |
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puts("FEC MXS: Unable to init FEC0\n"); |
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return ret; |
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} |
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dev = eth_get_dev_by_name("FEC0"); |
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if (!dev) { |
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puts("FEC MXS: Unable to get FEC0 device entry\n"); |
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return -EINVAL; |
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} |
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return ret; |
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} |
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#endif |
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@ -0,0 +1,153 @@ |
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/*
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* PPC-AG BG0900 Boot setup |
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* |
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* Copyright (C) 2013 Marek Vasut <marex@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <config.h> |
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#include <asm/io.h> |
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#include <asm/arch/iomux-mx28.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/sys_proto.h> |
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#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) |
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#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) |
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#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) |
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#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) |
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const iomux_cfg_t iomux_setup[] = { |
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/* DUART */ |
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MX28_PAD_PWM0__DUART_RX, |
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MX28_PAD_PWM1__DUART_TX, |
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/* GPMI NAND */ |
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MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_RDN__GPMI_RDN | |
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(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), |
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MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, |
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MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, |
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/* FEC0 */ |
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MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, |
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MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, |
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MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, |
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MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, |
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MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, |
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MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, |
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MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, |
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MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, |
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MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, |
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/* FEC0 Reset */ |
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MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), |
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/* EMI */ |
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MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, |
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MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, |
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/* SPI2 (for SPI flash) */ |
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MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, |
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MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, |
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MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, |
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MX28_PAD_SSP2_SS0__SSP2_D3 | |
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(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), |
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}; |
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void mxs_adjust_memory_params(uint32_t *dram_vals) |
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{ |
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/*
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* DDR Controller Registers |
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* Manufacturer: Winbond |
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* Device Part Number: W972GG6JB-25I |
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* Clock Freq.: 200MHz |
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* Density: 2Gb |
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* Chip Selects: 1 |
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* Number of Banks: 8 |
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* Row address: 14 |
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* Column address: 10 |
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*/ |
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dram_vals[0x74 / 4] = 0x0102010A; |
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dram_vals[0x98 / 4] = 0x04005003; |
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dram_vals[0x9c / 4] = 0x090000c8; |
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dram_vals[0xa8 / 4] = 0x0036b009; |
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dram_vals[0xac / 4] = 0x03270612; |
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dram_vals[0xb0 / 4] = 0x02020202; |
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dram_vals[0xb4 / 4] = 0x00c80029; |
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dram_vals[0xc0 / 4] = 0x00011900; |
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dram_vals[0x12c / 4] = 0x07400300; |
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dram_vals[0x130 / 4] = 0x07400300; |
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dram_vals[0x2c4 / 4] = 0x02030303; |
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} |
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void board_init_ll(const uint32_t arg, const uint32_t *resptr) |
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{ |
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mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); |
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} |
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@ -0,0 +1,26 @@ |
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#
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# (C) Copyright 2013 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := udoo.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,110 @@ |
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc. |
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* |
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* Author: Fabio Estevam <fabio.estevam@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm/arch/clock.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/iomux.h> |
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#include <asm/arch/mx6-pins.h> |
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#include <asm/errno.h> |
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#include <asm/gpio.h> |
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#include <asm/imx-common/iomux-v3.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/io.h> |
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#include <asm/arch/sys_proto.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
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#define WDT_EN IMX_GPIO_NR(5, 4) |
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#define WDT_TRG IMX_GPIO_NR(3, 19) |
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int dram_init(void) |
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{ |
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gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; |
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return 0; |
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} |
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static iomux_v3_cfg_t const uart2_pads[] = { |
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MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
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}; |
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static iomux_v3_cfg_t const usdhc3_pads[] = { |
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MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
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}; |
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|
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static iomux_v3_cfg_t const wdog_pads[] = { |
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MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), |
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MX6_PAD_EIM_D19__GPIO_3_19, |
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}; |
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|
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static void setup_iomux_uart(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
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} |
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static void setup_iomux_wdog(void) |
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{ |
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
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gpio_direction_output(WDT_TRG, 0); |
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gpio_direction_output(WDT_EN, 1); |
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} |
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|
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static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; |
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|
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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return 1; /* Always present */ |
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} |
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|
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int board_mmc_init(bd_t *bis) |
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{ |
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
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usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
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usdhc_cfg.max_bus_width = 4; |
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|
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return fsl_esdhc_initialize(bis, &usdhc_cfg); |
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} |
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int board_early_init_f(void) |
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{ |
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setup_iomux_wdog(); |
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setup_iomux_uart(); |
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|
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return 0; |
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} |
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|
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int board_init(void) |
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{ |
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/* address of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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|
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return 0; |
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} |
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|
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int checkboard(void) |
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{ |
||||
puts("Board: Udoo\n"); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,97 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Marek Vasut <marex@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __CONFIGS_BG0900_H__ |
||||
#define __CONFIGS_BG0900_H__ |
||||
|
||||
/* System configurations */ |
||||
#define CONFIG_MX28 /* i.MX28 SoC */ |
||||
|
||||
/* U-Boot Commands */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_CMD_BOOTZ |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_GPIO |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_NAND_TRIMFFS |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVEENV |
||||
#define CONFIG_CMD_SETEXPR |
||||
#define CONFIG_CMD_SF |
||||
#define CONFIG_CMD_SPI |
||||
|
||||
/* Memory configuration */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x40000000 /* Base address */ |
||||
#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
|
||||
/* Environment */ |
||||
#define CONFIG_ENV_SIZE (16 * 1024) |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
|
||||
/* FEC Ethernet on SoC */ |
||||
#ifdef CONFIG_CMD_NET |
||||
#define CONFIG_FEC_MXC |
||||
#define CONFIG_NET_MULTI |
||||
#endif |
||||
|
||||
/* SPI */ |
||||
#ifdef CONFIG_CMD_SPI |
||||
#define CONFIG_DEFAULT_SPI_BUS 2 |
||||
#define CONFIG_DEFAULT_SPI_CS 0 |
||||
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 |
||||
|
||||
/* SPI FLASH */ |
||||
#ifdef CONFIG_CMD_SF |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_BAR |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
#define CONFIG_SF_DEFAULT_BUS 2 |
||||
#define CONFIG_SF_DEFAULT_CS 0 |
||||
#define CONFIG_SF_DEFAULT_SPEED 40000000 |
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
||||
|
||||
#define CONFIG_ENV_SPI_BUS 2 |
||||
#define CONFIG_ENV_SPI_CS 0 |
||||
#define CONFIG_ENV_SPI_MAX_HZ 40000000 |
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0 |
||||
#endif |
||||
|
||||
#endif |
||||
|
||||
/* Boot Linux */ |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
#define CONFIG_BOOTARGS "console=ttyAMA0,115200" |
||||
#define CONFIG_BOOTCOMMAND "bootm" |
||||
#define CONFIG_LOADADDR 0x42000000 |
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
|
||||
/* Extra Environment */ |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"update_spi_firmware_filename=u-boot.sb\0" \
|
||||
"update_spi_firmware_maxsz=0x80000\0" \
|
||||
"update_spi_firmware=" /* Update the SPI flash firmware */ \
|
||||
"if sf probe 2:0 ; then " \
|
||||
"if tftp ${update_spi_firmware_filename} ; then " \
|
||||
"sf erase 0x0 +${filesize} ; " \
|
||||
"sf write ${loadaddr} 0x0 ${filesize} ; " \
|
||||
"fi ; " \
|
||||
"fi\0" |
||||
|
||||
/* The rest of the configuration is shared */ |
||||
#include <configs/mxs.h> |
||||
|
||||
#endif /* __CONFIGS_BG0900_H__ */ |
||||
@ -0,0 +1,206 @@ |
||||
/*
|
||||
* Copyright (C) 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for Udoo board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/imx-common/gpio.h> |
||||
#include <asm/sizes.h> |
||||
|
||||
#define CONFIG_MX6 |
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
#define MACH_TYPE_UDOO 4800 |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_UDOO |
||||
|
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_MXC_GPIO |
||||
|
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART2_BASE |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/* Command definition */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#undef CONFIG_CMD_IMLS |
||||
|
||||
#define CONFIG_CMD_BMODE |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) |
||||
#define CONFIG_LOADADDR 0x12000000 |
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000 |
||||
|
||||
/* MMC Configuration */ |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_BOUNCE_BUFFER |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"console=ttymxc1\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x11000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"update_sd_firmware_filename=u-boot.imx\0" \
|
||||
"update_sd_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if mmc dev ${mmcdev}; then " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${uimage}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootm ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootm; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootm; " \
|
||||
"fi;\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT "=> " |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_CBSIZE 256 |
||||
|
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
#define CONFIG_CMDLINE_EDITING |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
|
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_CMD_BOOTZ |
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF |
||||
#define CONFIG_CMD_CACHE |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H * */ |
||||
Loading…
Reference in new issue