The init code for UMC (Unified Memory Controller) and PLL has not been mainlined yet, but U-boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>master
Masahiro Yamada
9 years ago
parent
ad6670ee12
commit
3365b4eb55
@ -0,0 +1,16 @@ |
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD |
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obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
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obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
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early_pinctrl.o pll_spectrum.o umc_init.o
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obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
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obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
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obj-$(CONFIG_SPL_DM) += platdevice.o
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else |
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obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
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endif |
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obj-y += boot-mode.o
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@ -0,0 +1,36 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/io.h> |
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#include <mach/bcu-regs.h> |
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#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) |
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void bcu_init(void) |
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{ |
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int shift; |
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writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ |
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writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ |
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writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ |
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/*
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* 0xe0000000-0xefffffff: Ex-bus |
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* 0xf0000000-0xfbffffff: ASM bus |
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* 0xfc000000-0xffffffff: OCM bus |
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*/ |
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writel(0x24440000, BCSCR5); |
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/* Specify DDR channel */ |
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shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; |
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writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ |
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shift -= 32; |
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writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ |
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shift -= 32; |
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writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ |
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} |
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@ -0,0 +1,97 @@ |
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/*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spl.h> |
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#include <linux/io.h> |
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#include <mach/boot-device.h> |
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#include <mach/sg-regs.h> |
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#include <mach/sbc-regs.h> |
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struct boot_device_info boot_device_table[] = { |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "External Master"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{BOOT_DEVICE_NONE, "Reserved"}, |
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{ /* sentinel */ } |
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}; |
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int get_boot_mode_sel(void) |
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{ |
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return readl(SG_PINMON0) & 0x3f; |
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} |
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u32 spl_boot_device(void) |
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{ |
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int boot_mode; |
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if (boot_is_swapped()) |
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return BOOT_DEVICE_NOR; |
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boot_mode = get_boot_mode_sel(); |
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return boot_device_table[boot_mode].type; |
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} |
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@ -0,0 +1 @@ |
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#include "../ph1-pro4/clkrst_init.c" |
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@ -0,0 +1 @@ |
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#include "../ph1-pro4/early_clkrst_init.c" |
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@ -0,0 +1,23 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <mach/sg-regs.h> |
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void early_pin_init(void) |
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{ |
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/* Comment format: PAD Name -> Function Name */ |
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#ifdef CONFIG_UNIPHIER_SERIAL |
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sg_set_pinsel(63, 0); /* RXD0 */ |
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sg_set_pinsel(64, 1); /* TXD0 */ |
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sg_set_pinsel(65, 0); /* RXD1 */ |
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sg_set_pinsel(66, 1); /* TXD1 */ |
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sg_set_pinsel(96, 2); /* RXD2 */ |
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sg_set_pinsel(102, 2); /* TXD2 */ |
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#endif |
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} |
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@ -0,0 +1,31 @@ |
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/* |
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* On-chip UART initializaion for low-level debugging |
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* |
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/linkage.h> |
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#include <mach/bcu-regs.h> |
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#include <mach/sc-regs.h> |
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#include <mach/sg-regs.h> |
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#include <mach/debug-uart.S> |
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ENTRY(setup_lowlevel_debug) |
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ldr r0, =BCSCR5 |
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ldr r1, =0x24440000 |
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str r1, [r0] |
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ldr r0, =SC_CLKCTRL |
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ldr r1, [r0] |
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orr r1, r1, #SC_CLKCTRL_CEN_PERI |
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str r1, [r0] |
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init_debug_uart r0, r1, r2 |
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set_pinsel 63, 0, r0, r1 |
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set_pinsel 64, 1, r0, r1 |
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mov pc, lr |
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ENDPROC(setup_lowlevel_debug) |
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@ -0,0 +1,52 @@ |
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/types.h> |
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#include <linux/sizes.h> |
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#include <mach/sg-regs.h> |
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static inline u32 sg_memconf_val_ch2(unsigned long size, int num) |
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{ |
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int size_mb = size / num; |
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u32 ret; |
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switch (size_mb) { |
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case SZ_64M: |
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ret = SG_MEMCONF_CH2_SZ_64M; |
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break; |
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case SZ_128M: |
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ret = SG_MEMCONF_CH2_SZ_128M; |
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break; |
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case SZ_256M: |
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ret = SG_MEMCONF_CH2_SZ_256M; |
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break; |
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case SZ_512M: |
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ret = SG_MEMCONF_CH2_SZ_512M; |
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break; |
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default: |
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BUG(); |
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break; |
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} |
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switch (num) { |
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case 1: |
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ret |= SG_MEMCONF_CH2_NUM_1; |
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break; |
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case 2: |
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ret |= SG_MEMCONF_CH2_NUM_2; |
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break; |
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default: |
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BUG(); |
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break; |
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} |
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return ret; |
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} |
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u32 memconf_additional_val(void) |
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{ |
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return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2); |
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} |
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@ -0,0 +1,24 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <mach/sg-regs.h> |
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void pin_init(void) |
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{ |
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#ifdef CONFIG_USB_EHCI_UNIPHIER |
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sg_set_pinsel(13, 0); /* USB0OC */ |
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sg_set_pinsel(14, 1); /* USB0VBUS */ |
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sg_set_pinsel(15, 0); /* USB1OC */ |
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sg_set_pinsel(16, 1); /* USB1VBUS */ |
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sg_set_pinsel(17, 0); /* USB2OC */ |
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sg_set_pinsel(18, 1); /* USB2VBUS */ |
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sg_set_pinsel(19, 0); /* USB3OC */ |
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sg_set_pinsel(20, 1); /* USB3VBUS */ |
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#endif |
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} |
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@ -0,0 +1 @@ |
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#include "../ph1-ld4/platdevice.c" |
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@ -0,0 +1,10 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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void pll_init(void) |
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{ |
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/* add pll init code here */ |
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} |
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@ -0,0 +1,18 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/io.h> |
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#include <mach/sc-regs.h> |
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void enable_dpll_ssc(void) |
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{ |
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u32 tmp; |
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tmp = readl(SC_DPLLCTRL); |
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tmp |= SC_DPLLCTRL_SSC_EN; |
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writel(tmp, SC_DPLLCTRL); |
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} |
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@ -0,0 +1,45 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/io.h> |
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#include <mach/sbc-regs.h> |
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#include <mach/sg-regs.h> |
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void sbc_init(void) |
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{ |
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/* only address/data multiplex mode is supported */ |
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/*
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* Only CS1 is connected to support card. |
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* BKSZ[1:0] should be set to "01". |
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*/ |
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writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); |
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writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); |
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writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); |
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if (boot_is_swapped()) { |
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/*
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* Boot Swap On: boot from external NOR/SRAM |
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* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. |
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* |
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* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank |
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* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals |
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*/ |
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writel(0x0000bc01, SBBASE0); |
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} else { |
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/*
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* Boot Swap Off: boot from mask ROM |
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* 0x00000000-0x01ffffff: mask ROM |
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* 0x02000000-0x03efffff: memory bank (31MB) |
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* 0x03f00000-0x03ffffff: peripherals (1MB) |
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*/ |
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writel(0x0000be01, SBBASE0); /* dummy */ |
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writel(0x0200be01, SBBASE1); |
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} |
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sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */ |
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} |
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@ -0,0 +1,37 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <linux/io.h> |
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#include <mach/sbc-regs.h> |
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#include <mach/sg-regs.h> |
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void sbc_init(void) |
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{ |
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/* only address/data multiplex mode is supported */ |
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/* XECS0 : boot/sub memory (boot swap = off/on) */ |
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writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00); |
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writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01); |
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writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02); |
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/* XECS1 : sub/boot memory (boot swap = off/on) */ |
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writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); |
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writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); |
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writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); |
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/* XECS2 : peripherals */ |
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writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20); |
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writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21); |
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writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22); |
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/* base address regsiters */ |
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writel(0x0000bc01, SBBASE0); |
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writel(0x0400bc01, SBBASE1); |
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writel(0x0800bf01, SBBASE2); |
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sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */ |
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} |
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@ -0,0 +1,9 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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void sg_init(void) |
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{ |
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} |
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@ -0,0 +1,15 @@ |
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/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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int umc_init(void) |
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{ |
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/* add UMC init code here */ |
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printf("Implement memory init code\n"); |
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return 0; |
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} |
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@ -0,0 +1,28 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_UNIPHIER=y |
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CONFIG_MACH_PH1_SLD3=y |
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CONFIG_PFC_MICRO_SUPPORT_CARD=y |
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CONFIG_SYS_TEXT_BASE=0x84000000 |
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CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref" |
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CONFIG_HUSH_PARSER=y |
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# CONFIG_CMD_XIMG is not set |
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# CONFIG_CMD_ENV_EXISTS is not set |
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CONFIG_CMD_NAND=y |
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CONFIG_CMD_I2C=y |
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CONFIG_CMD_USB=y |
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# CONFIG_CMD_FPGA is not set |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_CMD_TFTPPUT=y |
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CONFIG_CMD_PING=y |
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CONFIG_CMD_TIME=y |
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# CONFIG_CMD_MISC is not set |
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CONFIG_NET_RANDOM_ETHADDR=y |
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CONFIG_SPL_DM=y |
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CONFIG_NAND_DENALI=y |
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CONFIG_SYS_NAND_DENALI_64BIT=y |
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CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 |
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CONFIG_SPL_NAND_DENALI=y |
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CONFIG_UNIPHIER_SERIAL=y |
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CONFIG_USB=y |
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CONFIG_USB_EHCI_HCD=y |
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CONFIG_USB_STORAGE=y |
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