Stefan Roese
19 years ago
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3a83ee3021
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34167a36c2
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/*
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/************************************************************************
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* TAISHAN.h - configuration for AMCC 440GX Ref |
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***********************************************************************/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*-----------------------------------------------------------------------
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* High Level Configuration Options |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_TAISHAN 1 /* Board is taishan */ |
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#define CONFIG_440GX 1 /* Specifc GX support */ |
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#define CONFIG_4xx 1 /* ... PPC4xx family */ |
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#undef CFG_DRAM_TEST /* Disable-takes long time! */ |
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the |
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* actual resources get mapped (not physical addresses) |
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*----------------------------------------------------------------------*/ |
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
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#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ |
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#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ |
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
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#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
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#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
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#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ |
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#define CFG_EBC0_FLASH_BASE CFG_FLASH_BASE |
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#define CFG_EBC1_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x01000000) |
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#define CFG_EBC2_LCM_BASE (CFG_PERIPHERAL_BASE + 0x02000000) |
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#define CFG_EBC3_CONN_BASE (CFG_PERIPHERAL_BASE + 0x08000000) |
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#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) |
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in internal SRAM) |
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*----------------------------------------------------------------------*/ |
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#define CFG_TEMP_STACK_OCM 1 |
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#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE |
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#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM*/ |
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) |
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR |
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ |
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#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc*/ |
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/*-----------------------------------------------------------------------
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* Serial Port |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */ |
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#define CONFIG_SERIAL_MULTI 1 /* enable serial multi support */ |
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#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ |
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#define CONFIG_BAUDRATE 115200 |
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#define CFG_BAUDRATE_TABLE \ |
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
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/*-----------------------------------------------------------------------
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* Environment |
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*----------------------------------------------------------------------*/ |
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
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/*-----------------------------------------------------------------------
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* FLASH related |
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*----------------------------------------------------------------------*/ |
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#define CFG_FLASH_CFI |
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#define CFG_FLASH_CFI_DRIVER |
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
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#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} |
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
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#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ |
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#undef CFG_FLASH_CHECKSUM |
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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/* Address and size of Redundant Environment Sector */ |
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
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/*-----------------------------------------------------------------------
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* E2PROM bootstrap configure value |
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*----------------------------------------------------------------------*/ |
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/*
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* 800/133/66 |
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* IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00 |
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*/ |
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/*
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* 800/160/80 |
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* IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00 |
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*/ |
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/*-----------------------------------------------------------------------
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* DDR SDRAM |
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*----------------------------------------------------------------------*/ |
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#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ |
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#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ |
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#define CFG_SDRAM0_TR0 0xC10A401A |
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#undef CONFIG_SDRAM_ECC /* enable ECC support */ |
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/*-----------------------------------------------------------------------
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* I2C |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
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#define CFG_I2C_SLAVE 0x7F |
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#undef CFG_I2C_MULTI_EEPROMS |
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#define CFG_I2C_EEPROM_ADDR 0x50 |
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#define CFG_I2C_EEPROM_ADDR_LEN 1 |
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#define CFG_EEPROM_PAGE_WRITE_ENABLE |
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#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 |
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#define CFG_BOOTSTRAP_IIC_ADDR 0x50 |
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ |
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#define CFG_DTT_MAX_TEMP 70 |
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#define CFG_DTT_LOW_TEMP -30 |
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#define CFG_DTT_HYSTERESIS 3 |
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/*-----------------------------------------------------------------------
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* Environment |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_PREBOOT "echo;" \ |
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo" |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"netdev=eth0\0" \
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"hostname=taishan\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/taishan/uImage\0" \
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"kernel_addr=fc000000\0" \
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"ramdisk_addr=fc180000\0" \
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"load=tftp 100000 /tftpboot/taishan/u-boot.bin\0" \
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"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
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"cp.b 100000 fffc0000 40000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load;run update\0" \
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"fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
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"$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \
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"dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \
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"kozio=bootm 0xffe00000\0" \
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"" |
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#define CONFIG_BOOTCOMMAND "run flash_self" |
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#if 0 |
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
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#else |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#endif |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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/*-----------------------------------------------------------------------
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* Networking |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ |
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#define CONFIG_MII 1 /* MII PHY management */ |
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#define CONFIG_NET_MULTI 1 |
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#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ |
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#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ |
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#define CONFIG_PHY2_ADDR 0x1 |
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#define CONFIG_PHY3_ADDR 0x3 |
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#define CONFIG_ET1011C_PHY 1 |
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#define CONFIG_HAS_ETH0 |
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#define CONFIG_HAS_ETH1 |
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#define CONFIG_HAS_ETH2 |
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#define CONFIG_HAS_ETH3 |
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
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#define CONFIG_PHY_RESET_DELAY 1000 |
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
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#define CONFIG_NETCONSOLE /* include NetConsole support */ |
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/*-----------------------------------------------------------------------
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* Console/Commands/Parser |
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*----------------------------------------------------------------------*/ |
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
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CFG_CMD_ASKENV | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_DTT | \
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CFG_CMD_ELF | \
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CFG_CMD_EEPROM | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO) |
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
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#include <cmd_confdefs.h> |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options |
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*----------------------------------------------------------------------*/ |
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#define CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
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#define CONFIG_LOOPW 1 /* enable loopw command */ |
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
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/*-----------------------------------------------------------------------
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* PCI stuff |
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*----------------------------------------------------------------------- |
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*/ |
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/* General PCI */ |
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#define CONFIG_PCI /* include pci support */ |
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#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
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#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */ |
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ |
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/* Board-specific PCI */ |
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#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ |
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#define CFG_PCI_TARGET_INIT /* let board init pci target */ |
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
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#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*----------------------------------------------------------------------*/ |
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#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ |
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#define CFG_CACHELINE_SIZE 32 /* ... */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
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#endif |
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/*
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* Internal Definitions |
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* |
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* Boot Flags |
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*/ |
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
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#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
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#endif |
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#endif /* __CONFIG_H */ |
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