Bring in required device tree files from Linux. Since mainline Linux is somewhat behind, use the files from the Chromium tree. We can re-sync once further code is acccepted upstream. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
10 years ago
parent
765a1b1eb3
commit
344c837686
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/* |
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* Device Tree Source for RK3288 SoC thermal |
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* |
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#include <dt-bindings/thermal/thermal.h> |
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|
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reserve_thermal: reserve_thermal { |
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polling-delay-passive = <1000>; /* milliseconds */ |
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polling-delay = <5000>; /* milliseconds */ |
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|
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/* sensor ID */ |
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thermal-sensors = <&tsadc 0>; |
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}; |
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cpu_thermal: cpu_thermal { |
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polling-delay-passive = <100>; /* milliseconds */ |
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polling-delay = <5000>; /* milliseconds */ |
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|
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/* sensor ID */ |
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thermal-sensors = <&tsadc 1>; |
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linux,hwmon; |
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|
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trips { |
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cpu_alert0: cpu_alert0 { |
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temperature = <70000>; /* millicelsius */ |
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hysteresis = <2000>; /* millicelsius */ |
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type = "passive"; |
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}; |
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cpu_alert1: cpu_alert1 { |
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temperature = <75000>; /* millicelsius */ |
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hysteresis = <2000>; /* millicelsius */ |
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type = "passive"; |
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}; |
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cpu_crit: cpu_crit { |
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temperature = <100000>; /* millicelsius */ |
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hysteresis = <2000>; /* millicelsius */ |
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type = "critical"; |
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}; |
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}; |
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|
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cooling-maps { |
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map0 { |
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trip = <&cpu_alert0>; |
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cooling-device = |
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<&cpu0 THERMAL_NO_LIMIT 6>; |
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}; |
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map1 { |
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trip = <&cpu_alert1>; |
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cooling-device = |
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
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}; |
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}; |
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}; |
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|
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gpu_thermal: gpu_thermal { |
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polling-delay-passive = <100>; /* milliseconds */ |
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polling-delay = <5000>; /* milliseconds */ |
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|
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/* sensor ID */ |
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thermal-sensors = <&tsadc 2>; |
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linux,hwmon; |
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trips { |
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gpu_alert0: gpu_alert0 { |
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temperature = <80000>; /* millicelsius */ |
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hysteresis = <2000>; /* millicelsius */ |
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type = "passive"; |
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}; |
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gpu_crit: gpu_crit { |
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temperature = <100000>; /* millicelsius */ |
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hysteresis = <2000>; /* millicelsius */ |
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type = "critical"; |
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}; |
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}; |
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|
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cooling-maps { |
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map0 { |
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trip = <&gpu_alert0>; |
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cooling-device = |
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
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}; |
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}; |
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}; |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,61 @@ |
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* Rockchip RK3188/RK3066 Clock and Reset Unit |
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|
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The RK3188/RK3066 clock controller generates and supplies clock to various |
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controllers within the SoC and also implements a reset controller for SoC |
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peripherals. |
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|
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Required Properties: |
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|
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- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or |
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"rockchip,rk3066a-cru" |
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- reg: physical base address of the controller and length of memory mapped |
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region. |
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- #clock-cells: should be 1. |
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- #reset-cells: should be 1. |
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|
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Optional Properties: |
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|
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- rockchip,grf: phandle to the syscon managing the "general register files" |
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If missing pll rates are not changable, due to the missing pll lock status. |
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|
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Each clock is assigned an identifier and client nodes can use this identifier |
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to specify the clock which they consume. All available clocks are defined as |
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preprocessor macros in the dt-bindings/clock/rk3188-cru.h and |
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dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. |
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Similar macros exist for the reset sources in these files. |
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|
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External clocks: |
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|
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There are several clocks that are generated outside the SoC. It is expected |
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that they are defined using standard clock bindings with following |
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clock-output-names: |
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- "xin24m" - crystal input - required, |
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- "xin32k" - rtc clock - optional, |
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- "xin27m" - 27mhz crystal input on rk3066 - optional, |
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- "ext_hsadc" - external HSADC clock - optional, |
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- "ext_cif0" - external camera clock - optional, |
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- "ext_rmii" - external RMII clock - optional, |
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- "ext_jtag" - externalJTAG clock - optional |
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|
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Example: Clock controller node: |
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cru: cru@20000000 { |
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compatible = "rockchip,rk3188-cru"; |
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reg = <0x20000000 0x1000>; |
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rockchip,grf = <&grf>; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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}; |
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|
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Example: UART controller node that consumes the clock generated by the clock |
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controller: |
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uart0: serial@10124000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x10124000 0x400>; |
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <1>; |
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clocks = <&cru SCLK_UART0>; |
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}; |
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@ -0,0 +1,61 @@ |
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* Rockchip RK3288 Clock and Reset Unit |
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|
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The RK3288 clock controller generates and supplies clock to various |
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controllers within the SoC and also implements a reset controller for SoC |
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peripherals. |
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|
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Required Properties: |
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|
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- compatible: should be "rockchip,rk3288-cru" |
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- reg: physical base address of the controller and length of memory mapped |
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region. |
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- #clock-cells: should be 1. |
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- #reset-cells: should be 1. |
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|
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Optional Properties: |
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|
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- rockchip,grf: phandle to the syscon managing the "general register files" |
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If missing pll rates are not changable, due to the missing pll lock status. |
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|
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Each clock is assigned an identifier and client nodes can use this identifier |
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to specify the clock which they consume. All available clocks are defined as |
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preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be |
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used in device tree sources. Similar macros exist for the reset sources in |
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these files. |
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|
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External clocks: |
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|
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There are several clocks that are generated outside the SoC. It is expected |
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that they are defined using standard clock bindings with following |
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clock-output-names: |
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- "xin24m" - crystal input - required, |
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- "xin32k" - rtc clock - optional, |
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- "ext_i2s" - external I2S clock - optional, |
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- "ext_hsadc" - external HSADC clock - optional, |
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- "ext_edp_24m" - external display port clock - optional, |
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- "ext_vip" - external VIP clock - optional, |
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- "ext_isp" - external ISP clock - optional, |
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- "ext_jtag" - external JTAG clock - optional |
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|
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Example: Clock controller node: |
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cru: cru@20000000 { |
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compatible = "rockchip,rk3188-cru"; |
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reg = <0x20000000 0x1000>; |
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rockchip,grf = <&grf>; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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}; |
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Example: UART controller node that consumes the clock generated by the clock |
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controller: |
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uart0: serial@10124000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x10124000 0x400>; |
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <1>; |
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clocks = <&cru SCLK_UART0>; |
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}; |
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@ -0,0 +1,155 @@ |
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Rockchip Dynamic Memory Controller Driver |
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Required properties: |
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- compatible: "rockchip,rk3288-dmc", "syscon" |
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- rockchip,cru: this driver should access cru regs, so need get cru here |
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- rockchip,grf: this driver should access grf regs, so need get grf here |
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- rockchip,pmu: this driver should access pmu regs, so need get pmu here |
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- rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here |
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- rockchip,noc: this driver should access noc regs, so need get noc here |
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- reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address |
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- clock: must include clock specifiers corresponding to entries in the clock-names property. |
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- clock-output-names: from common clock binding to override the default output clock name |
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Must contain |
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pclk_ddrupctl0: support clock for access protocol controller registers of channel 0 |
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pclk_publ0: support clock for access phy controller registers of channel 0 |
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pclk_ddrupctl1: support clock for access protocol controller registers of channel 1 |
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pclk_publ1: support clock for access phy controller registers of channel 1 |
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arm_clk: for get arm frequency |
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-logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-supply here |
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-timings: |
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Must contain |
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rockchip,odt-disable-freq: if ddr clock frequency low than odt-disable-freq,this driver should disable DDR ODT |
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rockchip,dll-disable-freq: if ddr clock frequency low than dll-disable-freq,this driver should disable DDR DLL |
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rockchip,sr-enable-freq: if ddr clock frequency high than sr-enable-freq,this driver should enable the automatic self refresh function |
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rockchip,pd-enable-freq: if ddr clock frequency high than pd-enable-freq,this driver should enable the automatic power down function |
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rockchip,auto-self-refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mode if the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self refresh function is disabled when auto-self-refresh-cnt=0. |
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rockchip,auto-power-down-cnt: Power-down idle period. Memories are placed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic power down function is disabled when auto-power-down-cnt=0. |
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rockchip,ddr-speed-bin: DDR3 type,AC timing parameters from the memory data-sheet |
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0.DDR3_800D (5-5-5) |
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1.DDR3_800E (6-6-6) |
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2.DDR3_1066E (6-6-6) |
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3.DDR3_1066F (7-7-7) |
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4.DDR3_1066G (8-8-8) |
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5.DDR3_1333F (7-7-7) |
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6.DDR3_1333G (8-8-8) |
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7.DDR3_1333H (9-9-9) |
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8.DDR3_1333J (10-10-10) |
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9.DDR3_1600G (8-8-8) |
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10.DDR3_1600H (9-9-9) |
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11.DDR3_1600J (10-10-10) |
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12.DDR3_1600K (11-11-11) |
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13.DDR3_1866J (10-10-10) |
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14.DDR3_1866K (11-11-11) |
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15.DDR3_1866L (12-12-12) |
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16.DDR3_1866M (13-13-13) |
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17.DDR3_2133K (11-11-11) |
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18.DDR3_2133L (12-12-12) |
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19.DDR3_2133M (13-13-13) |
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20.DDR3_2133N (14-14-14) |
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21.DDR3_DEFAULT |
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rockchip,trcd: tRCD,AC timing parameters from the memory data-sheet |
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rockchip,trp: tRP,AC timing parameters from the memory data-sheet |
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-rockchip,num-channels: number of SDRAM channels (1 or 2) |
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-rockchip,pctl-timing: parameters for the SDRAM setup, in this order: |
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togcnt1u |
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tinit |
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trsth |
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togcnt100n |
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trefi |
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tmrd |
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trfc |
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trp |
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trtw |
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tal |
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tcl |
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tcwl |
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tras |
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trc |
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trcd |
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trrd |
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trtp |
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twr |
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twtr |
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texsr |
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txp |
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txpdll |
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tzqcs |
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tzqcsi |
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tdqs |
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tcksre |
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tcksrx |
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tcke |
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tmod |
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trstl |
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tzqcl |
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tmrr |
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tckesr |
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tdpd |
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-rockchip,phy-timing: PHY timing information in this order: |
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dtpr0 |
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dtpr1 |
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dtpr2 |
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mr0..mr3 |
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-rockchip,sdram-channel: SDRAM channel information, each 8 bits. Both channels |
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will be set up the same. The parameters are in this order: |
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rank |
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col |
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bk |
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bw |
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dbw |
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row_3_4 |
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cs0_row |
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cs1_row |
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- rockchip,sdram-params: SDRAM base parameters, in this order: |
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NOC timing - value for ddrtiming register |
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NOC activate - value for activate register |
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ddrconf - value for ddrconf register |
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DDR frequency in MHz |
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DRAM type (3=DDR3, 6=LPDDR3) |
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stride - stride value for soc_con2 register |
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odt - 1 to enable DDR ODT, 0 to disable |
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Example: |
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dmc: dmc@ff610000 { |
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compatible = "rockchip,rk3288-dmc", "syscon"; |
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rockchip,cru = <&cru>; |
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rockchip,grf = <&grf>; |
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rockchip,pmu = <&pmu>; |
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rockchip,sgrf = <&sgrf>; |
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rockchip,noc = <&noc>; |
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reg = <0xff610000 0x3fc |
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0xff620000 0x294 |
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0xff630000 0x3fc |
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0xff640000 0x294>; |
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clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>, |
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<&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>, |
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<&cru ARMCLK>; |
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clock-names = "pclk_ddrupctl0", "pclk_publ0", |
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"pclk_ddrupctl1", "pclk_publ1", |
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"arm_clk"; |
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}; |
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&dmc { |
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logic-supply = <&vdd_logic>; |
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timings { |
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rockchip,odt-disable-freq = <333000000>; |
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rockchip,dll-disable-freq = <333000000>; |
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rockchip,sr-enable-freq = <333000000>; |
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rockchip,pd-enable-freq = <666000000>; |
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rockchip,auto-self-refresh-cnt = <0>; |
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rockchip,auto-power-down-cnt = <64>; |
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rockchip,ddr-speed-bin = <21>; |
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rockchip,trcd = <10>; |
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rockchip,trp = <10>; |
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}; |
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rockchip,num-channels = <2>; |
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rockchip,pctl-timing = <0x29a 0x1f4 0xc8 0x42 0x4e 0x4 0xea 0xa |
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0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 |
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0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 |
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0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 |
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0x5 0x0>; |
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rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 |
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0xa60 0x40 0x10 0x0>; |
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rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>; |
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rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; |
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}; |
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@ -0,0 +1,77 @@ |
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Device Tree Clock bindings for arch-rockchip |
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|
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This binding uses the common clock binding[1]. |
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|
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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|
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== Gate clocks == |
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|
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These bindings are deprecated! |
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Please use the soc specific CRU bindings instead. |
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|
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The gate registers form a continuos block which makes the dt node |
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structure a matter of taste, as either all gates can be put into |
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one gate clock spanning all registers or they can be divided into |
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the 10 individual gates containing 16 clocks each. |
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The code supports both approaches. |
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|
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Required properties: |
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- compatible : "rockchip,rk2928-gate-clk" |
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- reg : shall be the control register address(es) for the clock. |
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- #clock-cells : from common clock binding; shall be set to 1 |
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- clock-output-names : the corresponding gate names that the clock controls |
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- clocks : should contain the parent clock for each individual gate, |
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therefore the number of clocks elements should match the number of |
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clock-output-names |
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|
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Example using multiple gate clocks: |
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|
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clk_gates0: gate-clk@200000d0 { |
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compatible = "rockchip,rk2928-gate-clk"; |
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reg = <0x200000d0 0x4>; |
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clocks = <&dummy>, <&dummy>, |
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<&dummy>, <&dummy>, |
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<&dummy>, <&dummy>, |
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<&dummy>, <&dummy>, |
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<&dummy>, <&dummy>, |
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<&dummy>, <&dummy>, |
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<&dummy>, <&dummy>, |
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<&dummy>, <&dummy>; |
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|
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clock-output-names = |
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"gate_core_periph", "gate_cpu_gpll", |
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"gate_ddrphy", "gate_aclk_cpu", |
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"gate_hclk_cpu", "gate_pclk_cpu", |
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"gate_atclk_cpu", "gate_i2s0", |
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"gate_i2s0_frac", "gate_i2s1", |
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"gate_i2s1_frac", "gate_i2s2", |
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"gate_i2s2_frac", "gate_spdif", |
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"gate_spdif_frac", "gate_testclk"; |
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|
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#clock-cells = <1>; |
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}; |
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|
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clk_gates1: gate-clk@200000d4 { |
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compatible = "rockchip,rk2928-gate-clk"; |
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reg = <0x200000d4 0x4>; |
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clocks = <&xin24m>, <&xin24m>, |
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<&xin24m>, <&dummy>, |
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<&dummy>, <&xin24m>, |
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<&xin24m>, <&dummy>, |
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<&xin24m>, <&dummy>, |
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<&xin24m>, <&dummy>, |
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<&xin24m>, <&dummy>, |
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<&xin24m>, <&dummy>; |
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|
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clock-output-names = |
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"gate_timer0", "gate_timer1", |
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"gate_timer2", "gate_jtag", |
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"gate_aclk_lcdc1_src", "gate_otgphy0", |
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"gate_otgphy1", "gate_ddr_gpll", |
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"gate_uart0", "gate_frac_uart0", |
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"gate_uart1", "gate_frac_uart1", |
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"gate_uart2", "gate_frac_uart2", |
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"gate_uart3", "gate_frac_uart3"; |
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|
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#clock-cells = <1>; |
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}; |
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@ -0,0 +1,157 @@ |
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* Rockchip Pinmux Controller |
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|
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The Rockchip Pinmux Controller, enables the IC |
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to share one PAD to several functional blocks. The sharing is done by |
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multiplexing the PAD input/output signals. For each PAD there are several |
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muxing options with option 0 being the use as a GPIO. |
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|
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Please refer to pinctrl-bindings.txt in this directory for details of the |
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common pinctrl bindings used by client devices, including the meaning of the |
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phrase "pin configuration node". |
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|
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The Rockchip pin configuration node is a node of a group of pins which can be |
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used for a specific device or function. This node represents both mux and |
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config of the pins in that group. The 'pins' selects the function mode(also |
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named pin mode) this pin can work on and the 'config' configures various pad |
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settings such as pull-up, etc. |
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|
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The pins are grouped into up to 5 individual pin banks which need to be |
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defined as gpio sub-nodes of the pinmux controller. |
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|
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Required properties for iomux controller: |
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- compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl" |
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"rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl" |
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"rockchip,rk3288-pinctrl" |
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- rockchip,grf: phandle referencing a syscon providing the |
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"general register files" |
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|
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Optional properties for iomux controller: |
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- rockchip,pmu: phandle referencing a syscon providing the pmu registers |
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as some SoCs carry parts of the iomux controller registers there. |
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Required for at least rk3188 and rk3288. |
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|
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Deprecated properties for iomux controller: |
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- reg: first element is the general register space of the iomux controller |
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It should be large enough to contain also separate pull registers. |
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second element is the separate pull register space of the rk3188. |
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Use rockchip,grf and rockchip,pmu described above instead. |
||||
|
||||
Required properties for gpio sub nodes: |
||||
- compatible: "rockchip,gpio-bank" |
||||
- reg: register of the gpio bank (different than the iomux registerset) |
||||
- interrupts: base interrupt of the gpio bank in the interrupt controller |
||||
- clocks: clock that drives this bank |
||||
- gpio-controller: identifies the node as a gpio controller and pin bank. |
||||
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO |
||||
binding is used, the amount of cells must be specified as 2. See generic |
||||
GPIO binding documentation for description of particular cells. |
||||
- interrupt-controller: identifies the controller node as interrupt-parent. |
||||
- #interrupt-cells: the value of this property should be 2 and the interrupt |
||||
cells should use the standard two-cell scheme described in |
||||
bindings/interrupt-controller/interrupts.txt |
||||
|
||||
Deprecated properties for gpio sub nodes: |
||||
- compatible: "rockchip,rk3188-gpio-bank0" |
||||
- reg: second element: separate pull register for rk3188 bank0, use |
||||
rockchip,pmu described above instead |
||||
|
||||
Required properties for pin configuration node: |
||||
- rockchip,pins: 3 integers array, represents a group of pins mux and config |
||||
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. |
||||
The MUX 0 means gpio and MUX 1 to N mean the specific device function. |
||||
The phandle of a node containing the generic pinconfig options |
||||
to use, as described in pinctrl-bindings.txt in this directory. |
||||
|
||||
Examples: |
||||
|
||||
#include <dt-bindings/pinctrl/rockchip.h> |
||||
|
||||
... |
||||
|
||||
pinctrl@20008000 { |
||||
compatible = "rockchip,rk3066a-pinctrl"; |
||||
rockchip,grf = <&grf>; |
||||
|
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
gpio0: gpio0@20034000 { |
||||
compatible = "rockchip,gpio-bank"; |
||||
reg = <0x20034000 0x100>; |
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clk_gates8 9>; |
||||
|
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
|
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
}; |
||||
|
||||
... |
||||
|
||||
pcfg_pull_default: pcfg_pull_default { |
||||
bias-pull-pin-default |
||||
}; |
||||
|
||||
uart2 { |
||||
uart2_xfer: uart2-xfer { |
||||
rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>, |
||||
<RK_GPIO1 9 1 &pcfg_pull_default>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
uart2: serial@20064000 { |
||||
compatible = "snps,dw-apb-uart"; |
||||
reg = <0x20064000 0x400>; |
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
||||
reg-shift = <2>; |
||||
reg-io-width = <1>; |
||||
clocks = <&mux_uart2>; |
||||
status = "okay"; |
||||
|
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&uart2_xfer>; |
||||
}; |
||||
|
||||
Example for rk3188: |
||||
|
||||
pinctrl@20008000 { |
||||
compatible = "rockchip,rk3188-pinctrl"; |
||||
rockchip,grf = <&grf>; |
||||
rockchip,pmu = <&pmu>; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
|
||||
gpio0: gpio0@0x2000a000 { |
||||
compatible = "rockchip,rk3188-gpio-bank0"; |
||||
reg = <0x2000a000 0x100>; |
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clk_gates8 9>; |
||||
|
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
|
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
}; |
||||
|
||||
gpio1: gpio1@0x2003c000 { |
||||
compatible = "rockchip,gpio-bank"; |
||||
reg = <0x2003c000 0x100>; |
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&clk_gates8 10>; |
||||
|
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
|
||||
interrupt-controller; |
||||
#interrupt-cells = <2>; |
||||
}; |
||||
|
||||
... |
||||
|
||||
}; |
||||
@ -0,0 +1,68 @@ |
||||
* Temperature Sensor ADC (TSADC) on rockchip SoCs |
||||
|
||||
Required properties: |
||||
- compatible : "rockchip,rk3288-tsadc" |
||||
- reg : physical base address of the controller and length of memory mapped |
||||
region. |
||||
- interrupts : The interrupt number to the cpu. The interrupt specifier format |
||||
depends on the interrupt controller. |
||||
- clocks : Must contain an entry for each entry in clock-names. |
||||
- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for |
||||
the peripheral clock. |
||||
- resets : Must contain an entry for each entry in reset-names. |
||||
See ../reset/reset.txt for details. |
||||
- reset-names : Must include the name "tsadc-apb". |
||||
- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. |
||||
- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. |
||||
- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. |
||||
- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW |
||||
1:HIGH. |
||||
|
||||
Exiample: |
||||
tsadc: tsadc@ff280000 { |
||||
compatible = "rockchip,rk3288-tsadc"; |
||||
reg = <0xff280000 0x100>; |
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
||||
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; |
||||
clock-names = "tsadc", "apb_pclk"; |
||||
resets = <&cru SRST_TSADC>; |
||||
reset-names = "tsadc-apb"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&otp_out>; |
||||
#thermal-sensor-cells = <1>; |
||||
rockchip,hw-tshut-temp = <95000>; |
||||
rockchip,hw-tshut-mode = <0>; |
||||
rockchip,hw-tshut-polarity = <0>; |
||||
}; |
||||
|
||||
Example: referring to thermal sensors: |
||||
thermal-zones { |
||||
cpu_thermal: cpu_thermal { |
||||
polling-delay-passive = <1000>; /* milliseconds */ |
||||
polling-delay = <5000>; /* milliseconds */ |
||||
|
||||
/* sensor ID */ |
||||
thermal-sensors = <&tsadc 1>; |
||||
|
||||
trips { |
||||
cpu_alert0: cpu_alert { |
||||
temperature = <70000>; /* millicelsius */ |
||||
hysteresis = <2000>; /* millicelsius */ |
||||
type = "passive"; |
||||
}; |
||||
cpu_crit: cpu_crit { |
||||
temperature = <90000>; /* millicelsius */ |
||||
hysteresis = <2000>; /* millicelsius */ |
||||
type = "critical"; |
||||
}; |
||||
}; |
||||
|
||||
cooling-maps { |
||||
map0 { |
||||
trip = <&cpu_alert0>; |
||||
cooling-device = |
||||
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
@ -0,0 +1,370 @@ |
||||
/*
|
||||
* Copyright (c) 2014 MundoReader S.L. |
||||
* Author: Heiko Stuebner <heiko@sntech.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* core clocks */ |
||||
#define PLL_APLL 1 |
||||
#define PLL_DPLL 2 |
||||
#define PLL_CPLL 3 |
||||
#define PLL_GPLL 4 |
||||
#define PLL_NPLL 5 |
||||
#define ARMCLK 6 |
||||
|
||||
/* sclk gates (special clocks) */ |
||||
#define SCLK_GPU 64 |
||||
#define SCLK_SPI0 65 |
||||
#define SCLK_SPI1 66 |
||||
#define SCLK_SPI2 67 |
||||
#define SCLK_SDMMC 68 |
||||
#define SCLK_SDIO0 69 |
||||
#define SCLK_SDIO1 70 |
||||
#define SCLK_EMMC 71 |
||||
#define SCLK_TSADC 72 |
||||
#define SCLK_SARADC 73 |
||||
#define SCLK_PS2C 74 |
||||
#define SCLK_NANDC0 75 |
||||
#define SCLK_NANDC1 76 |
||||
#define SCLK_UART0 77 |
||||
#define SCLK_UART1 78 |
||||
#define SCLK_UART2 79 |
||||
#define SCLK_UART3 80 |
||||
#define SCLK_UART4 81 |
||||
#define SCLK_I2S0 82 |
||||
#define SCLK_SPDIF 83 |
||||
#define SCLK_SPDIF8CH 84 |
||||
#define SCLK_TIMER0 85 |
||||
#define SCLK_TIMER1 86 |
||||
#define SCLK_TIMER2 87 |
||||
#define SCLK_TIMER3 88 |
||||
#define SCLK_TIMER4 89 |
||||
#define SCLK_TIMER5 90 |
||||
#define SCLK_TIMER6 91 |
||||
#define SCLK_HSADC 92 |
||||
#define SCLK_OTGPHY0 93 |
||||
#define SCLK_OTGPHY1 94 |
||||
#define SCLK_OTGPHY2 95 |
||||
#define SCLK_OTG_ADP 96 |
||||
#define SCLK_HSICPHY480M 97 |
||||
#define SCLK_HSICPHY12M 98 |
||||
#define SCLK_MACREF 99 |
||||
#define SCLK_LCDC_PWM0 100 |
||||
#define SCLK_LCDC_PWM1 101 |
||||
#define SCLK_MAC_RX 102 |
||||
#define SCLK_MAC_TX 103 |
||||
#define SCLK_EDP_24M 104 |
||||
#define SCLK_EDP 105 |
||||
#define SCLK_RGA 106 |
||||
#define SCLK_ISP 107 |
||||
#define SCLK_ISP_JPE 108 |
||||
#define SCLK_HDMI_HDCP 109 |
||||
#define SCLK_HDMI_CEC 110 |
||||
#define SCLK_HEVC_CABAC 111 |
||||
#define SCLK_HEVC_CORE 112 |
||||
#define SCLK_I2S0_OUT 113 |
||||
#define SCLK_SDMMC_DRV 114 |
||||
#define SCLK_SDIO0_DRV 115 |
||||
#define SCLK_SDIO1_DRV 116 |
||||
#define SCLK_EMMC_DRV 117 |
||||
#define SCLK_SDMMC_SAMPLE 118 |
||||
#define SCLK_SDIO0_SAMPLE 119 |
||||
#define SCLK_SDIO1_SAMPLE 120 |
||||
#define SCLK_EMMC_SAMPLE 121 |
||||
#define SCLK_USBPHY480M_SRC 122 |
||||
#define SCLK_PVTM_CORE 123 |
||||
#define SCLK_PVTM_GPU 124 |
||||
|
||||
#define SCLK_MAC 151 |
||||
#define SCLK_MACREF_OUT 152 |
||||
|
||||
#define DCLK_VOP0 190 |
||||
#define DCLK_VOP1 191 |
||||
|
||||
/* aclk gates */ |
||||
#define ACLK_GPU 192 |
||||
#define ACLK_DMAC1 193 |
||||
#define ACLK_DMAC2 194 |
||||
#define ACLK_MMU 195 |
||||
#define ACLK_GMAC 196 |
||||
#define ACLK_VOP0 197 |
||||
#define ACLK_VOP1 198 |
||||
#define ACLK_CRYPTO 199 |
||||
#define ACLK_RGA 200 |
||||
#define ACLK_RGA_NIU 201 |
||||
#define ACLK_IEP 202 |
||||
#define ACLK_VIO0_NIU 203 |
||||
#define ACLK_VIP 204 |
||||
#define ACLK_ISP 205 |
||||
#define ACLK_VIO1_NIU 206 |
||||
#define ACLK_HEVC 207 |
||||
#define ACLK_VCODEC 208 |
||||
#define ACLK_CPU 209 |
||||
#define ACLK_PERI 210 |
||||
|
||||
/* pclk gates */ |
||||
#define PCLK_GPIO0 320 |
||||
#define PCLK_GPIO1 321 |
||||
#define PCLK_GPIO2 322 |
||||
#define PCLK_GPIO3 323 |
||||
#define PCLK_GPIO4 324 |
||||
#define PCLK_GPIO5 325 |
||||
#define PCLK_GPIO6 326 |
||||
#define PCLK_GPIO7 327 |
||||
#define PCLK_GPIO8 328 |
||||
#define PCLK_GRF 329 |
||||
#define PCLK_SGRF 330 |
||||
#define PCLK_PMU 331 |
||||
#define PCLK_I2C0 332 |
||||
#define PCLK_I2C1 333 |
||||
#define PCLK_I2C2 334 |
||||
#define PCLK_I2C3 335 |
||||
#define PCLK_I2C4 336 |
||||
#define PCLK_I2C5 337 |
||||
#define PCLK_SPI0 338 |
||||
#define PCLK_SPI1 339 |
||||
#define PCLK_SPI2 340 |
||||
#define PCLK_UART0 341 |
||||
#define PCLK_UART1 342 |
||||
#define PCLK_UART2 343 |
||||
#define PCLK_UART3 344 |
||||
#define PCLK_UART4 345 |
||||
#define PCLK_TSADC 346 |
||||
#define PCLK_SARADC 347 |
||||
#define PCLK_SIM 348 |
||||
#define PCLK_GMAC 349 |
||||
#define PCLK_PWM 350 |
||||
#define PCLK_RKPWM 351 |
||||
#define PCLK_PS2C 352 |
||||
#define PCLK_TIMER 353 |
||||
#define PCLK_TZPC 354 |
||||
#define PCLK_EDP_CTRL 355 |
||||
#define PCLK_MIPI_DSI0 356 |
||||
#define PCLK_MIPI_DSI1 357 |
||||
#define PCLK_MIPI_CSI 358 |
||||
#define PCLK_LVDS_PHY 359 |
||||
#define PCLK_HDMI_CTRL 360 |
||||
#define PCLK_VIO2_H2P 361 |
||||
#define PCLK_CPU 362 |
||||
#define PCLK_PERI 363 |
||||
#define PCLK_DDRUPCTL0 364 |
||||
#define PCLK_PUBL0 365 |
||||
#define PCLK_DDRUPCTL1 366 |
||||
#define PCLK_PUBL1 367 |
||||
#define PCLK_WDT 368 |
||||
|
||||
/* hclk gates */ |
||||
#define HCLK_GPS 448 |
||||
#define HCLK_OTG0 449 |
||||
#define HCLK_USBHOST0 450 |
||||
#define HCLK_USBHOST1 451 |
||||
#define HCLK_HSIC 452 |
||||
#define HCLK_NANDC0 453 |
||||
#define HCLK_NANDC1 454 |
||||
#define HCLK_TSP 455 |
||||
#define HCLK_SDMMC 456 |
||||
#define HCLK_SDIO0 457 |
||||
#define HCLK_SDIO1 458 |
||||
#define HCLK_EMMC 459 |
||||
#define HCLK_HSADC 460 |
||||
#define HCLK_CRYPTO 461 |
||||
#define HCLK_I2S0 462 |
||||
#define HCLK_SPDIF 463 |
||||
#define HCLK_SPDIF8CH 464 |
||||
#define HCLK_VOP0 465 |
||||
#define HCLK_VOP1 466 |
||||
#define HCLK_ROM 467 |
||||
#define HCLK_IEP 468 |
||||
#define HCLK_ISP 469 |
||||
#define HCLK_RGA 470 |
||||
#define HCLK_VIO_AHB_ARBI 471 |
||||
#define HCLK_VIO_NIU 472 |
||||
#define HCLK_VIP 473 |
||||
#define HCLK_VIO2_H2P 474 |
||||
#define HCLK_HEVC 475 |
||||
#define HCLK_VCODEC 476 |
||||
#define HCLK_CPU 477 |
||||
#define HCLK_PERI 478 |
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1) |
||||
|
||||
/* soft-reset indices */ |
||||
#define SRST_CORE0 0 |
||||
#define SRST_CORE1 1 |
||||
#define SRST_CORE2 2 |
||||
#define SRST_CORE3 3 |
||||
#define SRST_CORE0_PO 4 |
||||
#define SRST_CORE1_PO 5 |
||||
#define SRST_CORE2_PO 6 |
||||
#define SRST_CORE3_PO 7 |
||||
#define SRST_PDCORE_STRSYS 8 |
||||
#define SRST_PDBUS_STRSYS 9 |
||||
#define SRST_L2C 10 |
||||
#define SRST_TOPDBG 11 |
||||
#define SRST_CORE0_DBG 12 |
||||
#define SRST_CORE1_DBG 13 |
||||
#define SRST_CORE2_DBG 14 |
||||
#define SRST_CORE3_DBG 15 |
||||
|
||||
#define SRST_PDBUG_AHB_ARBITOR 16 |
||||
#define SRST_EFUSE256 17 |
||||
#define SRST_DMAC1 18 |
||||
#define SRST_INTMEM 19 |
||||
#define SRST_ROM 20 |
||||
#define SRST_SPDIF8CH 21 |
||||
#define SRST_TIMER 22 |
||||
#define SRST_I2S0 23 |
||||
#define SRST_SPDIF 24 |
||||
#define SRST_TIMER0 25 |
||||
#define SRST_TIMER1 26 |
||||
#define SRST_TIMER2 27 |
||||
#define SRST_TIMER3 28 |
||||
#define SRST_TIMER4 29 |
||||
#define SRST_TIMER5 30 |
||||
#define SRST_EFUSE 31 |
||||
|
||||
#define SRST_GPIO0 32 |
||||
#define SRST_GPIO1 33 |
||||
#define SRST_GPIO2 34 |
||||
#define SRST_GPIO3 35 |
||||
#define SRST_GPIO4 36 |
||||
#define SRST_GPIO5 37 |
||||
#define SRST_GPIO6 38 |
||||
#define SRST_GPIO7 39 |
||||
#define SRST_GPIO8 40 |
||||
#define SRST_I2C0 42 |
||||
#define SRST_I2C1 43 |
||||
#define SRST_I2C2 44 |
||||
#define SRST_I2C3 45 |
||||
#define SRST_I2C4 46 |
||||
#define SRST_I2C5 47 |
||||
|
||||
#define SRST_DWPWM 48 |
||||
#define SRST_MMC_PERI 49 |
||||
#define SRST_PERIPH_MMU 50 |
||||
#define SRST_DAP 51 |
||||
#define SRST_DAP_SYS 52 |
||||
#define SRST_TPIU 53 |
||||
#define SRST_PMU_APB 54 |
||||
#define SRST_GRF 55 |
||||
#define SRST_PMU 56 |
||||
#define SRST_PERIPH_AXI 57 |
||||
#define SRST_PERIPH_AHB 58 |
||||
#define SRST_PERIPH_APB 59 |
||||
#define SRST_PERIPH_NIU 60 |
||||
#define SRST_PDPERI_AHB_ARBI 61 |
||||
#define SRST_EMEM 62 |
||||
#define SRST_USB_PERI 63 |
||||
|
||||
#define SRST_DMAC2 64 |
||||
#define SRST_MAC 66 |
||||
#define SRST_GPS 67 |
||||
#define SRST_RKPWM 69 |
||||
#define SRST_CCP 71 |
||||
#define SRST_USBHOST0 72 |
||||
#define SRST_HSIC 73 |
||||
#define SRST_HSIC_AUX 74 |
||||
#define SRST_HSIC_PHY 75 |
||||
#define SRST_HSADC 76 |
||||
#define SRST_NANDC0 77 |
||||
#define SRST_NANDC1 78 |
||||
|
||||
#define SRST_TZPC 80 |
||||
#define SRST_SPI0 83 |
||||
#define SRST_SPI1 84 |
||||
#define SRST_SPI2 85 |
||||
#define SRST_SARADC 87 |
||||
#define SRST_PDALIVE_NIU 88 |
||||
#define SRST_PDPMU_INTMEM 89 |
||||
#define SRST_PDPMU_NIU 90 |
||||
#define SRST_SGRF 91 |
||||
|
||||
#define SRST_VIO_ARBI 96 |
||||
#define SRST_RGA_NIU 97 |
||||
#define SRST_VIO0_NIU_AXI 98 |
||||
#define SRST_VIO_NIU_AHB 99 |
||||
#define SRST_LCDC0_AXI 100 |
||||
#define SRST_LCDC0_AHB 101 |
||||
#define SRST_LCDC0_DCLK 102 |
||||
#define SRST_VIO1_NIU_AXI 103 |
||||
#define SRST_VIP 104 |
||||
#define SRST_RGA_CORE 105 |
||||
#define SRST_IEP_AXI 106 |
||||
#define SRST_IEP_AHB 107 |
||||
#define SRST_RGA_AXI 108 |
||||
#define SRST_RGA_AHB 109 |
||||
#define SRST_ISP 110 |
||||
#define SRST_EDP 111 |
||||
|
||||
#define SRST_VCODEC_AXI 112 |
||||
#define SRST_VCODEC_AHB 113 |
||||
#define SRST_VIO_H2P 114 |
||||
#define SRST_MIPIDSI0 115 |
||||
#define SRST_MIPIDSI1 116 |
||||
#define SRST_MIPICSI 117 |
||||
#define SRST_LVDS_PHY 118 |
||||
#define SRST_LVDS_CON 119 |
||||
#define SRST_GPU 120 |
||||
#define SRST_HDMI 121 |
||||
#define SRST_CORE_PVTM 124 |
||||
#define SRST_GPU_PVTM 125 |
||||
|
||||
#define SRST_MMC0 128 |
||||
#define SRST_SDIO0 129 |
||||
#define SRST_SDIO1 130 |
||||
#define SRST_EMMC 131 |
||||
#define SRST_USBOTG_AHB 132 |
||||
#define SRST_USBOTG_PHY 133 |
||||
#define SRST_USBOTG_CON 134 |
||||
#define SRST_USBHOST0_AHB 135 |
||||
#define SRST_USBHOST0_PHY 136 |
||||
#define SRST_USBHOST0_CON 137 |
||||
#define SRST_USBHOST1_AHB 138 |
||||
#define SRST_USBHOST1_PHY 139 |
||||
#define SRST_USBHOST1_CON 140 |
||||
#define SRST_USB_ADP 141 |
||||
#define SRST_ACC_EFUSE 142 |
||||
|
||||
#define SRST_CORESIGHT 144 |
||||
#define SRST_PD_CORE_AHB_NOC 145 |
||||
#define SRST_PD_CORE_APB_NOC 146 |
||||
#define SRST_PD_CORE_MP_AXI 147 |
||||
#define SRST_GIC 148 |
||||
#define SRST_LCDC_PWM0 149 |
||||
#define SRST_LCDC_PWM1 150 |
||||
#define SRST_VIO0_H2P_BRG 151 |
||||
#define SRST_VIO1_H2P_BRG 152 |
||||
#define SRST_RGA_H2P_BRG 153 |
||||
#define SRST_HEVC 154 |
||||
#define SRST_TSADC 159 |
||||
|
||||
#define SRST_DDRPHY0 160 |
||||
#define SRST_DDRPHY0_APB 161 |
||||
#define SRST_DDRCTRL0 162 |
||||
#define SRST_DDRCTRL0_APB 163 |
||||
#define SRST_DDRPHY0_CTRL 164 |
||||
#define SRST_DDRPHY1 165 |
||||
#define SRST_DDRPHY1_APB 166 |
||||
#define SRST_DDRCTRL1 167 |
||||
#define SRST_DDRCTRL1_APB 168 |
||||
#define SRST_DDRPHY1_CTRL 169 |
||||
#define SRST_DDRMSCH0 170 |
||||
#define SRST_DDRMSCH1 171 |
||||
#define SRST_CRYPTO 174 |
||||
#define SRST_C2C_HOST 175 |
||||
|
||||
#define SRST_LCDC1_AXI 176 |
||||
#define SRST_LCDC1_AHB 177 |
||||
#define SRST_LCDC1_DCLK 178 |
||||
#define SRST_UART0 179 |
||||
#define SRST_UART1 180 |
||||
#define SRST_UART2 181 |
||||
#define SRST_UART3 182 |
||||
#define SRST_UART4 183 |
||||
#define SRST_SIMC 186 |
||||
#define SRST_PS2C 187 |
||||
#define SRST_TSP 188 |
||||
#define SRST_TSP_CLKIN0 189 |
||||
#define SRST_TSP_CLKIN1 190 |
||||
#define SRST_TSP_27M 191 |
||||
@ -0,0 +1,11 @@ |
||||
/*
|
||||
* This header provides constants clk index RK808 pmic clkout |
||||
*/ |
||||
#ifndef _CLK_ROCKCHIP_RK808 |
||||
#define _CLK_ROCKCHIP_RK808 |
||||
|
||||
/* CLOCKOUT index */ |
||||
#define RK808_CLKOUT0 0 |
||||
#define RK808_CLKOUT1 1 |
||||
|
||||
#endif |
||||
@ -0,0 +1,26 @@ |
||||
/*
|
||||
* Header providing constants for Rockchip pinctrl bindings. |
||||
* |
||||
* Copyright (c) 2013 MundoReader S.L. |
||||
* Author: Heiko Stuebner <heiko@sntech.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ |
||||
#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ |
||||
|
||||
#define RK_GPIO0 0 |
||||
#define RK_GPIO1 1 |
||||
#define RK_GPIO2 2 |
||||
#define RK_GPIO3 3 |
||||
#define RK_GPIO4 4 |
||||
#define RK_GPIO6 6 |
||||
|
||||
#define RK_FUNC_GPIO 0 |
||||
#define RK_FUNC_1 1 |
||||
#define RK_FUNC_2 2 |
||||
#define RK_FUNC_3 3 |
||||
#define RK_FUNC_4 4 |
||||
|
||||
#endif |
||||
@ -0,0 +1,11 @@ |
||||
#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ |
||||
#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ |
||||
|
||||
/* RK3288 power domain index */ |
||||
#define RK3288_PD_GPU 0 |
||||
#define RK3288_PD_VIO 1 |
||||
#define RK3288_PD_VIDEO 2 |
||||
#define RK3288_PD_HEVC 3 |
||||
#define RK3288_PD_PERI 4 |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue