Add support for board eth initialization and support for loading phy firmware. PHY firmware needs to be loaded from board_eth_init() because all the MACs are not initialized by ldpaa_eth driver. Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>master
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/*
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* Copyright 2015 Freescale Semiconductor, Inc. |
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* |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <netdev.h> |
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#include <malloc.h> |
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#include <fsl_mdio.h> |
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#include <miiphy.h> |
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#include <phy.h> |
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#include <fm_eth.h> |
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#include <asm/io.h> |
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#include <asm/arch/fsl_serdes.h> |
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#include <asm/arch-fsl-lsch3/immap_lsch3.h> |
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#include <fsl-mc/ldpaa_wriop.h> |
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int load_firmware_cortina(struct phy_device *phy_dev) |
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{ |
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if (phy_dev->drv->config) |
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return phy_dev->drv->config(phy_dev); |
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return 0; |
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} |
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void load_phy_firmware(void) |
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{ |
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int i; |
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u8 phy_addr; |
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struct phy_device *phy_dev; |
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struct mii_dev *dev; |
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phy_interface_t interface; |
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/*Initialize and upload firmware for all the PHYs*/ |
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for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) { |
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interface = wriop_get_enet_if(i); |
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if (interface == PHY_INTERFACE_MODE_XGMII) { |
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dev = wriop_get_mdio(i); |
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phy_addr = wriop_get_phy_address(i); |
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phy_dev = phy_find_by_mask(dev, 1 << phy_addr, |
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interface); |
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if (!phy_dev) { |
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printf("No phydev for phyaddr %d\n", phy_addr); |
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continue; |
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} |
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/*Flash firmware for All CS4340 PHYS */ |
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if (phy_dev->phy_id == PHY_UID_CS4340) |
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load_firmware_cortina(phy_dev); |
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} |
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} |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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#if defined(CONFIG_FSL_MC_ENET) |
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int i, interface; |
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struct memac_mdio_info mdio_info; |
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struct mii_dev *dev; |
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); |
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u32 srds_s1; |
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struct memac_mdio_controller *reg; |
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srds_s1 = in_le32(&gur->rcwsr[28]) & |
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FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; |
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srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; |
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; |
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mdio_info.regs = reg; |
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mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; |
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/* Register the EMI 1 */ |
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fm_memac_mdio_init(bis, &mdio_info); |
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reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; |
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mdio_info.regs = reg; |
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mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; |
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/* Register the EMI 2 */ |
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fm_memac_mdio_init(bis, &mdio_info); |
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switch (srds_s1) { |
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case 0x2A: |
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wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); |
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wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); |
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wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); |
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wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); |
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wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); |
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wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); |
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wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); |
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wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); |
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break; |
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default: |
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printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n", |
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srds_s1); |
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break; |
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} |
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for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) { |
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interface = wriop_get_enet_if(i); |
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switch (interface) { |
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case PHY_INTERFACE_MODE_XGMII: |
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); |
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wriop_set_mdio(i, dev); |
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break; |
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default: |
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break; |
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} |
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} |
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for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) { |
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switch (wriop_get_enet_if(i)) { |
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case PHY_INTERFACE_MODE_XGMII: |
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dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); |
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wriop_set_mdio(i, dev); |
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break; |
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default: |
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break; |
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} |
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} |
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/* Load CORTINA CS4340 PHY firmware */ |
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load_phy_firmware(); |
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cpu_eth_init(bis); |
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#endif /* CONFIG_FMAN_ENET */ |
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return pci_eth_init(bis); |
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} |
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