ZynqMP Emulation board is no longer tested and there is no reason to keep maintaining it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>master
Michal Simek
6 years ago
parent
83bf2ff03d
commit
348dbf4368
@ -1,172 +0,0 @@ |
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/* |
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* clock specification for Xilinx ZynqMP ep108 development board |
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* |
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* (C) Copyright 2015, Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/ { |
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misc_clk: misc_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <25000000>; |
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u-boot,dm-pre-reloc; |
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}; |
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i2c_clk: i2c_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0x0>; |
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clock-frequency = <111111111>; |
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}; |
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sata_clk: sata_clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <75000000>; |
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}; |
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dp_aclk: clock0 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <50000000>; |
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clock-accuracy = <100>; |
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}; |
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clk100: clk100 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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}; |
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clk600: clk600 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <600000000>; |
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}; |
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dp_aud_clk: clock1 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <22579200>; |
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clock-accuracy = <100>; |
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}; |
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}; |
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|
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&can0 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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&can1 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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&fpd_dma_chan1 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan2 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan3 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan4 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan5 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan6 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan7 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&fpd_dma_chan8 { |
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clocks = <&clk600>, <&clk100>; |
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}; |
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&gem0 { |
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clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; |
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}; |
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&gpio { |
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clocks = <&misc_clk>; |
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}; |
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&i2c0 { |
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clocks = <&i2c_clk>; |
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}; |
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&i2c1 { |
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clocks = <&i2c_clk>; |
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}; |
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&nand0 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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&qspi { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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&sata { |
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clocks = <&sata_clk>; |
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}; |
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&sdhci0 { |
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clocks = <&misc_clk>, <&misc_clk>; |
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}; |
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&sdhci1 { |
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clocks = <&misc_clk>, <&misc_clk>; |
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}; |
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&spi0 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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&spi1 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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&uart0 { |
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clocks = <&misc_clk &misc_clk>; |
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}; |
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&usb0 { |
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clocks = <&misc_clk>, <&misc_clk>; |
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}; |
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&usb1 { |
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clocks = <&misc_clk>, <&misc_clk>; |
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}; |
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&watchdog0 { |
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clocks= <&misc_clk>; |
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}; |
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&xilinx_drm { |
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clocks = <&misc_clk>; |
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}; |
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&xlnx_dp { |
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clocks = <&dp_aclk>, <&dp_aud_clk>; |
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}; |
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&xlnx_dp_snd_codec0 { |
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clocks = <&dp_aud_clk>; |
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}; |
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&xlnx_dpdma { |
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clocks = <&misc_clk>; |
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}; |
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@ -1,235 +0,0 @@ |
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/* |
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* dts file for Xilinx ZynqMP ep108 development board |
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* |
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* (C) Copyright 2014 - 2015, Xilinx, Inc. |
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* |
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* Michal Simek <michal.simek@xilinx.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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#include "zynqmp.dtsi" |
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#include "zynqmp-ep108-clk.dtsi" |
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/ { |
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model = "ZynqMP EP108"; |
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aliases { |
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ethernet0 = &gem0; |
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mmc0 = &sdhci0; |
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mmc1 = &sdhci1; |
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serial0 = &uart0; |
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spi0 = &qspi; |
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spi1 = &spi0; |
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spi2 = &spi1; |
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usb0 = &usb0; |
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usb1 = &usb1; |
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}; |
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chosen { |
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bootargs = "earlycon"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x40000000>; |
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}; |
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}; |
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&can0 { |
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status = "okay"; |
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}; |
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&can1 { |
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status = "okay"; |
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}; |
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&gem0 { |
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status = "okay"; |
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phy-handle = <&phy0>; |
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phy-mode = "rgmii-id"; |
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phy0: phy@0 { |
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reg = <0>; |
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max-speed = <100>; |
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}; |
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}; |
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&gpio { |
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status = "okay"; |
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}; |
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&i2c0 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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eeprom@54 { |
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compatible = "atmel,24c64"; |
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reg = <0x54>; |
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}; |
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}; |
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&i2c1 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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eeprom@55 { |
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compatible = "atmel,24c64"; |
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reg = <0x55>; |
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}; |
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}; |
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&nand0 { |
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status = "okay"; |
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arasan,has-mdma; |
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num-cs = <1>; |
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partition@0 { /* for testing purpose */ |
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label = "nand-fsbl-uboot"; |
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reg = <0x0 0x0 0x400000>; |
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}; |
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partition@1 { /* for testing purpose */ |
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label = "nand-linux"; |
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reg = <0x0 0x400000 0x1400000>; |
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}; |
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partition@2 { /* for testing purpose */ |
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label = "nand-device-tree"; |
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reg = <0x0 0x1800000 0x400000>; |
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}; |
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partition@3 { /* for testing purpose */ |
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label = "nand-rootfs"; |
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reg = <0x0 0x1C00000 0x1400000>; |
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}; |
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partition@4 { /* for testing purpose */ |
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label = "nand-bitstream"; |
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reg = <0x0 0x3000000 0x400000>; |
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}; |
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partition@5 { /* for testing purpose */ |
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label = "nand-misc"; |
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reg = <0x0 0x3400000 0xFCC00000>; |
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}; |
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}; |
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&qspi { |
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status = "okay"; |
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flash@0 { |
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compatible = "m25p80"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x0>; |
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spi-tx-bus-width = <1>; |
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spi-rx-bus-width = <4>; |
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spi-max-frequency = <10000000>; |
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partition@qspi-fsbl-uboot { /* for testing purpose */ |
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label = "qspi-fsbl-uboot"; |
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reg = <0x0 0x100000>; |
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}; |
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partition@qspi-linux { /* for testing purpose */ |
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label = "qspi-linux"; |
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reg = <0x100000 0x500000>; |
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}; |
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partition@qspi-device-tree { /* for testing purpose */ |
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label = "qspi-device-tree"; |
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reg = <0x600000 0x20000>; |
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}; |
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partition@qspi-rootfs { /* for testing purpose */ |
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label = "qspi-rootfs"; |
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reg = <0x620000 0x5E0000>; |
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}; |
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}; |
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}; |
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&sata { |
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status = "okay"; |
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ceva,broken-gen2; |
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/* SATA Phy OOB timing settings */ |
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ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; |
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ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; |
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ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; |
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ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; |
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ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; |
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ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; |
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ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; |
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ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; |
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}; |
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&sdhci0 { |
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status = "okay"; |
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bus-width = <8>; |
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xlnx,mio_bank = <2>; |
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}; |
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&sdhci1 { |
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status = "okay"; |
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xlnx,mio_bank = <1>; |
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}; |
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&spi0 { |
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status = "okay"; |
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num-cs = <1>; |
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spi0_flash0: spi0_flash0@0 { |
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compatible = "m25p80"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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spi-max-frequency = <50000000>; |
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reg = <0>; |
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spi0_flash0@0 { |
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label = "spi0_flash0"; |
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reg = <0x0 0x100000>; |
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}; |
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}; |
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}; |
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&spi1 { |
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status = "okay"; |
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num-cs = <1>; |
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spi1_flash0: spi1_flash0@0 { |
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compatible = "m25p80"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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spi-max-frequency = <50000000>; |
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reg = <0>; |
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spi1_flash0@0 { |
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label = "spi1_flash0"; |
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reg = <0x0 0x100000>; |
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}; |
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}; |
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}; |
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&uart0 { |
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status = "okay"; |
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}; |
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&usb0 { |
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status = "okay"; |
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}; |
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&dwc3_0 { |
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status = "okay"; |
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dr_mode = "peripheral"; |
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maximum-speed = "high-speed"; |
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}; |
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&usb1 { |
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status = "okay"; |
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}; |
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&dwc3_1 { |
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status = "okay"; |
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dr_mode = "host"; |
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maximum-speed = "high-speed"; |
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}; |
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&watchdog0 { |
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status = "okay"; |
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}; |
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&xlnx_dp { |
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xlnx,max-pclock-frequency = <200000>; |
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}; |
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&xlnx_dpdma { |
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xlnx,axi-clock-freq = <200000000>; |
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}; |
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@ -1,102 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep" |
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CONFIG_ARCH_ZYNQMP=y |
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CONFIG_SYS_TEXT_BASE=0x8000000 |
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CONFIG_SYS_MALLOC_F_LEN=0x8000 |
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CONFIG_SPL=y |
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CONFIG_ZYNQ_SDHCI_MAX_FREQ=52000000 |
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CONFIG_ZYNQMP_USB=y |
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CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" |
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CONFIG_DEBUG_UART=y |
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CONFIG_AHCI=y |
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CONFIG_DISTRO_DEFAULTS=y |
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CONFIG_FIT=y |
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CONFIG_FIT_VERBOSE=y |
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CONFIG_SPL_LOAD_FIT=y |
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# CONFIG_DISPLAY_CPUINFO is not set |
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# CONFIG_DISPLAY_BOARDINFO is not set |
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CONFIG_SPL_OS_BOOT=y |
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CONFIG_SYS_PROMPT="ZynqMP> " |
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CONFIG_FASTBOOT=y |
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CONFIG_FASTBOOT_FLASH=y |
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CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
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# CONFIG_CMD_CONSOLE is not set |
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# CONFIG_CMD_XIMG is not set |
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CONFIG_CMD_THOR_DOWNLOAD=y |
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# CONFIG_CMD_EDITENV is not set |
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# CONFIG_CMD_ENV_EXISTS is not set |
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CONFIG_CMD_CLK=y |
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CONFIG_CMD_DFU=y |
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# CONFIG_CMD_FPGA is not set |
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CONFIG_CMD_GPIO=y |
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CONFIG_CMD_GPT=y |
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CONFIG_CMD_I2C=y |
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# CONFIG_CMD_LOADB is not set |
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# CONFIG_CMD_LOADS is not set |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_NAND_LOCK_UNLOCK=y |
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CONFIG_CMD_USB=y |
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# CONFIG_CMD_ITEST is not set |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_CMD_TFTPPUT=y |
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# CONFIG_CMD_NFS is not set |
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CONFIG_CMD_TIME=y |
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CONFIG_CMD_TIMER=y |
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CONFIG_CMD_EXT4_WRITE=y |
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# CONFIG_SPL_ISO_PARTITION is not set |
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CONFIG_SPL_OF_CONTROL=y |
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CONFIG_OF_EMBED=y |
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CONFIG_ENV_IS_IN_FAT=y |
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CONFIG_NET_RANDOM_ETHADDR=y |
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CONFIG_SPL_DM=y |
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CONFIG_SPL_DM_SEQ_ALIAS=y |
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CONFIG_SCSI_AHCI=y |
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CONFIG_SATA_CEVA=y |
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CONFIG_DFU_RAM=y |
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CONFIG_FPGA_XILINX=y |
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CONFIG_FPGA_ZYNQMPPL=y |
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CONFIG_DM_GPIO=y |
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CONFIG_DM_I2C=y |
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CONFIG_SYS_I2C_CADENCE=y |
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CONFIG_MISC=y |
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CONFIG_DM_MMC=y |
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CONFIG_MMC_SDHCI=y |
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CONFIG_MMC_SDHCI_ZYNQ=y |
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CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 |
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CONFIG_NAND=y |
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CONFIG_NAND_ARASAN=y |
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CONFIG_SPI_FLASH=y |
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CONFIG_SPI_FLASH_BAR=y |
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CONFIG_SPI_FLASH_SPANSION=y |
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CONFIG_SPI_FLASH_STMICRO=y |
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CONFIG_SPI_FLASH_WINBOND=y |
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
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CONFIG_PHY_MARVELL=y |
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CONFIG_PHY_NATSEMI=y |
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CONFIG_PHY_REALTEK=y |
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CONFIG_PHY_TI=y |
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CONFIG_PHY_VITESSE=y |
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CONFIG_DM_ETH=y |
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CONFIG_PHY_GIGE=y |
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CONFIG_ZYNQ_GEM=y |
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CONFIG_SCSI=y |
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CONFIG_DM_SCSI=y |
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CONFIG_DEBUG_UART_ZYNQ=y |
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CONFIG_DEBUG_UART_BASE=0xff000000 |
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CONFIG_DEBUG_UART_CLOCK=25000000 |
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CONFIG_DEBUG_UART_ANNOUNCE=y |
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CONFIG_ZYNQ_SERIAL=y |
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CONFIG_USB=y |
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CONFIG_USB_XHCI_HCD=y |
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CONFIG_USB_XHCI_DWC3=y |
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CONFIG_USB_XHCI_ZYNQMP=y |
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CONFIG_USB_DWC3=y |
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CONFIG_USB_DWC3_GADGET=y |
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CONFIG_USB_STORAGE=y |
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CONFIG_USB_GADGET=y |
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CONFIG_USB_GADGET_MANUFACTURER="Xilinx" |
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CONFIG_USB_GADGET_VENDOR_NUM=0x03fd |
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CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 |
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CONFIG_USB_FUNCTION_THOR=y |
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# CONFIG_REGEX is not set |
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y |
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@ -1,24 +0,0 @@ |
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/*
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* Configuration for Xilinx ZynqMP emulation platforms |
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* |
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* (C) Copyright 2014 - 2015 Xilinx, Inc. |
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* Michal Simek <michal.simek@xilinx.com> |
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* Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
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* |
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* Based on Configuration for Versatile Express |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_ZYNQMP_EP_H |
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#define __CONFIG_ZYNQMP_EP_H |
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#define CONFIG_ZYNQ_EEPROM |
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#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ |
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ZYNQMP_USB1_XHCI_BASEADDR} |
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#define COUNTER_FREQUENCY 4000000 |
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#include <configs/xilinx_zynqmp.h> |
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#endif /* __CONFIG_ZYNQMP_EP_H */ |
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