commit
34d51566bc
@ -0,0 +1,414 @@ |
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/*
|
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* (C) Copyright 2007 |
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* DENX Software Engineering, Anatolij Gustschin, agust@denx.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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/*
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* mb862xx.c - Graphic interface for Fujitsu CoralP/Lime |
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* PCI and video mode code was derived from smiLynxEM driver. |
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*/ |
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#include <common.h> |
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#if defined(CONFIG_VIDEO_MB862xx) |
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#include <asm/io.h> |
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#include <pci.h> |
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#include <video_fb.h> |
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#include "videomodes.h" |
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#include <mb862xx.h> |
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|
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/*
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* Graphic Device |
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*/ |
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GraphicDevice mb862xx; |
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|
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/*
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* 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ; |
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*/ |
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#define VIDEO_MEM_SIZE 0x01FC0000 |
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|
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#if defined(CONFIG_PCI) |
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#if defined(CONFIG_VIDEO_CORALP) |
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|
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static struct pci_device_id supported[] = { |
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{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P }, |
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{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA }, |
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{ } |
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}; |
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|
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/* Internal clock frequency divider table, index is mode number */ |
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unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; |
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#endif |
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#endif |
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|
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#if defined(CONFIG_VIDEO_CORALP) |
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#define rd_io in32r |
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#define wr_io out32r |
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#else |
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#define rd_io(addr) in_be32((volatile unsigned*)(addr)) |
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#define wr_io(addr,val) out_be32((volatile unsigned*)(addr), (val)) |
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#endif |
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#define HOST_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fc0000 + (off))) |
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#define HOST_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fc0000 + (off)), (val)) |
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#define DISP_RD_REG(off) rd_io((pGD->frameAdrs + 0x01fd0000 + (off))) |
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#define DISP_WR_REG(off, val) wr_io((pGD->frameAdrs + 0x01fd0000 + (off)), (val)) |
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#define DE_RD_REG(off) rd_io((pGD->dprBase + (off))) |
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#define DE_WR_REG(off, val) wr_io((pGD->dprBase + (off)), (val)) |
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#if defined(CONFIG_VIDEO_CORALP) |
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#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x8400)), (val)) |
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#else |
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#define DE_WR_FIFO(val) wr_io((pGD->dprBase + (0x04a0)), (val)) |
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#endif |
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|
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#define L0PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2))) |
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#define L0PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0400 + ((idx)<<2)), (val)) |
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#define L1PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2))) |
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#define L1PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd0800 + ((idx)<<2)), (val)) |
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#define L2PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2))) |
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#define L2PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1000 + ((idx)<<2)), (val)) |
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#define L3PAL_RD_REG(idx, val) rd_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2))) |
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#define L3PAL_WR_REG(idx, val) wr_io((pGD->frameAdrs + 0x01fd1400 + ((idx)<<2)), (val)) |
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static void gdc_sw_reset(void) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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HOST_WR_REG (0x002c, 0x00000001); |
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udelay (500); |
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video_hw_init (); |
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} |
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static void de_wait(void) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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int lc = 0x10000; |
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/* Sync with software writes to framebuffer,
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try to reset if engine locked */ |
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while (DE_RD_REG (0x0400) & 0x00000131) |
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if (lc-- < 0) { |
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gdc_sw_reset (); |
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printf ("gdc reset done after drawing engine lock...\n"); |
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break; |
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} |
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} |
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static void de_wait_slots(int slots) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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int lc = 0x10000; |
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|
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/* Wait for free fifo slots */ |
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while (DE_RD_REG (0x0408) < slots) |
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if (lc-- < 0) { |
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gdc_sw_reset (); |
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printf ("gdc reset done after drawing engine lock...\n"); |
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break; |
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} |
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} |
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#if !defined(CONFIG_VIDEO_CORALP) |
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static void board_disp_init(void) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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const gdc_regs *regs = board_get_regs (); |
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while (regs->index) { |
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DISP_WR_REG (regs->index, regs->value); |
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regs++; |
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} |
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} |
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#endif |
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/*
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* Init drawing engine |
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*/ |
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static void de_init (void) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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int cf = (pGD->gdfBytesPP == 1) ? 0x0000 : 0x8000; |
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pGD->dprBase = pGD->frameAdrs + 0x01ff0000; |
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/* Setup mode and fbbase, xres, fg, bg */ |
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de_wait_slots (2); |
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DE_WR_FIFO (0xf1010108); |
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DE_WR_FIFO (cf | 0x0300); |
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DE_WR_REG (0x0440, 0x0000); |
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DE_WR_REG (0x0444, pGD->winSizeX); |
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DE_WR_REG (0x0480, 0x0000); |
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DE_WR_REG (0x0484, 0x0000); |
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/* Reset clipping */ |
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DE_WR_REG (0x0454, 0x0000); |
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DE_WR_REG (0x0458, pGD->winSizeX); |
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DE_WR_REG (0x045c, 0x0000); |
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DE_WR_REG (0x0460, pGD->winSizeY); |
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|
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/* Clear framebuffer using drawing engine */ |
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de_wait_slots (3); |
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DE_WR_FIFO (0x09410000); |
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DE_WR_FIFO (0x00000000); |
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DE_WR_FIFO (pGD->winSizeY<<16 | pGD->winSizeX); |
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} |
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#if defined(CONFIG_VIDEO_CORALP) |
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unsigned int pci_video_init(void) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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pci_dev_t devbusfn; |
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if ((devbusfn = pci_find_devices(supported, 0)) < 0) |
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{ |
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printf ("PCI video controller not found!\n"); |
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return 0; |
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} |
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/* PCI setup */ |
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pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
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pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs); |
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pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs); |
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if (pGD->frameAdrs == 0) { |
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printf ("PCI config: failed to get base address\n"); |
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return 0; |
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} |
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pGD->pciBase = pGD->frameAdrs; |
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/* Setup clocks and memory mode for Coral-P Eval. Board */ |
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HOST_WR_REG (0x0038, 0x00090000); |
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udelay (200); |
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HOST_WR_REG (0xfffc, 0x11d7fa13); |
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udelay (100); |
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return pGD->frameAdrs; |
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} |
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unsigned int card_init (void) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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unsigned int cf, videomode, div = 0; |
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unsigned long t1, hsync, vsync; |
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char *penv; |
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int tmp, i, bpp; |
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struct ctfb_res_modes *res_mode; |
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struct ctfb_res_modes var_mode; |
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memset (pGD, 0, sizeof (GraphicDevice)); |
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if (!pci_video_init ()) { |
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return 0; |
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} |
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printf ("CoralP\n"); |
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tmp = 0; |
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videomode = 0x310; |
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/* get video mode via environment */ |
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if ((penv = getenv ("videomode")) != NULL) { |
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/* deceide if it is a string */ |
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if (penv[0] <= '9') { |
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videomode = (int) simple_strtoul (penv, NULL, 16); |
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tmp = 1; |
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} |
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} else { |
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tmp = 1; |
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} |
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if (tmp) { |
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/* parameter are vesa modes */ |
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/* search params */ |
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for (i = 0; i < VESA_MODES_COUNT; i++) { |
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if (vesa_modes[i].vesanr == videomode) |
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break; |
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} |
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if (i == VESA_MODES_COUNT) { |
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printf ("\tno VESA Mode found, switching to mode 0x%x \n", videomode); |
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i = 0; |
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} |
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res_mode = |
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(struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; |
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if (vesa_modes[i].resindex > 2) { |
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printf ("\tUnsupported resolution, switching to default\n"); |
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bpp = vesa_modes[1].bits_per_pixel; |
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div = fr_div[1]; |
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} |
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bpp = vesa_modes[i].bits_per_pixel; |
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div = fr_div[vesa_modes[i].resindex]; |
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} else { |
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res_mode = (struct ctfb_res_modes *) &var_mode; |
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bpp = video_get_params (res_mode, penv); |
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} |
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/* calculate hsync and vsync freq (info only) */ |
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t1 = (res_mode->left_margin + res_mode->xres + |
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res_mode->right_margin + res_mode->hsync_len) / 8; |
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t1 *= 8; |
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t1 *= res_mode->pixclock; |
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t1 /= 1000; |
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hsync = 1000000000L / t1; |
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t1 *= (res_mode->upper_margin + res_mode->yres + |
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res_mode->lower_margin + res_mode->vsync_len); |
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t1 /= 1000; |
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vsync = 1000000000L / t1; |
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|
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/* fill in Graphic device struct */ |
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sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, |
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res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); |
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printf ("\t%s\n", pGD->modeIdent); |
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pGD->winSizeX = res_mode->xres; |
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pGD->winSizeY = res_mode->yres; |
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pGD->memSize = VIDEO_MEM_SIZE; |
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switch (bpp) { |
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case 8: |
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pGD->gdfIndex = GDF__8BIT_INDEX; |
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pGD->gdfBytesPP = 1; |
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break; |
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case 15: |
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case 16: |
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pGD->gdfIndex = GDF_15BIT_555RGB; |
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pGD->gdfBytesPP = 2; |
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break; |
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default: |
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printf ("\t%d bpp configured, but only 8,15 and 16 supported.\n", bpp); |
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printf ("\tSwitching back to 15bpp\n"); |
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pGD->gdfIndex = GDF_15BIT_555RGB; |
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pGD->gdfBytesPP = 2; |
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} |
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|
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/* Setup dot clock (internal pll, division rate) */ |
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DISP_WR_REG (0x0100, div); |
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/* L0 init */ |
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cf = (pGD->gdfBytesPP == 1) ? 0x00000000 : 0x80000000; |
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DISP_WR_REG (0x0020, ((pGD->winSizeX * pGD->gdfBytesPP)/64)<<16 | |
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(pGD->winSizeY-1) | |
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cf); |
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DISP_WR_REG (0x0024, 0x00000000); |
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DISP_WR_REG (0x0028, 0x00000000); |
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DISP_WR_REG (0x002c, 0x00000000); |
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DISP_WR_REG (0x0110, 0x00000000); |
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DISP_WR_REG (0x0114, 0x00000000); |
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DISP_WR_REG (0x0118, (pGD->winSizeY-1)<<16 | pGD->winSizeX); |
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|
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/* Display timing init */ |
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DISP_WR_REG (0x0004, (pGD->winSizeX+res_mode->left_margin+res_mode->right_margin+res_mode->hsync_len-1)<<16); |
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DISP_WR_REG (0x0008, (pGD->winSizeX-1) << 16 | (pGD->winSizeX-1)); |
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DISP_WR_REG (0x000c, (res_mode->vsync_len-1)<<24|(res_mode->hsync_len-1)<<16|(pGD->winSizeX+res_mode->right_margin-1)); |
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DISP_WR_REG (0x0010, (pGD->winSizeY+res_mode->lower_margin+res_mode->upper_margin+res_mode->vsync_len-1)<<16); |
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DISP_WR_REG (0x0014, (pGD->winSizeY-1) << 16 | (pGD->winSizeY+res_mode->lower_margin-1)); |
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DISP_WR_REG (0x0018, 0x00000000); |
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DISP_WR_REG (0x001c, pGD->winSizeY << 16 | pGD->winSizeX); |
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/* Display enable, L0 layer */ |
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DISP_WR_REG (0x0100, 0x80010000 | div); |
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|
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return pGD->frameAdrs; |
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} |
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#endif |
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|
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void *video_hw_init (void) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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|
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printf ("Video: Fujitsu "); |
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|
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memset (pGD, 0, sizeof (GraphicDevice)); |
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|
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#if defined(CONFIG_VIDEO_CORALP) |
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if (card_init () == 0) { |
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return (NULL); |
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} |
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#else |
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/* Preliminary init of the onboard graphic controller,
|
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retrieve base address */ |
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if ((pGD->frameAdrs = board_video_init ()) == 0) { |
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printf ("Controller not found!\n"); |
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return (NULL); |
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} else |
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printf("Lime\n"); |
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#endif |
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|
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de_init (); |
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|
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#if !defined(CONFIG_VIDEO_CORALP) |
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board_disp_init(); |
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#endif |
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|
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#if defined(CONFIG_LWMON5) |
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/* Lamp on */ |
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board_backlight_switch (1); |
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#endif |
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|
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return pGD; |
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} |
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|
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/*
|
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* Set a RGB color in the LUT |
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*/ |
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void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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|
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L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); |
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} |
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|
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/*
|
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* Drawing engine Fill and BitBlt screen region |
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*/ |
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void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, unsigned int dst_y, |
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unsigned int dim_x, unsigned int dim_y, unsigned int color) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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|
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de_wait_slots (3); |
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DE_WR_REG (0x0480, color); |
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DE_WR_FIFO (0x09410000); |
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DE_WR_FIFO ((dst_y << 16) | dst_x); |
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DE_WR_FIFO ((dim_y << 16) | dim_x); |
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de_wait (); |
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} |
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|
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void video_hw_bitblt (unsigned int bpp, unsigned int src_x, unsigned int src_y, |
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unsigned int dst_x, unsigned int dst_y, unsigned int width, |
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unsigned int height) |
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{ |
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GraphicDevice *pGD = (GraphicDevice *)&mb862xx; |
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unsigned int ctrl = 0x0d000000L; |
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|
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if (src_x >= dst_x && src_y >= dst_y) |
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ctrl |= 0x00440000L; |
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else if (src_x >= dst_x && src_y <= dst_y) |
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ctrl |= 0x00460000L; |
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else if (src_x <= dst_x && src_y >= dst_y) |
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ctrl |= 0x00450000L; |
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else |
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ctrl |= 0x00470000L; |
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|
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de_wait_slots (4); |
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DE_WR_FIFO (ctrl); |
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DE_WR_FIFO ((src_y << 16) | src_x); |
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DE_WR_FIFO ((dst_y << 16) | dst_x); |
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DE_WR_FIFO ((height << 16) | width); |
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de_wait (); /* sync */ |
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} |
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#endif /* CONFIG_VIDEO_MB862xx */ |
@ -0,0 +1,44 @@ |
||||
/*
|
||||
* (C) Copyright 2007 |
||||
* DENX Software Engineering, Anatolij Gustschin, agust@denx.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* mb862xx.h - Graphic interface for Fujitsu CoralP/Lime |
||||
*/ |
||||
|
||||
#ifndef _MB862XX_H_ |
||||
#define _MB862XX_H_ |
||||
|
||||
#define PCI_VENDOR_ID_FUJITSU 0x10CF |
||||
#define PCI_DEVICE_ID_CORAL_P 0x2019 |
||||
#define PCI_DEVICE_ID_CORAL_PA 0x201E |
||||
|
||||
typedef struct { |
||||
unsigned int index; |
||||
unsigned int value; |
||||
} gdc_regs; |
||||
|
||||
const gdc_regs *board_get_regs (void); |
||||
unsigned int board_video_init (void); |
||||
void board_backlight_switch(int); |
||||
|
||||
#endif /* _MB862XX_H_ */ |
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