davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK

these variables are curently defined in several config files but the
driver doesn't use them and defaults to hardcoded values in
nand_defs.h

It's interesting to be able to change this hardcoded valude when the
hardware is not using the default adress signals to drive ALE and CLE
and two configuration defines already exist for this purpose so use
them.

Signed-off-by: Eric Bénard <eric@eukrea.com>
master
Eric Benard 12 years ago committed by Tom Rini
parent 81ac7e51cc
commit 34fa07063a
  1. 9
      arch/arm/include/asm/arch-davinci/nand_defs.h
  2. 4
      include/configs/da830evm.h
  3. 4
      include/configs/da850evm.h
  4. 4
      include/configs/enbw_cmc.h
  5. 4
      include/configs/tnetv107x_evm.h

@ -36,6 +36,15 @@
#define MASK_ALE 0x08
#endif
#ifdef CONFIG_SYS_NAND_MASK_CLE
#undef MASK_CLE
#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
#endif
#ifdef CONFIG_SYS_NAND_MASK_ALE
#undef MASK_ALE
#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
#endif
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70

@ -109,8 +109,8 @@
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_CLE_MASK 0x10
#define CONFIG_SYS_ALE_MASK 0x8
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#endif

@ -199,8 +199,8 @@
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_CLE_MASK 0x10
#define CONFIG_SYS_ALE_MASK 0x8
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST

@ -118,8 +118,8 @@
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS 3
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_CLE_MASK 0x10
#define CONFIG_SYS_ALE_MASK 0x8
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */

@ -82,8 +82,8 @@
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
#define CONFIG_SYS_CLE_MASK 0x10
#define CONFIG_SYS_ALE_MASK 0x8
#define CONFIG_SYS_NAND_MASK_CLE 0x10
#define CONFIG_SYS_NAND_MASK_ALE 0x8
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS

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