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@ -2,6 +2,24 @@ |
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Changes since U-Boot 1.1.4: |
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====================================================================== |
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* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) |
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405 SDRAM: - The SDRAM parameters can now be defined in the board |
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config file and the 405 SDRAM controller values will |
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be calculated upon bootup (see PPChameleonEVB). |
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When those settings are not defined in the board |
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config file, the register setup will be as it is now, |
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so this implementation should not break any current |
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design using this code. |
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Thanks to Andrea Marson from DAVE for this patch. |
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440 DDR: - Added function sdram_tr1_set to auto calculate the |
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TR1 value for the DDR. |
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- Added ECC support (see p3p440). |
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Patch by Stefan Roese, 17 Mar 2006 |
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* Enable Quad UART om MCC200 board. |
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* Cleanup MCC200 board configuration; omit non-existent stuff. |
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@ -33,24 +51,6 @@ Changes since U-Boot 1.1.4: |
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* Add support for Lite5200B board. |
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Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006 |
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* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) |
|
|
|
|
|
|
|
|
|
405 SDRAM: - The SDRAM parameters can now be defined in the board |
|
|
|
|
config file and the 405 SDRAM controller values will |
|
|
|
|
be calculated upon bootup (see PPChameleonEVB). |
|
|
|
|
When those settings are not defined in the board |
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|
|
|
config file, the register setup will be as it is now, |
|
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|
|
so this implementation should not break any current |
|
|
|
|
design using this code. |
|
|
|
|
|
|
|
|
|
Thanks to Andrea Marson from DAVE for this patch. |
|
|
|
|
|
|
|
|
|
440 DDR: - Added function sdram_tr1_set to auto calculate the |
|
|
|
|
TR1 value for the DDR. |
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|
- Added ECC support (see p3p440). |
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Patch by Stefan Roese, 17 Mar 2006 |
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* Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific |
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timer and cpu_reset code from cpu/$(CPU) into the new |
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cpu/$(CPU)/$(SOC) directories |
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