Dan Malek
18 years ago
committed by
Wolfgang Denk
parent
14da5f7675
commit
35171dc04e
@ -0,0 +1,48 @@ |
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := $(BOARD).o
|
||||
SOBJS := init.o
|
||||
#SOBJS :=
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean: |
||||
rm -f $(OBJS) $(SOBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,34 @@ |
||||
# Modified by Xianghua Xiao, X.Xiao@motorola.com
|
||||
# (C) Copyright 2002,2003 Motorola Inc.
|
||||
#
|
||||
# Copied from ADS85xx for STx GP3 - Dan Malek
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# default CCARBAR is at 0xff700000
|
||||
# assume U-Boot is less than 0.5MB
|
||||
# U-Boot is less than 256K, so push
|
||||
# it further up into the flash
|
||||
#
|
||||
TEXT_BASE = 0xfffC0000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
|
||||
@ -0,0 +1,256 @@ |
||||
/* |
||||
* Copyright (C) 2005 Embedded Alley Solutions, Inc. |
||||
* Dan Malek <dan@embeddedalley.com>
|
||||
* Copied from STx GP3. |
||||
* Updates for Silicon Tx GP3 SSA. We only support 32-bit flash |
||||
* and DDR with SPD EEPROM configuration. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, sharen, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 12
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long TLB1_MAS0(0, 0, 0) |
||||
.long TLB1_MAS1(1, 0, 0, 0, 0) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long TLB1_MAS0(0, 0, 0) |
||||
.long TLB1_MAS1(1, 0, 0, 0, 0) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \ |
||||
0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \ |
||||
0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(0, 0, 0) |
||||
.long TLB1_MAS1(1, 0, 0, 0, 0) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \ |
||||
0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \ |
||||
0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(0, 0, 0) |
||||
.long TLB1_MAS1(1, 0, 0, 0, 0) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \ |
||||
0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \ |
||||
0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
.long TLB1_MAS0(0, 0, 0) |
||||
.long TLB1_MAS1(1, 0, 0, 0, 0) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \ |
||||
0,0,0,0,0,0,0,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \ |
||||
0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 6M4 FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long TLB1_MAS0(1, 0, 0) |
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long TLB1_MAS0(1, 1, 0) |
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long TLB1_MAS0(1, 2, 0) |
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \ |
||||
0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \ |
||||
0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xa0000000 256M PCI2 MEM First half |
||||
*/ |
||||
.long TLB1_MAS0(1, 3, 0) |
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xb0000000 256M PCI2 MEM Second half |
||||
*/ |
||||
.long TLB1_MAS0(1, 4, 0) |
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), \ |
||||
0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), \ |
||||
0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
* 0xe300_0000 16M PCI2 IO |
||||
*/ |
||||
.long TLB1_MAS0(1, 5, 0) |
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) |
||||
|
||||
/* |
||||
* TLB 6: 256M Non-cacheable, guarded |
||||
* 0xf0000000 Local bus expansion option. |
||||
* 0xfb000000 Configuration Latch register (one word) |
||||
* 0xfc000000 Up to 64M flash |
||||
*/ |
||||
.long TLB1_MAS0(1, 7, 0) |
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_OPTION_BASE), 0,0,0,0,1,0,1,0) |
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_OPTION_BASE), 0,0,0,0,0,1,0,1,0,1) |
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M |
||||
* 0xf000_0000 0xfaff_ffff Local bus 128M |
||||
* 0xfb00_0000 0xfb00_ffff Config Latch 64K |
||||
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
/* Map the whole localbus, including flash and reset latch. |
||||
*/ |
||||
#define LAWBAR5 ((CFG_LBC_OPTION_BASE>>12) & 0xfffff) |
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 6
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 |
||||
entry_end |
||||
@ -0,0 +1,397 @@ |
||||
/*
|
||||
* (C) Copyright 2005, Embedded Alley Solutions, Inc. |
||||
* Dan Malek, <dan@embeddedalley.com> |
||||
* Copied from STx GP3. |
||||
* Updates for Silicon Tx GP3 SSA |
||||
* |
||||
* (C) Copyright 2003,Motorola Inc. |
||||
* Xianghua Xiao, (X.Xiao@motorola.com) |
||||
* |
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
extern long int spd_sdram (void); |
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <ioports.h> |
||||
#include <asm/io.h> |
||||
#include <spd.h> |
||||
#include <miiphy.h> |
||||
|
||||
long int fixed_sdram (void); |
||||
|
||||
/*
|
||||
* I/O Port configuration table |
||||
* |
||||
* if conf is 1, then that port pin will be configured at boot time |
||||
* according to the five values podr/pdir/ppar/psor/pdat for that entry |
||||
*/ |
||||
|
||||
const iop_conf_t iop_conf_tab[4][32] = { |
||||
|
||||
/* Port A configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ |
||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ |
||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ |
||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ |
||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ |
||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ |
||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ |
||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ |
||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ |
||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ |
||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ |
||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ |
||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ |
||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ |
||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ |
||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ |
||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ |
||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ |
||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ |
||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ |
||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ |
||||
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ |
||||
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ |
||||
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ |
||||
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ |
||||
/* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ |
||||
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ |
||||
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ |
||||
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ |
||||
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ |
||||
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ |
||||
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ |
||||
}, |
||||
|
||||
/* Port B configuration */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ |
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ |
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ |
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ |
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ |
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ |
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ |
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ |
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ |
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ |
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ |
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ |
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ |
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ |
||||
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ |
||||
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ |
||||
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ |
||||
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ |
||||
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ |
||||
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ |
||||
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ |
||||
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ |
||||
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
}, |
||||
|
||||
/* Port C */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ |
||||
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ |
||||
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ |
||||
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ |
||||
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ |
||||
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ |
||||
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ |
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ |
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ |
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ |
||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ |
||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ |
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ |
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ |
||||
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ |
||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ |
||||
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ |
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ |
||||
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ |
||||
/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ |
||||
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ |
||||
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ |
||||
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ |
||||
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ |
||||
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ |
||||
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ |
||||
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ |
||||
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ |
||||
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ |
||||
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ |
||||
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ |
||||
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ |
||||
}, |
||||
|
||||
/* Port D */ |
||||
{ /* conf ppar psor pdir podr pdat */ |
||||
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ |
||||
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ |
||||
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ |
||||
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ |
||||
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ |
||||
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ |
||||
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ |
||||
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ |
||||
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ |
||||
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ |
||||
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ |
||||
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ |
||||
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ |
||||
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ |
||||
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ |
||||
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ |
||||
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ |
||||
/* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ |
||||
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
||||
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ |
||||
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ |
||||
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ |
||||
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ |
||||
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ |
||||
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ |
||||
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ |
||||
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ |
||||
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ |
||||
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ |
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ |
||||
} |
||||
}; |
||||
|
||||
static uint64_t next_led_update; |
||||
static uint led_bit; |
||||
|
||||
void |
||||
reset_phy(void) |
||||
{ |
||||
volatile uint *blatch; |
||||
int i; |
||||
|
||||
blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE; |
||||
|
||||
/* reset Giga bit Ethernet port if needed here */ |
||||
|
||||
#if 1 |
||||
*blatch &= ~0x000000c0; |
||||
udelay(100); |
||||
#else |
||||
*blatch = 0; |
||||
asm("eieio"); |
||||
for (i=0; i<1000; i++) |
||||
udelay(1000); |
||||
#endif |
||||
*blatch = 0x000000c1; /* Light one led, too */ |
||||
udelay(1000); |
||||
|
||||
#if 0 /* This is the port we really want to use for debugging. */
|
||||
/* reset the CPM FEC port */ |
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
bcsr->bcsr2 &= ~FETH2_RST; |
||||
udelay(2); |
||||
bcsr->bcsr2 |= FETH2_RST; |
||||
udelay(1000); |
||||
#elif (CONFIG_ETHER_INDEX == 3) |
||||
bcsr->bcsr3 &= ~FETH3_RST; |
||||
udelay(2); |
||||
bcsr->bcsr3 |= FETH3_RST; |
||||
udelay(1000); |
||||
#endif |
||||
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) |
||||
/* reset PHY */ |
||||
miiphy_reset("FCC1 ETHERNET", 0x0); |
||||
|
||||
/* change PHY address to 0x02 */ |
||||
bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); |
||||
|
||||
bb_miiphy_write(NULL, 0x02, PHY_BMCR, |
||||
PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); |
||||
#endif /* CONFIG_MII */ |
||||
#endif |
||||
} |
||||
|
||||
int |
||||
board_early_init_f(void) |
||||
{ |
||||
#if defined(CONFIG_PCI) |
||||
volatile immap_t *immr = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_pcix_t *pci = &immr->im_pcix; |
||||
|
||||
pci->peer &= 0xfffffffdf; /* disable master abort */ |
||||
#endif |
||||
|
||||
/* Why is the phy reset done _after_ the ethernet
|
||||
* initialization in lib_ppc/board.c? |
||||
* Do it here so it's done before the TSECs are used. |
||||
*/ |
||||
reset_phy(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int |
||||
checkboard(void) |
||||
{ |
||||
printf ("Board: Silicon Tx GPPP SSA Board\n"); |
||||
return (0); |
||||
} |
||||
|
||||
/* Blinkin' LEDS for Robert.
|
||||
*/ |
||||
void |
||||
show_activity(int flag) |
||||
{ |
||||
volatile uint *blatch; |
||||
|
||||
if (next_led_update > get_ticks()) |
||||
return; |
||||
|
||||
blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE; |
||||
|
||||
led_bit >>= 1; |
||||
if (led_bit == 0) |
||||
led_bit = 0x08; |
||||
*blatch = (0xc0 | led_bit); |
||||
eieio(); |
||||
next_led_update += (get_tbclk() / 4); |
||||
} |
||||
|
||||
long int |
||||
initdram (int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
extern long spd_sdram (void); |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
|
||||
#if defined(CONFIG_DDR_DLL) |
||||
{ |
||||
volatile ccsr_gur_t *gur= &immap->im_gur; |
||||
uint temp_ddrdll = 0; |
||||
|
||||
/* Work around to stabilize DDR DLL */ |
||||
temp_ddrdll = gur->ddrdllcr; |
||||
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; |
||||
asm("sync;isync;msync"); |
||||
} |
||||
#endif |
||||
|
||||
dram_size = spd_sdram (); |
||||
|
||||
#if defined(CONFIG_DDR_ECC) |
||||
/* Initialize and enable DDR ECC.
|
||||
*/ |
||||
ddr_enable_ecc(dram_size); |
||||
#endif |
||||
|
||||
return dram_size; |
||||
} |
||||
|
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int testdram (void) |
||||
{ |
||||
uint *pstart = (uint *) CFG_MEMTEST_START; |
||||
uint *pend = (uint *) CFG_MEMTEST_END; |
||||
uint *p; |
||||
|
||||
printf("SDRAM test phase 1:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("SDRAM test phase 2:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("SDRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("SDRAM test passed.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_stxgp3_config_table[] = { |
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
||||
} }, |
||||
{ } |
||||
}; |
||||
#endif |
||||
|
||||
|
||||
static struct pci_controller hose = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table: pci_stxgp3_config_table, |
||||
#endif |
||||
}; |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
void |
||||
pci_init_board(void) |
||||
{ |
||||
#ifdef CONFIG_PCI |
||||
extern void pci_mpc85xx_init(struct pci_controller *hose); |
||||
|
||||
pci_mpc85xx_init(&hose); |
||||
#endif /* CONFIG_PCI */ |
||||
} |
||||
@ -0,0 +1,158 @@ |
||||
/* |
||||
* (C) Copyright 2005 Embedded Alley Solutions, Inc. |
||||
* Dan Malek, <dan@embeddedalley.com> |
||||
* Copied from STx GP3. |
||||
* Updates for Silicon Tx GP3 SSA. |
||||
* |
||||
* (C) Copyright 2002,2003,Motorola,Inc. |
||||
* Xianghua Xiao, X.Xiao@motorola.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/mpc85xx/start.o (.bootpg) |
||||
board/stxssa/init.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc85xx/start.o (.text) |
||||
board/stxssa/init.o (.text) |
||||
cpu/mpc85xx/commproc.o (.text) |
||||
cpu/mpc85xx/traps.o (.text) |
||||
cpu/mpc85xx/interrupts.o (.text) |
||||
cpu/mpc85xx/serial_scc.o (.text) |
||||
cpu/mpc85xx/ether_fcc.o (.text) |
||||
cpu/mpc85xx/cpu_init.o (.text) |
||||
cpu/mpc85xx/cpu.o (.text) |
||||
cpu/mpc85xx/speed.o (.text) |
||||
cpu/mpc85xx/spd_sdram.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,418 @@ |
||||
/*
|
||||
* (C) Copyright 2005 Embedded Alley Solutions, Inc. |
||||
* Dan Malek <dan@embeddedalley.com> |
||||
* Copied from STx GP3. |
||||
* Updates for Silicon Tx GP3 SSA board. |
||||
* |
||||
* (C) Copyright 2002,2003 Motorola,Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* mpc8560ads board configuration file */ |
||||
/* please refer to doc/README.mpc85xx for more info */ |
||||
/* make sure you change the MAC address and other network params first,
|
||||
* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
||||
#define CONFIG_CPM2 1 /* has CPM2 */ |
||||
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ |
||||
|
||||
#undef CONFIG_PCI /* pci ethernet support */ |
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support*/ |
||||
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#undef CONFIG_DDR_DLL /* possible DLL fix needed */ |
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
||||
|
||||
|
||||
/* sysclk for MPC85xx
|
||||
*/ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ |
||||
|
||||
/* Blinkin' LEDs for Robert :-)
|
||||
*/ |
||||
#define CONFIG_SHOW_ACTIVITY 1 |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00400000 |
||||
|
||||
|
||||
/* Localbus connector. There are many options that can be
|
||||
* connected here, including sdram or lots of flash. |
||||
* This address, however, is used to configure a 256M local bus |
||||
* window that includes the Config latch below. |
||||
*/ |
||||
#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */ |
||||
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */ |
||||
|
||||
/* There are various flash options used, we configure for the largest,
|
||||
* which is 64Mbytes. The CFI works fine and will discover the proper |
||||
* sizes. |
||||
*/ |
||||
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH 64M */ |
||||
#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ |
||||
#define CFG_OR0_PRELIM 0xfc000ff7 /* 64 MB Flash */ |
||||
|
||||
#define CFG_FLASH_CFI 1 |
||||
#define CFG_FLASH_CFI_DRIVER 1 |
||||
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
||||
|
||||
#define CFG_FLASH_PROTECTION |
||||
|
||||
/* The configuration latch is Chip Select 1.
|
||||
* It's an 8-bit latch in the lower 8 bits of the word. |
||||
*/ |
||||
#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */ |
||||
#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */ |
||||
#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#ifdef CFG_RAMBOOT |
||||
#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ |
||||
#else |
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#endif |
||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
||||
|
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
||||
|
||||
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
/* local bus definitions */ |
||||
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ |
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
#define CFG_LBC_LSRT 0x20000000 |
||||
#define CFG_LBC_MRTPR 0x20000000 |
||||
#define CFG_LBC_LSDMR_1 0x2861b723 |
||||
#define CFG_LBC_LSDMR_2 0x0861b723 |
||||
#define CFG_LBC_LSDMR_3 0x0861b723 |
||||
#define CFG_LBC_LSDMR_4 0x1861b723 |
||||
#define CFG_LBC_LSDMR_5 0x4061b723 |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 2 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CONFIG_BAUDRATE 38400 |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#if 0 |
||||
#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ |
||||
#else |
||||
/* I did the 'if 0' so we could keep the syntax above if ever needed. */ |
||||
#undef CFG_I2C_NOPROBES |
||||
#endif |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
|
||||
/* I2C EEPROM. AT24C32, we keep our environment in here.
|
||||
*/ |
||||
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 |
||||
|
||||
/*
|
||||
* Standard 8555 PCI mapping. |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI1_IO_BASE 0x00000000 |
||||
#define CFG_PCI1_IO_PHYS 0xe2000000 |
||||
#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ |
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000 |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI2_IO_BASE 0x00000000 |
||||
#define CFG_PCI2_IO_PHYS 0xe3000000 |
||||
#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ |
||||
|
||||
#if defined(CONFIG_PCI) /* PCI Ethernet card */ |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
|
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xe0000000 |
||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
||||
#endif |
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
|
||||
#define CONFIG_MPC85XX_TSEC1 1 |
||||
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" |
||||
#define CONFIG_MPC85XX_TSEC2 1 |
||||
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" |
||||
#undef CONFIG_MPS85XX_FEC |
||||
|
||||
#define TSEC1_PHY_ADDR 2 |
||||
#define TSEC2_PHY_ADDR 4 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define CONFIG_ETHPRIME "TSEC0" |
||||
|
||||
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
||||
|
||||
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ |
||||
#undef CONFIG_ETHER_NONE /* define if ether on something else */ |
||||
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
||||
|
||||
#if (CONFIG_ETHER_INDEX == 2) |
||||
/*
|
||||
* - Rx-CLK is CLK13 |
||||
* - Tx-CLK is CLK14 |
||||
* - Select bus for bd/buffers |
||||
* - Full duplex |
||||
*/ |
||||
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
||||
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
||||
#define CFG_CPMFCR_RAMTYPE 0 |
||||
#if 0 |
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE) |
||||
#else |
||||
#define CFG_FCC_PSMR 0 |
||||
#endif |
||||
#define FETH2_RST 0x01 |
||||
#elif (CONFIG_ETHER_INDEX == 3) |
||||
/* need more definitions here for FE3 */ |
||||
#define FETH3_RST 0x80 |
||||
#endif /* CONFIG_ETHER_INDEX */ |
||||
|
||||
/* MDIO is done through the TSEC0 control.
|
||||
*/ |
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
||||
|
||||
#endif |
||||
|
||||
/* Environment */ |
||||
/* Config in EEPROM
|
||||
*/ |
||||
#if 1 |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_ENV_OFFSET 0 |
||||
#define CFG_ENV_SIZE 2048 |
||||
#else |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SECT_SIZE 0x10000 |
||||
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00030000) |
||||
#define CFG_ENV_OFFSET 0 |
||||
#define CFG_ENV_SIZE 0x4000 |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" |
||||
#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" |
||||
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ |
||||
CFG_CMD_PING | CFG_CMD_I2C) & \
|
||||
~(CFG_CMD_ENV | \
|
||||
CFG_CMD_LOADS )) |
||||
#elif defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ |
||||
CFG_CMD_MII | CFG_CMD_I2C ) & \
|
||||
~(CFG_CMD_ENV)) |
||||
#elif defined(CONFIG_ETHER_ON_FCC) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ |
||||
CFG_CMD_PING | CFG_CMD_I2C) & \
|
||||
~(CFG_CMD_ENV)) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ |
||||
CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) |
||||
#elif defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ |
||||
CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C) |
||||
#elif defined(CONFIG_ETHER_ON_FCC) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ |
||||
CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) |
||||
#endif |
||||
#endif |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x1000000 /* default load address */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*Note: change below for your network setting!!! */ |
||||
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
||||
#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b |
||||
#define CONFIG_HAS_ETH2 |
||||
#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c |
||||
#endif |
||||
|
||||
#define CONFIG_SERVERIP 192.168.85.1 |
||||
#define CONFIG_IPADDR 192.168.85.60 |
||||
#define CONFIG_GATEWAYIP 192.168.85.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_HOSTNAME STX_SSA |
||||
#define CONFIG_ROOTPATH /gppproot |
||||
#define CONFIG_BOOTFILE uImage |
||||
#define CONFIG_LOADADDR 0x1000000 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue