To compatible with different rockchip soc, we split the mipi dirver into common and soc specific parts, and all the soc share the common functions from common driver part. Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [agust: fix build breakage and warnings] Signed-off-by: Anatolij Gustschin <agust@denx.de>master
eric.gao@rock-chips.com
8 years ago
committed by
Anatolij Gustschin
parent
c83e835966
commit
36602eba80
@ -0,0 +1,182 @@ |
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/*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd |
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* Author: Eric Gao <eric.gao@rock-chips.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <clk.h> |
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#include <display.h> |
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#include <dm.h> |
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#include <fdtdec.h> |
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#include <panel.h> |
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#include <regmap.h> |
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#include "rk_mipi.h" |
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#include <syscon.h> |
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#include <asm/gpio.h> |
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#include <asm/hardware.h> |
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#include <asm/io.h> |
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#include <dm/uclass-internal.h> |
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#include <linux/kernel.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rk3399.h> |
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#include <asm/arch/grf_rk3399.h> |
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#include <asm/arch/rockchip_mipi_dsi.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Select mipi dsi source, big or little vop */ |
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static int rk_mipi_dsi_source_select(struct udevice *dev) |
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{ |
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struct rk_mipi_priv *priv = dev_get_priv(dev); |
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struct rk3399_grf_regs *grf = priv->grf; |
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struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev); |
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/* Select the video source */ |
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switch (disp_uc_plat->source_id) { |
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case VOP_B: |
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rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, |
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GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT); |
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break; |
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case VOP_L: |
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rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, |
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GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT); |
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break; |
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default: |
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debug("%s: Invalid VOP id\n", __func__); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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/* Setup mipi dphy working mode */ |
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static void rk_mipi_dphy_mode_set(struct udevice *dev) |
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{ |
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struct rk_mipi_priv *priv = dev_get_priv(dev); |
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struct rk3399_grf_regs *grf = priv->grf; |
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int val; |
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/* Set Controller as TX mode */ |
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val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT; |
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rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); |
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/* Exit tx stop mode */ |
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val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT; |
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rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val); |
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/* Disable turnequest */ |
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val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT; |
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rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val); |
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} |
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/*
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* This function is called by rk_display_init() using rk_mipi_dsi_enable() and |
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* rk_mipi_phy_enable() to initialize mipi controller and dphy. If success, |
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* enable backlight. |
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*/ |
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static int rk_display_enable(struct udevice *dev, int panel_bpp, |
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const struct display_timing *timing) |
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{ |
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int ret; |
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struct rk_mipi_priv *priv = dev_get_priv(dev); |
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/* Fill the mipi controller parameter */ |
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priv->ref_clk = 24 * MHz; |
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priv->sys_clk = priv->ref_clk; |
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priv->pix_clk = timing->pixelclock.typ; |
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priv->phy_clk = priv->pix_clk * 6; |
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priv->txbyte_clk = priv->phy_clk / 8; |
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priv->txesc_clk = 20 * MHz; |
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/* Select vop port, big or little */ |
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rk_mipi_dsi_source_select(dev); |
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/* Set mipi dphy work mode */ |
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rk_mipi_dphy_mode_set(dev); |
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/* Config and enable mipi dsi according to timing */ |
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ret = rk_mipi_dsi_enable(dev, timing); |
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if (ret) { |
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debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n", |
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__func__, ret); |
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return ret; |
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} |
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/* Config and enable mipi phy */ |
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ret = rk_mipi_phy_enable(dev); |
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if (ret) { |
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debug("%s: rk_mipi_phy_enable() failed (err=%d)\n", |
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__func__, ret); |
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return ret; |
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} |
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/* Enable backlight */ |
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ret = panel_enable_backlight(priv->panel); |
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if (ret) { |
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debug("%s: panel_enable_backlight() failed (err=%d)\n", |
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__func__, ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int rk_mipi_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct rk_mipi_priv *priv = dev_get_priv(dev); |
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
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if (priv->grf <= 0) { |
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debug("%s: Get syscon grf failed (ret=%p)\n", |
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__func__, priv->grf); |
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return -ENXIO; |
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} |
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priv->regs = dev_read_addr(dev); |
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if (priv->regs == FDT_ADDR_T_NONE) { |
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debug("%s: Get MIPI dsi address failed\n", __func__); |
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return -ENXIO; |
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} |
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return 0; |
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} |
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/*
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* Probe function: check panel existence and readingit's timing. Then config |
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* mipi dsi controller and enable it according to the timing parameter. |
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*/ |
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static int rk_mipi_probe(struct udevice *dev) |
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{ |
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int ret; |
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struct rk_mipi_priv *priv = dev_get_priv(dev); |
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ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel", |
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&priv->panel); |
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if (ret) { |
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debug("%s: Can not find panel (err=%d)\n", __func__, ret); |
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return ret; |
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} |
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return 0; |
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} |
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static const struct dm_display_ops rk_mipi_dsi_ops = { |
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.read_timing = rk_mipi_read_timing, |
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.enable = rk_display_enable, |
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}; |
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static const struct udevice_id rk_mipi_dsi_ids[] = { |
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{ .compatible = "rockchip,rk3399_mipi_dsi" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(rk_mipi_dsi) = { |
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.name = "rk_mipi_dsi", |
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.id = UCLASS_DISPLAY, |
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.of_match = rk_mipi_dsi_ids, |
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.ofdata_to_platdata = rk_mipi_ofdata_to_platdata, |
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.probe = rk_mipi_probe, |
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.ops = &rk_mipi_dsi_ops, |
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.priv_auto_alloc_size = sizeof(struct rk_mipi_priv), |
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}; |
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@ -0,0 +1,32 @@ |
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/*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd |
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* Author: Eric Gao <eric.gao@rock-chips.com> |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __RK_MIPI_H |
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#define __RK_MIPI_H |
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struct rk_mipi_priv { |
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ulong regs; |
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void *grf; |
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struct udevice *panel; |
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struct mipi_dsi *dsi; |
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u32 ref_clk; |
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u32 sys_clk; |
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u32 pix_clk; |
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u32 phy_clk; |
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u32 txbyte_clk; |
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u32 txesc_clk; |
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}; |
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int rk_mipi_read_timing(struct udevice *dev, |
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struct display_timing *timing); |
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int rk_mipi_dsi_enable(struct udevice *dev, |
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const struct display_timing *timing); |
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int rk_mipi_phy_enable(struct udevice *dev); |
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#endif |
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