With dropping support for some boards and the deletion of some source files, it appears that both of these directories are now superfluous. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>master
Robert P. J. Day
8 years ago
committed by
Tom Rini
parent
2507854e46
commit
367d789d87
@ -1,94 +0,0 @@ |
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(cpu/mpc7xxx/start.S) |
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start: |
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b boot_cold |
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start_warm: |
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b boot_warm |
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boot_cold: |
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boot_warm: |
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clear bats |
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init l2 (if enabled) |
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init altivec (if enabled) |
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invalidate l2 (if enabled) |
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setup bats (from defines in config_EVB) |
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enable_addr_trans: (if MMU enabled) |
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enable MSR_IR and MSR_DR |
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jump to in_flash |
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|
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in_flash: |
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enable l1 dcache |
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gal_low_init: (board/evb64260/sdram_init.S) |
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config SDRAM (CFG, TIMING, DECODE) |
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init scratch regs (810 + 814) |
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|
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detect DIMM0 (bank 0 only) |
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config SDRAM_PARA0 to 256/512Mbit |
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bl sdram_op_mode |
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detect bank0 width |
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write scratch reg 810 |
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config SDRAM_PARA0 with results |
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config SDRAM_PARA1 with results |
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|
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detect DIMM1 (bank 2 only) |
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config SDRAM_PARA2 to 256/512Mbit |
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detect bank2 width |
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write scratch reg 814 |
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config SDRAM_PARA2 with results |
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config SDRAM_PARA3 with results |
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|
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setup device bus timings/width |
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setup boot device timings/width |
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|
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setup CPU_CONF (0x0) |
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setup cpu master control register 0x160 |
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setup PCI0 TIMEOUT |
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setup PCI1 TIMEOUT |
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setup PCI0 BAR |
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setup PCI1 BAR |
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|
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setup MPP control 0-3 |
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setup GPP level control |
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setup Serial ports multiplex |
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|
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setup stack pointer (r1) |
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setup GOT |
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call cpu_init_f |
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debug leds |
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board_init_f: (common/board.c) |
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board_early_init_f: |
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remap gt regs? |
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map PCI mem/io |
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map device space |
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clear out interrupts |
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init_timebase |
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env_init |
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serial_init |
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console_init_f |
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display_options |
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initdram: (board/evb64260/evb64260.c) |
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detect memory |
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for each bank: |
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dram_size() |
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setup PCI slave memory mappings |
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setup SCS |
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setup monitor |
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alloc board info struct |
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init bd struct |
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relocate_code: (cpu/mpc7xxx/start.S) |
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copy,got,clearbss |
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board_init_r(bd, dest_addr) (common/board.c) |
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setup bd function pointers |
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trap_init |
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flash_init: (board/evb64260/flash.c) |
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setup bd flash info |
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cpu_init_r: (cpu/mpc7xxx/cpu_init.c) |
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nothing |
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mem_malloc_init |
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malloc_bin_reloc |
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spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) |
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env_relocated |
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misc_init_r(bd): (board/evb64260/evb64260.c) |
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mpsc_init2 |
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@ -1,16 +0,0 @@ |
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/*
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Hacked for the DB64360 board by Ingo.Assmus@keymile.com |
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*/ |
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|
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#ifndef __I2C_H__ |
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#define __I2C_H__ |
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|
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/* function declarations */ |
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uchar i2c_read(uchar, unsigned int, int, uchar*, int); |
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#endif |
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@ -1,170 +0,0 @@ |
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/*
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Hacked for the marvell db64360 eval board by |
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* Ingo Assmus <ingo.assmus@keymile.com> |
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*/ |
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|
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/*************** DEFINES for Intel StrataFlash FLASH chip ********************/ |
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/*
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* acceptable chips types are: |
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* |
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* 28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A |
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*/ |
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|
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/* register addresses, valid only following an CHIP_CMD_RD_ID command */ |
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#define CHIP_ADDR_REG_MAN 0x000000 /* manufacturer's id */ |
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#define CHIP_ADDR_REG_DEV 0x000001 /* device id */ |
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#define CHIP_ADDR_REG_CFGM 0x000003 /* master lock config */ |
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#define CHIP_ADDR_REG_CFG(b) (((b)<<16)|2) /* lock config for block b */ |
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|
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/* Commands */ |
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#define CHIP_CMD_RST 0xFF /* reset flash */ |
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#define CHIP_CMD_RD_ID 0x90 /* read the id and lock bits */ |
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#define CHIP_CMD_RD_QUERY 0x98 /* read device capabilities */ |
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#define CHIP_CMD_RD_STAT 0x70 /* read the status register */ |
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#define CHIP_CMD_CLR_STAT 0x50 /* clear the staus register */ |
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#define CHIP_CMD_WR_BUF 0xE8 /* clear the staus register */ |
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#define CHIP_CMD_PROG 0x40 /* program word command */ |
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#define CHIP_CMD_ERASE1 0x20 /* 1st word for block erase */ |
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#define CHIP_CMD_ERASE2 0xD0 /* 2nd word for block erase */ |
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#define CHIP_CMD_ERASE_SUSP 0xB0 /* suspend block erase */ |
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#define CHIP_CMD_LOCK 0x60 /* 1st word for all lock cmds */ |
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#define CHIP_CMD_SET_LOCK_BLK 0x01 /* 2nd wrd set block lock bit */ |
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#define CHIP_CMD_SET_LOCK_MSTR 0xF1 /* 2nd wrd set master lck bit */ |
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#define CHIP_CMD_CLR_LOCK_BLK 0xD0 /* 2nd wrd clear blk lck bit */ |
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|
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/* status register bits */ |
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#define CHIP_STAT_DPS 0x02 /* Device Protect Status */ |
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#define CHIP_STAT_VPPS 0x08 /* VPP Status */ |
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#define CHIP_STAT_PSLBS 0x10 /* Program+Set Lock Bit Stat */ |
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#define CHIP_STAT_ECLBS 0x20 /* Erase+Clr Lock Bit Stat */ |
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#define CHIP_STAT_ESS 0x40 /* Erase Suspend Status */ |
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#define CHIP_STAT_RDY 0x80 /* WSM Mach Status, 1=rdy */ |
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#define CHIP_STAT_ERR (CHIP_STAT_VPPS | CHIP_STAT_DPS | \ |
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CHIP_STAT_ECLBS | CHIP_STAT_PSLBS) |
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/* ID and Lock Configuration */ |
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#define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ |
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#define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ |
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#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID |
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/* dimensions */ |
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#define CHIP_WIDTH 2 /* chips are in 16 bit mode */ |
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#define CHIP_WSHIFT 1 /* (log2 of CHIP_WIDTH) */ |
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#define CHIP_NBLOCKS 128 |
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#define CHIP_BLKSZ (128 * 1024) /* of 128Kbytes each */ |
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#define CHIP_SIZE (CHIP_BLKSZ * CHIP_NBLOCKS) |
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/********************** DEFINES for Hymod Flash ******************************/ |
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/*
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* The hymod board has 2 x 28F320J5 chips running in |
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* 16 bit mode, for a 32 bit wide bank. |
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*/ |
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typedef unsigned short bank_word_t; /* 8/16/32/64bit unsigned int */ |
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typedef volatile bank_word_t *bank_addr_t; |
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typedef unsigned long bank_size_t; /* want this big - >= 32 bit */ |
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#define BANK_CHIP_WIDTH 1 /* each bank is 1 chip wide */ |
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#define BANK_CHIP_WSHIFT 0 /* (log2 of BANK_CHIP_WIDTH) */ |
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#define BANK_WIDTH (CHIP_WIDTH * BANK_CHIP_WIDTH) |
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#define BANK_WSHIFT (CHIP_WSHIFT + BANK_CHIP_WSHIFT) |
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#define BANK_NBLOCKS CHIP_NBLOCKS |
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#define BANK_BLKSZ (CHIP_BLKSZ * BANK_CHIP_WIDTH) |
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#define BANK_SIZE (CHIP_SIZE * BANK_CHIP_WIDTH) |
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#define MAX_BANKS 1 /* only one bank possible */ |
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/* align bank addresses and sizes to bank word boundaries */ |
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#define BANK_ADDR_WORD_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ |
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& ~(BANK_WIDTH - 1))) |
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#define BANK_SIZE_WORD_ALIGN(s) ((bank_size_t)BANK_ADDR_WORD_ALIGN( \ |
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(bank_size_t)(s) + (BANK_WIDTH - 1))) |
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/* align bank addresses and sizes to bank block boundaries */ |
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#define BANK_ADDR_BLK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ |
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& ~(BANK_BLKSZ - 1))) |
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#define BANK_SIZE_BLK_ALIGN(s) ((bank_size_t)BANK_ADDR_BLK_ALIGN( \ |
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(bank_size_t)(s) + (BANK_BLKSZ - 1))) |
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/* align bank addresses and sizes to bank boundaries */ |
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#define BANK_ADDR_BANK_ALIGN(a) ((bank_addr_t)((bank_size_t)(a) \ |
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& ~(BANK_SIZE - 1))) |
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#define BANK_SIZE_BANK_ALIGN(s) ((bank_size_t)BANK_ADDR_BANK_ALIGN( \ |
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(bank_size_t)(s) + (BANK_SIZE - 1))) |
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/* add an offset to a bank address */ |
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#define BANK_ADDR_OFFSET(a, o) (bank_addr_t)((bank_size_t)(a) + \ |
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(bank_size_t)(o)) |
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/* get base address of bank b, given flash base address a */ |
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#define BANK_ADDR_BASE(a, b) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ |
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(bank_size_t)(b) * BANK_SIZE) |
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/* adjust a bank address to start of next word, block or bank */ |
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#define BANK_ADDR_NEXT_WORD(a) BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \ |
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BANK_WIDTH) |
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#define BANK_ADDR_NEXT_BLK(a) BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \ |
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BANK_BLKSZ) |
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#define BANK_ADDR_NEXT_BANK(a) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ |
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BANK_SIZE) |
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/* get bank address of chip register r given a bank base address a */ |
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#define BANK_ADDR_REG(a, r) BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \ |
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((bank_size_t)(r) << BANK_WSHIFT)) |
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/* make a bank address for each chip register address */ |
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#define BANK_ADDR_REG_MAN(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN) |
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#define BANK_ADDR_REG_DEV(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV) |
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#define BANK_ADDR_REG_CFGM(a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM) |
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#define BANK_ADDR_REG_CFG(b,a) BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b)) |
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/*
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* replicate a chip cmd/stat/rd value into each byte position within a word |
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* so that multiple chips are accessed in a single word i/o operation |
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* |
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* this must be as wide as the bank_word_t type, and take into account the |
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* chip width and bank layout |
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*/ |
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#define BANK_FILL_WORD(o) ((bank_word_t)(o)) |
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/* make a bank word value for each chip cmd/stat/rd value */ |
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/* Commands */ |
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#define BANK_CMD_RST BANK_FILL_WORD(CHIP_CMD_RST) |
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#define BANK_CMD_RD_ID BANK_FILL_WORD(CHIP_CMD_RD_ID) |
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#define BANK_CMD_RD_STAT BANK_FILL_WORD(CHIP_CMD_RD_STAT) |
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#define BANK_CMD_CLR_STAT BANK_FILL_WORD(CHIP_CMD_CLR_STAT) |
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#define BANK_CMD_ERASE1 BANK_FILL_WORD(CHIP_CMD_ERASE1) |
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#define BANK_CMD_ERASE2 BANK_FILL_WORD(CHIP_CMD_ERASE2) |
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#define BANK_CMD_PROG BANK_FILL_WORD(CHIP_CMD_PROG) |
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#define BANK_CMD_LOCK BANK_FILL_WORD(CHIP_CMD_LOCK) |
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#define BANK_CMD_SET_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK) |
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#define BANK_CMD_SET_LOCK_MSTR BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR) |
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#define BANK_CMD_CLR_LOCK_BLK BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK) |
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/* status register bits */ |
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#define BANK_STAT_DPS BANK_FILL_WORD(CHIP_STAT_DPS) |
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#define BANK_STAT_PSS BANK_FILL_WORD(CHIP_STAT_PSS) |
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#define BANK_STAT_VPPS BANK_FILL_WORD(CHIP_STAT_VPPS) |
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#define BANK_STAT_PSLBS BANK_FILL_WORD(CHIP_STAT_PSLBS) |
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#define BANK_STAT_ECLBS BANK_FILL_WORD(CHIP_STAT_ECLBS) |
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#define BANK_STAT_ESS BANK_FILL_WORD(CHIP_STAT_ESS) |
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#define BANK_STAT_RDY BANK_FILL_WORD(CHIP_STAT_RDY) |
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#define BANK_STAT_ERR BANK_FILL_WORD(CHIP_STAT_ERR) |
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/* ID and Lock Configuration */ |
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#define BANK_RD_ID_LOCK BANK_FILL_WORD(CHIP_RD_ID_LOCK) |
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#define BANK_RD_ID_MAN BANK_FILL_WORD(CHIP_RD_ID_MAN) |
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#define BANK_RD_ID_DEV BANK_FILL_WORD(CHIP_RD_ID_DEV) |
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File diff suppressed because it is too large
Load Diff
@ -1,66 +0,0 @@ |
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/*
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* COM1 NS16550 support |
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* originally from linux source (arch/powerpc/boot/ns16550.c) |
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* modified to use CONFIG_SYS_ISA_MEM and new defines |
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* |
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* further modified by Josh Huber <huber@mclx.com> to support |
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* the DUART on the Galileo Eval board. (db64360) |
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*/ |
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#include <config.h> |
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#include "ns16550.h" |
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#ifdef ZUMA_NTL |
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/* no 16550 device */ |
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#else |
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const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0), |
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(NS16550_t) (CONFIG_SYS_DUART_IO + 0x20) |
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}; |
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volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) |
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{ |
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volatile struct NS16550 *com_port; |
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com_port = (struct NS16550 *) COM_PORTS[chan]; |
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com_port->ier = 0x00; |
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com_port->lcr = LCR_BKSE; /* Access baud rate */ |
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com_port->dll = baud_divisor & 0xff; /* 9600 baud */ |
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com_port->dlm = (baud_divisor >> 8) & 0xff; |
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com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ |
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com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ |
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/* Clear & enable FIFOs */ |
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com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; |
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return (com_port); |
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} |
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void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor) |
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{ |
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com_port->ier = 0x00; |
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com_port->lcr = LCR_BKSE; /* Access baud rate */ |
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com_port->dll = baud_divisor & 0xff; /* 9600 baud */ |
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com_port->dlm = (baud_divisor >> 8) & 0xff; |
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com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */ |
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com_port->mcr = MCR_DTR | MCR_RTS; /* RTS/DTR */ |
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/* Clear & enable FIFOs */ |
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com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; |
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} |
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void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c) |
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{ |
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while ((com_port->lsr & LSR_THRE) == 0); |
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com_port->thr = c; |
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} |
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unsigned char NS16550_getc (volatile struct NS16550 *com_port) |
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{ |
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while ((com_port->lsr & LSR_DR) == 0); |
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return (com_port->rbr); |
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} |
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int NS16550_tstc (volatile struct NS16550 *com_port) |
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{ |
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return ((com_port->lsr & LSR_DR) != 0); |
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} |
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#endif |
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@ -1,102 +0,0 @@ |
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/*
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* NS16550 Serial Port |
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* originally from linux source (arch/powerpc/boot/ns16550.h) |
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* modified slightly to |
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* have addresses as offsets from CONFIG_SYS_ISA_BASE |
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* added a few more definitions |
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* added prototypes for ns16550.c |
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* reduced no of com ports to 2 |
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* modifications (c) Rob Taylor, Flying Pig Systems. 2000. |
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* |
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* further modified to support the DUART in the Galileo eval board |
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* modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. |
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*/ |
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#ifndef __NS16550_H__ |
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#define __NS16550_H__ |
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/* the padding is necessary because on the galileo board the UART is
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wired in with the 3 address lines shifted over by 2 bits */ |
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struct NS16550 |
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{ |
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unsigned char rbr; /* 0 = 0-3*/ |
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int pad1:24; |
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unsigned char ier; /* 1 = 4-7*/ |
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int pad2:24; |
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unsigned char fcr; /* 2 = 8-b*/ |
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int pad3:24; |
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unsigned char lcr; /* 3 = c-f*/ |
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int pad4:24; |
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unsigned char mcr; /* 4 = 10-13*/ |
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int pad5:24; |
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unsigned char lsr; /* 5 = 14-17*/ |
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int pad6:24; |
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unsigned char msr; /* 6 =18-1b*/ |
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int pad7:24; |
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unsigned char scr; /* 7 =1c-1f*/ |
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int pad8:24; |
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} __attribute__ ((packed)); |
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/* aliases */ |
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#define thr rbr |
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#define iir fcr |
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#define dll rbr |
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#define dlm ier |
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#define FCR_FIFO_EN 0x01 /*fifo enable*/ |
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#define FCR_RXSR 0x02 /*receiver soft reset*/ |
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#define FCR_TXSR 0x04 /*transmitter soft reset*/ |
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#define MCR_DTR 0x01 |
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#define MCR_RTS 0x02 |
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#define MCR_DMA_EN 0x04 |
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#define MCR_TX_DFR 0x08 |
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#define LCR_WLS_MSK 0x03 /* character length slect mask*/ |
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#define LCR_WLS_5 0x00 /* 5 bit character length */ |
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#define LCR_WLS_6 0x01 /* 6 bit character length */ |
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#define LCR_WLS_7 0x02 /* 7 bit character length */ |
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#define LCR_WLS_8 0x03 /* 8 bit character length */ |
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#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ |
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#define LCR_PEN 0x08 /* Parity eneble*/ |
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#define LCR_EPS 0x10 /* Even Parity Select*/ |
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#define LCR_STKP 0x20 /* Stick Parity*/ |
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#define LCR_SBRK 0x40 /* Set Break*/ |
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#define LCR_BKSE 0x80 /* Bank select enable*/ |
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#define LSR_DR 0x01 /* Data ready */ |
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#define LSR_OE 0x02 /* Overrun */ |
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#define LSR_PE 0x04 /* Parity error */ |
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#define LSR_FE 0x08 /* Framing error */ |
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#define LSR_BI 0x10 /* Break */ |
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#define LSR_THRE 0x20 /* Xmit holding register empty */ |
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#define LSR_TEMT 0x40 /* Xmitter empty */ |
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#define LSR_ERR 0x80 /* Error */ |
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/* useful defaults for LCR*/ |
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#define LCR_8N1 0x03 |
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#define COM1 0x03F8 |
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#define COM2 0x02F8 |
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volatile struct NS16550 * NS16550_init(int chan, int baud_divisor); |
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void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c); |
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unsigned char NS16550_getc(volatile struct NS16550 *com_port); |
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int NS16550_tstc(volatile struct NS16550 *com_port); |
||||
void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor); |
||||
|
||||
typedef struct NS16550 *NS16550_t; |
||||
|
||||
extern const NS16550_t COM_PORTS[]; |
||||
|
||||
#endif |
||||
@ -1,162 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. |
||||
* |
||||
* modified for marvell db64360 eval board by |
||||
* Ingo Assmus <ingo.assmus@keymile.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* serial.c - serial support for the gal ev board |
||||
*/ |
||||
|
||||
/* supports both the 16650 duart and the MPSC */ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <serial.h> |
||||
#include <linux/compiler.h> |
||||
|
||||
#include "../include/memory.h" |
||||
|
||||
#include "ns16550.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_MPSC |
||||
static int marvell_serial_init(void) |
||||
{ |
||||
#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) |
||||
int clock_divisor = 230400 / gd->baudrate; |
||||
#endif |
||||
|
||||
mpsc_init (gd->baudrate); |
||||
|
||||
/* init the DUART chans so that KGDB in the kernel can use them */ |
||||
#ifdef CONFIG_SYS_INIT_CHAN1 |
||||
NS16550_reinit (COM_PORTS[0], clock_divisor); |
||||
#endif |
||||
#ifdef CONFIG_SYS_INIT_CHAN2 |
||||
NS16550_reinit (COM_PORTS[1], clock_divisor); |
||||
#endif |
||||
return (0); |
||||
} |
||||
|
||||
static void marvell_serial_putc(const char c) |
||||
{ |
||||
if (c == '\n') |
||||
mpsc_putchar ('\r'); |
||||
|
||||
mpsc_putchar (c); |
||||
} |
||||
|
||||
static int marvell_serial_getc(void) |
||||
{ |
||||
return mpsc_getchar (); |
||||
} |
||||
|
||||
static int marvell_serial_tstc(void) |
||||
{ |
||||
return mpsc_test_char (); |
||||
} |
||||
|
||||
static void marvell_serial_setbrg(void) |
||||
{ |
||||
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate); |
||||
} |
||||
|
||||
#else /* ! CONFIG_MPSC */ |
||||
|
||||
static int marvell_serial_init(void) |
||||
{ |
||||
int clock_divisor = 230400 / gd->baudrate; |
||||
|
||||
#ifdef CONFIG_SYS_INIT_CHAN1 |
||||
(void) NS16550_init (0, clock_divisor); |
||||
#endif |
||||
#ifdef CONFIG_SYS_INIT_CHAN2 |
||||
(void) NS16550_init (1, clock_divisor); |
||||
#endif |
||||
return (0); |
||||
} |
||||
|
||||
static void marvell_serial_putc(const char c) |
||||
{ |
||||
if (c == '\n') |
||||
NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); |
||||
|
||||
NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); |
||||
} |
||||
|
||||
static int marvell_serial_getc(void) |
||||
{ |
||||
return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); |
||||
} |
||||
|
||||
static int marvell_serial_tstc(void) |
||||
{ |
||||
return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); |
||||
} |
||||
|
||||
static void marvell_serial_setbrg(void) |
||||
{ |
||||
int clock_divisor = 230400 / gd->baudrate; |
||||
|
||||
#ifdef CONFIG_SYS_INIT_CHAN1 |
||||
NS16550_reinit (COM_PORTS[0], clock_divisor); |
||||
#endif |
||||
#ifdef CONFIG_SYS_INIT_CHAN2 |
||||
NS16550_reinit (COM_PORTS[1], clock_divisor); |
||||
#endif |
||||
} |
||||
|
||||
#endif /* CONFIG_MPSC */ |
||||
|
||||
static struct serial_device marvell_serial_drv = { |
||||
.name = "marvell_serial", |
||||
.start = marvell_serial_init, |
||||
.stop = NULL, |
||||
.setbrg = marvell_serial_setbrg, |
||||
.putc = marvell_serial_putc, |
||||
.puts = default_serial_puts, |
||||
.getc = marvell_serial_getc, |
||||
.tstc = marvell_serial_tstc, |
||||
}; |
||||
|
||||
void marvell_serial_initialize(void) |
||||
{ |
||||
serial_register(&marvell_serial_drv); |
||||
} |
||||
|
||||
__weak struct serial_device *default_serial_console(void) |
||||
{ |
||||
return &marvell_serial_drv; |
||||
} |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
void kgdb_serial_init (void) |
||||
{ |
||||
} |
||||
|
||||
void putDebugChar (int c) |
||||
{ |
||||
serial_putc (c); |
||||
} |
||||
|
||||
void putDebugStr (const char *str) |
||||
{ |
||||
serial_puts (str); |
||||
} |
||||
|
||||
int getDebugChar (void) |
||||
{ |
||||
return serial_getc (); |
||||
} |
||||
|
||||
void kgdb_interruptible (int yes) |
||||
{ |
||||
return; |
||||
} |
||||
#endif |
||||
@ -1,173 +0,0 @@ |
||||
/* Memory.h - Memory mappings and remapping functions declarations */ |
||||
|
||||
/* Copyright - Galileo technology. */ |
||||
|
||||
#ifndef __INCmemoryh |
||||
#define __INCmemoryh |
||||
|
||||
/* includes */ |
||||
|
||||
#include "core.h" |
||||
|
||||
/* defines */ |
||||
|
||||
#define DONT_MODIFY 0xffffffff |
||||
#define PARITY_SUPPORT 0x40000000 |
||||
#define MINIMUM_MEM_BANK_SIZE 0x10000 |
||||
#define MINIMUM_DEVICE_WINDOW_SIZE 0x10000 |
||||
#define MINIMUM_PCI_WINDOW_SIZE 0x10000 |
||||
#define MINIMUM_ACCESS_WIN_SIZE 0x10000 |
||||
|
||||
#define _8BIT 0x00000000 |
||||
#define _16BIT 0x00100000 |
||||
#define _32BIT 0x00200000 |
||||
#define _64BIT 0x00300000 |
||||
|
||||
/* typedefs */ |
||||
|
||||
typedef struct deviceParam |
||||
{ /* boundary values */ |
||||
unsigned int turnOff; /* 0x0 - 0xf */ |
||||
unsigned int acc2First; /* 0x0 - 0x1f */ |
||||
unsigned int acc2Next; /* 0x0 - 0x1f */ |
||||
unsigned int ale2Wr; /* 0x0 - 0xf */ |
||||
unsigned int wrLow; /* 0x0 - 0xf */ |
||||
unsigned int wrHigh; /* 0x0 - 0xf */ |
||||
unsigned int badrSkew; /* 0x0 - 0x2 */ |
||||
unsigned int DPEn; /* 0x0 - 0x1 */ |
||||
unsigned int deviceWidth; /* in Bytes */ |
||||
} DEVICE_PARAM; |
||||
|
||||
|
||||
typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK; |
||||
typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE; |
||||
|
||||
/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
|
||||
MEM_REGION3,MEM_REGION4,MEM_REGION5, \
|
||||
MEM_REGION6,MEM_REGION7} \
|
||||
MEMORY_PROTECT_REGION;*/ |
||||
/* There are four possible windows that can be defined as protected */ |
||||
typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2, |
||||
MEM_WINDOW3 |
||||
} MEMORY_PROTECT_WINDOW; |
||||
/* When defining a protected window , this paramter indicates whether it
|
||||
is accessible or not */ |
||||
typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
|
||||
MEMORY_ACCESS; |
||||
typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
|
||||
MEMORY_ACCESS_WRITE; |
||||
typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
|
||||
MEMORY_CACHE_PROTECT; |
||||
typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
|
||||
MEMORY_SNOOP_TYPE; |
||||
typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
|
||||
MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
|
||||
MEMORY_SNOOP_REGION; |
||||
|
||||
/* There are 21 memory windows dedicated for the varios interfaces (PCI,
|
||||
devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's |
||||
address decoding mechanism. */ |
||||
typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1, |
||||
CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3, |
||||
DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5, |
||||
DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7, |
||||
BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9, |
||||
PCI_0_MEM0_WINDOW = BIT10, |
||||
PCI_0_MEM1_WINDOW = BIT11, |
||||
PCI_0_MEM2_WINDOW = BIT12, |
||||
PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14, |
||||
PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16, |
||||
PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18, |
||||
INTEGRATED_SRAM_WINDOW = BIT19, |
||||
INTERNAL_SPACE_WINDOW = BIT20, |
||||
ALL_WINDOWS = 0X1FFFFF |
||||
} MEMORY_WINDOW; |
||||
|
||||
typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED |
||||
} MEMORY_WINDOW_STATUS; |
||||
|
||||
|
||||
typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3 |
||||
#ifdef INCLUDE_PCI_1 |
||||
,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3 |
||||
#endif /* INCLUDE_PCI_1 */ |
||||
} PCI_MEM_WINDOW; |
||||
|
||||
|
||||
/* -------------------------------------------------------------------------------------------------*/ |
||||
|
||||
/* functions */ |
||||
unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank); |
||||
unsigned int memoryGetDeviceBaseAddress(DEVICE device); |
||||
/* New at MV6436x */ |
||||
unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow); |
||||
unsigned int memoryGetBankSize(MEMORY_BANK bank); |
||||
unsigned int memoryGetDeviceSize(DEVICE device); |
||||
unsigned int memoryGetDeviceWidth(DEVICE device); |
||||
/* New at MV6436x */ |
||||
unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow); |
||||
|
||||
/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/ |
||||
bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength); |
||||
/* Set a new base and size for one of the memory banks (CS0 - CS3) */ |
||||
bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase, |
||||
unsigned int bankSize); |
||||
bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength); |
||||
|
||||
/* Change the Internal Register Base Address to a new given Address. */ |
||||
bool memoryMapInternalRegistersSpace(unsigned int internalRegBase); |
||||
/* returns internal Register Space Base Address. */ |
||||
unsigned int memoryGetInternalRegistersSpace(void); |
||||
|
||||
/* Returns the integrated SRAM Base Address. */ |
||||
unsigned int memoryGetInternalSramBaseAddr(void); |
||||
/* -------------------------------------------------------------------------------------------------*/ |
||||
|
||||
/* Set new base address for the integrated SRAM. */ |
||||
void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress); |
||||
/* -------------------------------------------------------------------------------------------------*/ |
||||
|
||||
/* Delete a protection feature to a given space. */ |
||||
void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window); |
||||
/* -------------------------------------------------------------------------------------------------*/ |
||||
|
||||
/* Writes a new remap value to the remap register */ |
||||
unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow, |
||||
unsigned int remapValueHigh, |
||||
unsigned int remapValueLow); |
||||
/* -------------------------------------------------------------------------------------------------*/ |
||||
|
||||
/* Configurate the protection feature to a given space. */ |
||||
bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window, |
||||
MEMORY_ACCESS gtMemoryAccess, |
||||
MEMORY_ACCESS_WRITE gtMemoryWrite, |
||||
MEMORY_CACHE_PROTECT cacheProtection, |
||||
unsigned int baseAddress, |
||||
unsigned int size); |
||||
|
||||
/* Configurate the protection feature to a given space. */ |
||||
/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
|
||||
MEMORY_ACCESS memoryAccess, |
||||
MEMORY_ACCESS_WRITE memoryWrite, |
||||
MEMORY_CACHE_PROTECT cacheProtection, |
||||
unsigned int baseAddress, |
||||
unsigned int regionLength); */ |
||||
/* Configurate the snoop feature to a given space. */ |
||||
bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region, |
||||
MEMORY_SNOOP_TYPE snoopType, |
||||
unsigned int baseAddress, |
||||
unsigned int regionLength); |
||||
|
||||
bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue); |
||||
bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); |
||||
bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum); |
||||
/* Set a new base and size for one of the PCI windows. */ |
||||
bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, |
||||
unsigned int pciWindowSize); |
||||
|
||||
/* Disable or enable one of the 21 windows dedicated for the CPU's
|
||||
address decoding mechanism */ |
||||
void MemoryDisableWindow(MEMORY_WINDOW window); |
||||
void MemoryEnableWindow (MEMORY_WINDOW window); |
||||
MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window); |
||||
#endif /* __INCmemoryh */ |
||||
@ -1,293 +0,0 @@ |
||||
/* PCI.h - PCI functions header file */ |
||||
|
||||
/* Copyright - Galileo technology. */ |
||||
|
||||
#ifndef __INCpcih |
||||
#define __INCpcih |
||||
|
||||
/* includes */ |
||||
|
||||
#include "core.h" |
||||
#include "memory.h" |
||||
|
||||
/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */ |
||||
#define PCI_MAX_DEVICES 22 |
||||
|
||||
|
||||
/* Macros */ |
||||
|
||||
/* The next Macros configurate the initiator board (SELF) or any any agent on
|
||||
the PCI to become: MASTER, response to MEMORY transactions , response to |
||||
IO transactions or TWO both MEMORY_IO transactions. Those configuration |
||||
are for both PCI0 and PCI1. */ |
||||
|
||||
#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ |
||||
PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | \
|
||||
pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) |
||||
|
||||
#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ |
||||
PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE | \
|
||||
pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) |
||||
|
||||
#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host, \ |
||||
PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE | \
|
||||
pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) ) |
||||
|
||||
#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host, \ |
||||
PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8 & \
|
||||
pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber)) |
||||
|
||||
#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host, \ |
||||
PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE | \
|
||||
pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) |
||||
|
||||
#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host, \ |
||||
PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE & \
|
||||
pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) ) |
||||
|
||||
#define MASTER_ENABLE BIT2 |
||||
#define MEMORY_ENABLE BIT1 |
||||
#define I_O_ENABLE BIT0 |
||||
#define SELF 32 |
||||
|
||||
/* Agent on the PCI bus may have up to 6 BARS. */ |
||||
#define BAR0 0x10 |
||||
#define BAR1 0x14 |
||||
#define BAR2 0x18 |
||||
#define BAR3 0x1c |
||||
#define BAR4 0x20 |
||||
#define BAR5 0x24 |
||||
#define BAR_SEL_MEM_IO BIT0 |
||||
#define BAR_MEM_TYPE_32_BIT NO_BIT |
||||
#define BAR_MEM_TYPE_BELOW_1M BIT1 |
||||
#define BAR_MEM_TYPE_64_BIT BIT2 |
||||
#define BAR_MEM_TYPE_RESERVED (BIT1 | BIT2) |
||||
#define BAR_MEM_TYPE_MASK (BIT1 | BIT2) |
||||
#define BAR_PREFETCHABLE BIT3 |
||||
#define BAR_CONFIG_MASK (BIT0 | BIT1 | BIT2 | BIT3) |
||||
|
||||
/* Defines for the access regions. */ |
||||
#define PREFETCH_ENABLE BIT12 |
||||
#define PREFETCH_DISABLE NO_BIT |
||||
#define DELAYED_READ_ENABLE BIT13 |
||||
/* #define CACHING_ENABLE BIT14 */ |
||||
/* aggressive prefetch: PCI slave prefetch two burst in advance*/ |
||||
#define AGGRESSIVE_PREFETCH BIT16 |
||||
/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/ |
||||
#define READ_LINE_AGGRESSIVE_PREFETCH BIT17 |
||||
/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/ |
||||
#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18 |
||||
#define MAX_BURST_4 NO_BIT |
||||
#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */ |
||||
#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */ |
||||
#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */ |
||||
#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */ |
||||
#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */ |
||||
#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */ |
||||
#define PCI_ACCESS_PROTECT BIT28 |
||||
#define PCI_WRITE_PROTECT BIT29 |
||||
|
||||
/* typedefs */ |
||||
|
||||
typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5, |
||||
REGION6,REGION7} PCI_ACCESS_REGIONS; |
||||
|
||||
typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO; |
||||
typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK; |
||||
|
||||
typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB} |
||||
PCI_SNOOP_TYPE; |
||||
typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1, |
||||
PCI_SNOOP_REGION2,PCI_SNOOP_REGION3} |
||||
PCI_SNOOP_REGION; |
||||
|
||||
typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST; |
||||
typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1, |
||||
PCI_REGION2,PCI_REGION3, |
||||
PCI_IO} |
||||
PCI_REGION; |
||||
|
||||
/*ronen 7/Dec/03 */ |
||||
typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR, |
||||
PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR, |
||||
PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR, |
||||
PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR, |
||||
PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR, |
||||
PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR, |
||||
PCI_LAST_BAR} PCI_INTERNAL_BAR; |
||||
|
||||
typedef struct pciBar { |
||||
unsigned int detectBase; |
||||
unsigned int base; |
||||
unsigned int size; |
||||
unsigned int type; |
||||
} PCI_BAR; |
||||
|
||||
typedef struct pciDevice { |
||||
PCI_HOST host; |
||||
char type[40]; |
||||
unsigned int deviceNum; |
||||
unsigned int venID; |
||||
unsigned int deviceID; |
||||
PCI_BAR bar[6]; |
||||
} PCI_DEVICE; |
||||
|
||||
typedef struct pciSelfBars { |
||||
unsigned int SCS0Base; |
||||
unsigned int SCS0Size; |
||||
unsigned int SCS1Base; |
||||
unsigned int SCS1Size; |
||||
unsigned int SCS2Base; |
||||
unsigned int SCS2Size; |
||||
unsigned int SCS3Base; |
||||
unsigned int SCS3Size; |
||||
unsigned int internalMemBase; |
||||
unsigned int internalIOBase; |
||||
unsigned int CS0Base; |
||||
unsigned int CS0Size; |
||||
unsigned int CS1Base; |
||||
unsigned int CS1Size; |
||||
unsigned int CS2Base; |
||||
unsigned int CS2Size; |
||||
unsigned int CS3Base; |
||||
unsigned int CS3Size; |
||||
unsigned int CSBootBase; |
||||
unsigned int CSBootSize; |
||||
unsigned int P2PMem0Base; |
||||
unsigned int P2PMem0Size; |
||||
unsigned int P2PMem1Base; |
||||
unsigned int P2PMem1Size; |
||||
unsigned int P2PIOBase; |
||||
unsigned int P2PIOSize; |
||||
unsigned int CPUBase; |
||||
unsigned int CPUSize; |
||||
} PCI_SELF_BARS; |
||||
|
||||
/* read/write configuration registers on local PCI bus. */ |
||||
void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset, |
||||
unsigned int pciDevNum, unsigned int data); |
||||
unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, |
||||
unsigned int pciDevNum); |
||||
|
||||
/* read/write configuration registers on another PCI bus. */ |
||||
void pciOverBridgeWriteConfigReg(PCI_HOST host, |
||||
unsigned int regOffset, |
||||
unsigned int pciDevNum, |
||||
unsigned int busNum,unsigned int data); |
||||
unsigned int pciOverBridgeReadConfigReg(PCI_HOST host, |
||||
unsigned int regOffset, |
||||
unsigned int pciDevNum, |
||||
unsigned int busNum); |
||||
|
||||
/* Performs full scane on both PCI and returns all detail possible on the
|
||||
agents which exist on the bus. */ |
||||
void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect, |
||||
unsigned int numberOfElment); |
||||
|
||||
/* Master`s memory space */ |
||||
bool pciMapSpace(PCI_HOST host, PCI_REGION region, |
||||
unsigned int remapBase, |
||||
unsigned int deviceBase, |
||||
unsigned int deviceLength); |
||||
unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region); |
||||
unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region); |
||||
|
||||
/* Slave`s memory space */ |
||||
void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, |
||||
unsigned int pci0Dram0Base, unsigned int pci0Dram0Size); |
||||
|
||||
#if 0 /* GARBAGE routines - dont use till they get cleaned up */
|
||||
void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars); |
||||
void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars); |
||||
void pci0MapInternalRegSpace(unsigned int pci0InternalBase); |
||||
void pci1MapInternalRegSpace(unsigned int pci1InternalBase); |
||||
void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase); |
||||
void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase); |
||||
void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base, |
||||
unsigned int pci0Dev0Length); |
||||
void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base, |
||||
unsigned int pci1Dev0Length); |
||||
void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base, |
||||
unsigned int pci0Dev1Length); |
||||
void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base, |
||||
unsigned int pci1Dev1Length); |
||||
void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base, |
||||
unsigned int pci0Dev2Length); |
||||
void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base, |
||||
unsigned int pci1Dev2Length); |
||||
void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base, |
||||
unsigned int pci0Dev3Length); |
||||
void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base, |
||||
unsigned int pci1Dev3Length); |
||||
void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase, |
||||
unsigned int pci0DevBootLength); |
||||
void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase, |
||||
unsigned int pci1DevBootLength); |
||||
void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base, |
||||
unsigned int pci0P2pMem0Length); |
||||
void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base, |
||||
unsigned int pci1P2pMem0Length); |
||||
void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base, |
||||
unsigned int pci0P2pMem1Length); |
||||
void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base, |
||||
unsigned int pci1P2pMem1Length); |
||||
void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase, |
||||
unsigned int pci0P2pIoLength); |
||||
void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase, |
||||
unsigned int pci1P2pIoLength); |
||||
|
||||
void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs); |
||||
void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs); |
||||
#endif |
||||
|
||||
/* PCI region options */ |
||||
|
||||
bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region, |
||||
unsigned int features, unsigned int baseAddress, |
||||
unsigned int regionLength); |
||||
|
||||
void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region); |
||||
|
||||
/* PCI arbiter */ |
||||
|
||||
bool pciArbiterEnable(PCI_HOST host); |
||||
bool pciArbiterDisable(PCI_HOST host); |
||||
bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, |
||||
PCI_AGENT_PRIO externalAgent0, |
||||
PCI_AGENT_PRIO externalAgent1, |
||||
PCI_AGENT_PRIO externalAgent2, |
||||
PCI_AGENT_PRIO externalAgent3, |
||||
PCI_AGENT_PRIO externalAgent4, |
||||
PCI_AGENT_PRIO externalAgent5); |
||||
bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent, |
||||
PCI_AGENT_PRIO externalAgent0, |
||||
PCI_AGENT_PRIO externalAgent1, |
||||
PCI_AGENT_PRIO externalAgent2, |
||||
PCI_AGENT_PRIO externalAgent3, |
||||
PCI_AGENT_PRIO externalAgent4, |
||||
PCI_AGENT_PRIO externalAgent5); |
||||
bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent, |
||||
PCI_AGENT_PARK externalAgent0, |
||||
PCI_AGENT_PARK externalAgent1, |
||||
PCI_AGENT_PARK externalAgent2, |
||||
PCI_AGENT_PARK externalAgent3, |
||||
PCI_AGENT_PARK externalAgent4, |
||||
PCI_AGENT_PARK externalAgent5); |
||||
bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); |
||||
bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue); |
||||
|
||||
/* PCI-to-PCI (P2P) */ |
||||
|
||||
bool pciP2PConfig(PCI_HOST host, |
||||
unsigned int SecondBusLow,unsigned int SecondBusHigh, |
||||
unsigned int busNum,unsigned int devNum); |
||||
/* PCI Cache-coherency */ |
||||
|
||||
bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region, |
||||
PCI_SNOOP_TYPE snoopType, |
||||
unsigned int baseAddress, |
||||
unsigned int regionLength); |
||||
|
||||
PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev); |
||||
|
||||
#endif /* __INCpcih */ |
||||
Loading…
Reference in new issue