This patch adds support for CM-T35 board Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>master
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS := cm_t35.o
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean: |
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rm -f $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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/*
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* (C) Copyright 2010 |
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* CompuLab, Ltd. <www.compulab.co.il> |
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* |
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* Author: Mike Rapoport <mike@compulab.co.il> |
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* |
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* Derived from omap3evm and Beagle Board by |
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* Manikandan Pillai <mani.pillai@ti.com> |
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* Richard Woodruff <r-woodruff2@ti.com> |
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* Syed Mohammed Khasim <x0khasim@ti.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <net.h> |
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#include <i2c.h> |
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#include <twl4030.h> |
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#include <asm/io.h> |
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#include <asm/arch/mem.h> |
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#include <asm/arch/mux.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/mach-types.h> |
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const omap3_sysinfo sysinfo = { |
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DDR_DISCRETE, |
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"CM-T35 board", |
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"NAND", |
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}; |
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static u32 gpmc_net_config[GPMC_MAX_REG] = { |
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NET_GPMC_CONFIG1, |
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NET_GPMC_CONFIG2, |
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NET_GPMC_CONFIG3, |
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NET_GPMC_CONFIG4, |
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NET_GPMC_CONFIG5, |
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NET_GPMC_CONFIG6, |
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0 |
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}; |
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static u32 gpmc_nand_config[GPMC_MAX_REG] = { |
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SMNAND_GPMC_CONFIG1, |
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SMNAND_GPMC_CONFIG2, |
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SMNAND_GPMC_CONFIG3, |
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SMNAND_GPMC_CONFIG4, |
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SMNAND_GPMC_CONFIG5, |
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SMNAND_GPMC_CONFIG6, |
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0, |
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}; |
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/*
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* Routine: board_init |
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* Description: Early hardware init. |
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*/ |
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int board_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ |
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enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0], |
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CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M); |
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/* board id for Linux */ |
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gd->bd->bi_arch_number = MACH_TYPE_CM_T35; |
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/* boot param addr */ |
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); |
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return 0; |
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} |
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/*
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* Routine: misc_init_r |
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* Description: Init I2C and display die ID |
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*/ |
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int misc_init_r(void) |
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{ |
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C |
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
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#endif |
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dieid_num_r(); |
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return 0; |
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} |
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/*
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* Routine: set_muxconf_regs |
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* Description: Setting up the configuration Mux registers specific to the |
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* hardware. Many pins need to be moved from protect to primary |
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* mode. |
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*/ |
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void set_muxconf_regs(void) |
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{ |
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/* SDRC */ |
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MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/ |
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MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/ |
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MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/ |
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MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/ |
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MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/ |
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MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/ |
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MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/ |
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MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/ |
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MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/ |
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MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/ |
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MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/ |
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MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/ |
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MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/ |
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MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/ |
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MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/ |
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MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/ |
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MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/ |
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MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/ |
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MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/ |
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MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/ |
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MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/ |
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MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/ |
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MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/ |
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MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/ |
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MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/ |
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MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/ |
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MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/ |
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MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/ |
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MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/ |
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MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/ |
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MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/ |
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MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/ |
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MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/ |
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MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/ |
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MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/ |
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MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/ |
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MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/ |
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MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ |
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MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ |
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/* GPMC */ |
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ |
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ |
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ |
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ |
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ |
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ |
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ |
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ |
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ |
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/ |
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/ |
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/ |
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/ |
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/ |
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/ |
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/ |
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/ |
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/ |
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/ |
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/ |
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/ |
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/ |
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/ |
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/ |
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/ |
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/ |
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/ |
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/* SB-T35 Ethernet */ |
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MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/ |
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/* CM-T35 Ethernet */ |
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ |
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MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ |
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/ |
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/ |
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/ |
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/ |
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MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/ |
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/ |
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/ |
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/* DSS */ |
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MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/ |
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MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/ |
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MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/ |
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MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/ |
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MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/ |
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MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/ |
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MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/ |
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MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/ |
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MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/ |
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MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/ |
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MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/ |
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MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/ |
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MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/ |
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MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/ |
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MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/ |
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MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/ |
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MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/ |
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MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/ |
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MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/ |
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MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/ |
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MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/ |
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MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/ |
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MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/ |
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MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/ |
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MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/ |
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MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/ |
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MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/ |
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MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/ |
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/* serial interface */ |
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/ |
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/ |
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/* mUSB */ |
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MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/ |
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MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/ |
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MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/ |
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MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/ |
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MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/ |
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MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/ |
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MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/ |
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MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/ |
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MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/ |
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/ |
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MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ |
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MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ |
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/* I2C1 */ |
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MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ |
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MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ |
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/* control and debug */ |
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MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ |
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MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/ |
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MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/ |
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MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/ |
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MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/ |
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MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)); /*green LED*/ |
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MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/ |
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MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/ |
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MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/ |
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MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/ |
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} |
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#ifdef CONFIG_GENERIC_MMC |
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int board_mmc_init(bd_t *bis) |
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{ |
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return omap_mmc_init(0); |
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} |
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#endif |
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/*
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* Routine: setup_net_chip_gmpc |
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* Description: Setting up the configuration GPMC registers specific to the |
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* Ethernet hardware. |
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*/ |
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static void setup_net_chip_gmpc(void) |
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{ |
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struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; |
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enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], |
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CM_T35_SMC911X_BASE, GPMC_SIZE_16M); |
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enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], |
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SB_T35_SMC911X_BASE, GPMC_SIZE_16M); |
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/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ |
||||
writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); |
||||
|
||||
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ |
||||
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); |
||||
|
||||
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ |
||||
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, |
||||
&ctrl_base->gpmc_nadv_ale); |
||||
} |
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C |
||||
/*
|
||||
* Routine: reset_net_chip |
||||
* Description: reset the Ethernet controller via TPS65930 GPIO |
||||
*/ |
||||
static void reset_net_chip(void) |
||||
{ |
||||
/* Set GPIO1 of TPS65930 as output */ |
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, |
||||
TWL4030_BASEADD_GPIO+0x03); |
||||
/* Send a pulse on the GPIO pin */ |
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, |
||||
TWL4030_BASEADD_GPIO+0x0C); |
||||
udelay(1); |
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, |
||||
TWL4030_BASEADD_GPIO+0x09); |
||||
udelay(1); |
||||
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0x02, |
||||
TWL4030_BASEADD_GPIO+0x0C); |
||||
} |
||||
#else |
||||
static inline void reset_net_chip(void) {} |
||||
#endif |
||||
|
||||
/*
|
||||
* Routine: handle_mac_address |
||||
* Description: prepare MAC address for on-board Ethernet. |
||||
*/ |
||||
static int handle_mac_address(void) |
||||
{ |
||||
unsigned char enetaddr[6]; |
||||
int rc; |
||||
|
||||
rc = eth_getenv_enetaddr("ethaddr", enetaddr); |
||||
if (rc) |
||||
return 0; |
||||
|
||||
#ifdef CONFIG_DRIVER_OMAP34XX_I2C |
||||
rc = i2c_read(0x50, 0, 1, enetaddr, 6); |
||||
if (rc) |
||||
return rc; |
||||
#endif |
||||
|
||||
if (!is_valid_ether_addr(enetaddr)) |
||||
return -1; |
||||
|
||||
return eth_setenv_enetaddr("ethaddr", enetaddr); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Routine: board_eth_init |
||||
* Description: initialize module and base-board Ethernet chips |
||||
*/ |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = 0, rc1 = 0; |
||||
|
||||
#ifdef CONFIG_SMC911X |
||||
setup_net_chip_gmpc(); |
||||
reset_net_chip(); |
||||
|
||||
rc1 = handle_mac_address(); |
||||
if (rc1) |
||||
printf("CM-T35: No MAC address found\n"); |
||||
|
||||
rc1 = smc911x_initialize(0, CM_T35_SMC911X_BASE); |
||||
if (rc1 > 0) |
||||
rc++; |
||||
|
||||
rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); |
||||
if (rc1 > 0) |
||||
rc++; |
||||
#endif |
||||
|
||||
return rc; |
||||
} |
@ -0,0 +1,352 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* CompuLab, Ltd. |
||||
* Mike Rapoport <mike@compulab.co.il> |
||||
* |
||||
* Based on omap3_beagle.h |
||||
* (C) Copyright 2006-2008 |
||||
* Texas Instruments. |
||||
* Richard Woodruff <r-woodruff2@ti.com> |
||||
* Syed Mohammed Khasim <x0khasim@ti.com> |
||||
* |
||||
* Configuration settings for the CompuLab CM-T35 board |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP34XX 1 /* which is a 34XX */ |
||||
#define CONFIG_OMAP3430 1 /* which is in a 3430 */ |
||||
#define CONFIG_CM_T35 1 /* working with CM-T35 */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x80008000 |
||||
|
||||
#define CONFIG_SDRC /* The chip has SDRC controller */ |
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */ |
||||
#include <asm/arch/omap3.h> |
||||
|
||||
/*
|
||||
* Display CPU and Board information |
||||
*/ |
||||
#define CONFIG_DISPLAY_CPUINFO 1 |
||||
#define CONFIG_DISPLAY_BOARDINFO 1 |
||||
|
||||
/* Clock Defines */ |
||||
#define V_OSCK 26000000 /* Clock output from T2 */ |
||||
#define V_SCLK (V_OSCK >> 1) |
||||
|
||||
#undef CONFIG_USE_IRQ /* no support for IRQs */ |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_OF_LIBFDT 1 |
||||
/*
|
||||
* The early kernel mapping on ARM currently only maps from the base of DRAM |
||||
* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. |
||||
* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, |
||||
* so that leaves DRAM base to DRAM base + 0x4000 available. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ 0x4000 |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
#define CONFIG_REVISION_TAG 1 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
||||
/* Sector */ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
||||
/* initial data */ |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
||||
|
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 3 |
||||
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
||||
#define CONFIG_SERIAL3 3 /* UART3 */ |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
||||
115200} |
||||
#define CONFIG_GENERIC_MMC 1 |
||||
#define CONFIG_MMC 1 |
||||
#define CONFIG_OMAP_HSMMC 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
/* DDR - I use Micron DDR */ |
||||
#define CONFIG_OMAP3_MICRON_DDR 1 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_MUSB_UDC 1 |
||||
#define CONFIG_USB_OMAP3 1 |
||||
#define CONFIG_TWL4030_USB 1 |
||||
|
||||
/* USB device configuration */ |
||||
#define CONFIG_USB_DEVICE 1 |
||||
#define CONFIG_USB_TTY 1 |
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
||||
|
||||
/* commands to include */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_EXT2 /* EXT2 Support */ |
||||
#define CONFIG_CMD_FAT /* FAT support */ |
||||
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ |
||||
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
||||
#define MTDIDS_DEFAULT "nand0=nand" |
||||
#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ |
||||
"1920k(u-boot),128k(u-boot-env),"\
|
||||
"4m(kernel),-(fs)" |
||||
|
||||
#define CONFIG_CMD_I2C /* I2C serial bus support */ |
||||
#define CONFIG_CMD_MMC /* MMC support */ |
||||
#define CONFIG_CMD_NAND /* NAND support */ |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_PING |
||||
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ |
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ |
||||
#undef CONFIG_CMD_IMLS /* List all found images */ |
||||
|
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_SYS_I2C_SLAVE 1 |
||||
#define CONFIG_SYS_I2C_BUS 0 |
||||
#define CONFIG_SYS_I2C_BUS_SELECT 1 |
||||
#define CONFIG_DRIVER_OMAP34XX_I2C 1 |
||||
|
||||
/*
|
||||
* TWL4030 |
||||
*/ |
||||
#define CONFIG_TWL4030_POWER 1 |
||||
#define CONFIG_TWL4030_LED 1 |
||||
|
||||
/*
|
||||
* Board NAND Info. |
||||
*/ |
||||
#define CONFIG_SYS_NAND_QUIET_TEST 1 |
||||
#define CONFIG_NAND_OMAP_GPMC |
||||
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
||||
/* to access nand */ |
||||
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ |
||||
/* to access nand at */ |
||||
/* CS0 */ |
||||
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 |
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
||||
/* devices */ |
||||
#define CONFIG_JFFS2_NAND |
||||
/* nand device jffs2 lives on */ |
||||
#define CONFIG_JFFS2_DEV "nand0" |
||||
/* start of jffs2 partition */ |
||||
#define CONFIG_JFFS2_PART_OFFSET 0x680000 |
||||
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ |
||||
/* partition */ |
||||
|
||||
/* Environment information */ |
||||
#define CONFIG_BOOTDELAY 10 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"loadaddr=0x82000000\0" \
|
||||
"usbtty=cdc_acm\0" \
|
||||
"console=ttyS2,115200n8\0" \
|
||||
"mpurate=500\0" \
|
||||
"vram=12M\0" \
|
||||
"dvimode=1024x768MR-16@60\0" \
|
||||
"defaultdisplay=dvi\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||
"mmcrootfstype=ext3 rootwait\0" \
|
||||
"nandroot=/dev/mtdblock4 rw\0" \
|
||||
"nandrootfstype=jffs2\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"mpurate=${mpurate} " \
|
||||
"vram=${vram} " \
|
||||
"omapfb.mode=dvi:${dvimode} " \
|
||||
"omapfb.debug=y " \
|
||||
"omapdss.def_disp=${defaultdisplay} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"mpurate=${mpurate} " \
|
||||
"vram=${vram} " \
|
||||
"omapfb.mode=dvi:${dvimode} " \
|
||||
"omapfb.debug=y " \
|
||||
"omapdss.def_disp=${defaultdisplay} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source ${loadaddr}\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${loadaddr} 280000 400000; " \
|
||||
"bootm ${loadaddr}\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"if mmc rescan ${mmcdev}; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run nandboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run nandboot; fi" |
||||
|
||||
#define CONFIG_AUTO_COMPLETE 1 |
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_SYS_PROMPT "CM-T35 # " |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
||||
sizeof(CONFIG_SYS_PROMPT) + 16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
/* Boot Argument Buffer Size */ |
||||
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ |
||||
/* works on */ |
||||
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ |
||||
0x01F00000) /* 31MB */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ |
||||
/* load address */ |
||||
|
||||
/*
|
||||
* OMAP3 has 12 GP timers, they can be driven by the system clock |
||||
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). |
||||
* This rate is divided by a local divisor. |
||||
*/ |
||||
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) |
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ |
||||
#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ |
||||
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 |
||||
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ |
||||
|
||||
/* SDRAM Bank Allocation method */ |
||||
#define SDRC_R_B_C 1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
/* **** PISMO SUPPORT *** */ |
||||
|
||||
/* Configure the PISMO */ |
||||
#define PISMO1_NAND_SIZE GPMC_SIZE_128M |
||||
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE boot_flash_base |
||||
|
||||
/* Monitor at start of flash */ |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP |
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND 1 |
||||
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
||||
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
||||
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec |
||||
#define CONFIG_ENV_OFFSET boot_flash_off |
||||
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned int boot_flash_base; |
||||
extern volatile unsigned int boot_flash_env_addr; |
||||
extern unsigned int boot_flash_off; |
||||
extern unsigned int boot_flash_sec; |
||||
extern unsigned int boot_flash_type; |
||||
#endif |
||||
|
||||
#if defined(CONFIG_CMD_NET) |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_SMC911X |
||||
#define CONFIG_SMC911X_32_BIT |
||||
#define CM_T35_SMC911X_BASE 0x2C000000 |
||||
#define SB_T35_SMC911X_BASE (CM_T35_SMC911X_BASE + (16 << 20)) |
||||
#define CONFIG_SMC911X_BASE CM_T35_SMC911X_BASE |
||||
#endif /* (CONFIG_CMD_NET) */ |
||||
|
||||
/* additions for new relocation code, must be added to all boards */ |
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800 |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue