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ppc4xx: remove CPCIISER4 board

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Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
master
Matthias Fuchs 11 years ago committed by Tom Rini
parent 2404124c47
commit 3705726010
10 changed files with 0 additions and 4667 deletions
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  1. 4
      arch/powerpc/cpu/ppc4xx/Kconfig
  2. 12
      board/esd/cpciiser4/Kconfig
  3. 6
      board/esd/cpciiser4/MAINTAINERS
  4. 8
      board/esd/cpciiser4/Makefile
  5. 165
      board/esd/cpciiser4/cpciiser4.c
  6. 28
      board/esd/cpciiser4/cpciiser4.h
  7. 68
      board/esd/cpciiser4/flash.c
  8. 4136
      board/esd/cpciiser4/fpgadata.c
  9. 3
      configs/CPCIISER4_defconfig
  10. 237
      include/configs/CPCIISER4.h

4
arch/powerpc/cpu/ppc4xx/Kconfig
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@ -125,9 +125,6 @@ config TARGET_CPCI405AB
config TARGET_CPCI405DT config TARGET_CPCI405DT
bool "Support CPCI405DT" bool "Support CPCI405DT"
config TARGET_CPCIISER4
bool "Support CPCIISER4"
config TARGET_DP405 config TARGET_DP405
bool "Support DP405" bool "Support DP405"
@ -247,7 +244,6 @@ source "board/csb472/Kconfig"
source "board/dave/PPChameleonEVB/Kconfig" source "board/dave/PPChameleonEVB/Kconfig"
source "board/esd/cpci2dp/Kconfig" source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig" source "board/esd/cpci405/Kconfig"
source "board/esd/cpciiser4/Kconfig"
source "board/esd/dp405/Kconfig" source "board/esd/dp405/Kconfig"
source "board/esd/du405/Kconfig" source "board/esd/du405/Kconfig"
source "board/esd/du440/Kconfig" source "board/esd/du440/Kconfig"

12
board/esd/cpciiser4/Kconfig
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@ -1,12 +0,0 @@
if TARGET_CPCIISER4
config SYS_BOARD
default "cpciiser4"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "CPCIISER4"
endif

6
board/esd/cpciiser4/MAINTAINERS
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@ -1,6 +0,0 @@
CPCIISER4 BOARD
M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
S: Maintained
F: board/esd/cpciiser4/
F: include/configs/CPCIISER4.h
F: configs/CPCIISER4_defconfig

8
board/esd/cpciiser4/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = cpciiser4.o flash.o ../common/misc.o

165
board/esd/cpciiser4/cpciiser4.c
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@ -1,165 +0,0 @@
/*
* (C) Copyright 2000
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "cpciiser4.h"
#include <asm/processor.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
extern void lxt971_no_sleep(void);
/* ------------------------------------------------------------------------- */
#if 0
#define FPGA_DEBUG
#endif
#if 0
#define FPGA_DEBUG2
#endif
/* fpga configuration data - generated by bin2cc */
const unsigned char fpgadata[] = {
#include "fpgadata.c"
};
/*
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
int board_early_init_f (void)
{
int index, len, i;
int status;
#ifdef FPGA_DEBUG
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
serial_init ();
console_init_f ();
#endif
/*
* Boot onboard FPGA
*/
status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
if (status != 0) {
/* booting FPGA failed */
#ifndef FPGA_DEBUG
/* set up serial port with default baudrate */
(void) get_clocks ();
gd->baudrate = CONFIG_BAUDRATE;
serial_init ();
console_init_f ();
#endif
printf ("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
printf ("(Timeout: DONE not high after programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = fpgadata[index];
printf ("FPGA: %s\n", &(fpgadata[index + 1]));
index += len + 3;
}
putc ('\n');
/* delayed reboot */
for (i = 20; i > 0; i--) {
printf ("Rebooting in %2d seconds \r", i);
for (index = 0; index < 1000; index++)
udelay (1000);
}
putc ('\n');
do_reset (NULL, 0, 0, NULL);
}
/*
* Init FPGA via RESET (read access on CS3)
*/
in_8((void *)0xf0200000);
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
* IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr (UIC0ER, 0x00000000); /* disable all ints */
mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */
/* mtdcr(UIC0PR, 0xFFFFFF81); / set int polarities */
mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
int index;
int len;
char str[64];
int i = getenv_f("serial#", str, sizeof (str));
puts ("Board: ");
if (i == -1) {
puts ("### No HW ID - assuming AR405");
} else {
puts(str);
}
puts ("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
for (i = 0; i < 4; i++) {
len = fpgadata[index];
printf ("%s ", &(fpgadata[index + 1]));
index += len + 3;
}
putc ('\n');
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
return 0;
}

28
board/esd/cpciiser4/cpciiser4.h
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@ -1,28 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/****************************************************************************
* FLASH Memory Map as used by TQ Monitor:
*
* Start Address Length
* +-----------------------+ 0x4000_0000 Start of Flash -----------------
* | MON8xx code | 0x4000_0100 Reset Vector
* +-----------------------+ 0x400?_????
* | (unused) |
* +-----------------------+ 0x4001_FF00
* | Ethernet Addresses | 0x78
* +-----------------------+ 0x4001_FF78
* | (Reserved for MON8xx) | 0x44
* +-----------------------+ 0x4001_FFBC
* | Lock Address | 0x04
* +-----------------------+ 0x4001_FFC0 ^
* | Hardware Information | 0x40 | MON8xx
* +=======================+ 0x4002_0000 (sector border) -----------------
* | Autostart Header | | Applications
* | ... | v
*
*****************************************************************************/

68
board/esd/cpciiser4/flash.c
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@ -1,68 +0,0 @@
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
/*
* include common flash code (for esd boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0;
int i;
uint pbcr;
unsigned long base_b0;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
}
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-monitor_flash_len,
0xffffffff,
&flash_info[0]);
flash_info[0].size = size_b0;
return (size_b0);
}

4136
board/esd/cpciiser4/fpgadata.c
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File diff suppressed because it is too large Load Diff

3
configs/CPCIISER4_defconfig
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@ -1,3 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_CPCIISER4=y

237
include/configs/CPCIISER4.h
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@ -1,237 +0,0 @@
/*
* (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND "bootm fff00000"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */
#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
/* total size of a CAT24WC08 is 1024 bytes */
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (Uart 8bit) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */
#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 2 (Uart 32bit) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
#define CONFIG_SYS_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
/* Memory Bank 3 (FPGA Reset) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */
#define CONFIG_SYS_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#endif /* __CONFIG_H */
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