From c9974ab0a4d3731cdb76a7599d9fe9445d764d60 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 4 Jan 2008 11:58:23 -0600 Subject: [PATCH 1/4] 8610: Fix lingering compile warnings. Turn off DEBUG. Signed-off-by: Jon Loeliger --- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 617881a..9f32890 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -19,13 +19,14 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#define DEBUG + #include #include #include #include #include #include +#include #include #include @@ -47,6 +48,8 @@ extern void ddr_enable_ecc(unsigned int dram_size); void sdram_init(void); long int fixed_sdram(void); +void mpc8610hpcd_diu_init(void); + /* called before any console output */ int board_early_init_f(void) From 1df170f8b2a99e1e2f940f9f0b56511e1e4c9e1f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Fri, 4 Jan 2008 12:07:27 -0600 Subject: [PATCH 2/4] Convert MPC8610HPCD to use libfdt. Assumes the presence of the aliases node in the DTS to locate the pci and serial nodes for fixups. Use consistent fdtaddr and fdtfile in environment variables. Signed-off-by: Jon Loeliger --- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 73 +++++++++++++++++-------------- include/configs/MPC8610HPCD.h | 31 ++++++------- 2 files changed, 54 insertions(+), 50 deletions(-) diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 9f32890..264e959 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -29,12 +29,8 @@ #include #include #include - - -#if defined(CONFIG_OF_FLAT_TREE) -#include -extern void ft_cpu_setup(void *blob, bd_t *bd); -#endif +#include +#include #include "../common/pixis.h" @@ -459,46 +455,57 @@ void pci_init_board(void) #endif /* CONFIG_PCI1 */ } -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { - u32 *p; - int len; + int node, tmp[2]; + const char *path; - ft_cpu_setup(blob, bd); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", bd->bi_busfreq / 4, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "bus-frequency", bd->bi_busfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_prop_u32(blob, "device_type", "soc", 4, + "bus-frequency", bd->bi_busfreq, 1); - p = ft_get_prop(blob, "/memory/reg", &len); - if (p != NULL) { - *p++ = cpu_to_be32(bd->bi_memstart); - *p = cpu_to_be32(bd->bi_memsize); - } + do_fixup_by_compat_u32(blob, "ns16550", + "clock-frequency", bd->bi_busfreq, 1); + + fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); + + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { #ifdef CONFIG_PCI1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pci1_hose.last_busno - pci1_hose.first_busno; - debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } + #endif #ifdef CONFIG_PCIE1 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); + path = fdt_getprop(blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno + - pcie1_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); } #endif #ifdef CONFIG_PCIE2 - p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len); - if (p != NULL) { - p[0] = 0; - p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; - debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]); - } + path = fdt_getprop(blob, node, "pci2", NULL); + if (path) { + tmp[1] = pcie2_hose.last_busno + - pcie2_hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } #endif - + } } #endif diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 55df5aa..11c1836 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -245,17 +245,14 @@ /* * Pass open firmware flat tree to kernel */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + /* maximum size of the flat tree (8K) */ #define OF_FLAT_TREE_MAX_SIZE 8192 -#define OF_CPU "PowerPC,8610@0" -#define OF_SOC "soc@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc@e0000000/serial@4500" - #define CFG_64BIT_VSPRINTF 1 #define CFG_64BIT_STRTOUL 1 @@ -618,8 +615,8 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ - "dtbaddr=c00000\0" \ - "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ "bdev=sda3\0" \ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ @@ -658,8 +655,8 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ - "dtbaddr=c00000\0" \ - "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ "bdev=sda3\0" \ "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\ "monitor=0-DVI\0" @@ -671,22 +668,22 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #endif /* __CONFIG_H */ From fe8dd0b2220b7c02b0d4c9c4f9967879970477b1 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 9 Jan 2008 12:14:55 -0600 Subject: [PATCH 3/4] 86xx: Remove cache config from configs.h Just use the standard defines in asm/cache.h. Signed-off-by: Jon Loeliger --- include/configs/MPC8610HPCD.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 11c1836..eb6ccb6 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -514,13 +514,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - /* * Internal Definitions * From b830b7f1635984ba607219fcbd78597c28eeb529 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Thu, 10 Jan 2008 14:00:28 -0600 Subject: [PATCH 4/4] 86xx: Support 2GB DIMMs Configure the number of bits used to address the banks inside the SDRAM device. The default register value of 0 means 2 bits to address 4 banks. Higher capacity devices like a 2GB DIMM require 3 bits to address 8 banks. Signed-off-by: Becky Bruce --- cpu/mpc86xx/spd_sdram.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 265e033..54e40f1 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -196,7 +196,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, spd_eeprom_t spd; unsigned int n_ranks; unsigned int rank_density; - unsigned int odt_rd_cfg, odt_wr_cfg; + unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits; unsigned int odt_cfg, mode_odt_enable; unsigned int refresh_clk; #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL @@ -321,6 +321,10 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */ } + ba_bits = 0; + if (spd.nbanks == 0x8) + ba_bits = 1; + #ifdef CONFIG_DDR_INTERLEAVE if (dimm_num != 1) { @@ -357,6 +361,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, #endif | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -386,6 +391,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs0_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -403,6 +409,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs1_config = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds); @@ -422,6 +429,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs2_config = ( 1 << 31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); @@ -439,6 +447,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, ddr->cs3_config = ( 1<<31 | (odt_rd_cfg << 20) | (odt_wr_cfg << 16) + | (ba_bits << 14) | (spd.nrow_addr - 12) << 8 | (spd.ncol_addr - 8) ); debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);