The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>master
Marek Vasut
11 years ago
parent
e97f9d817e
commit
373ee048a8
@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := actux1.o
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@ -1,148 +0,0 @@ |
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/*
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* (C) Copyright 2007 |
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* Michael Schwingen, michael@schwingen.org |
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* |
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* (C) Copyright 2006 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* (C) Copyright 2002 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <malloc.h> |
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#include <asm/arch/ixp425.h> |
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#include <asm/io.h> |
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#include <miiphy.h> |
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#ifdef CONFIG_PCI |
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#include <pci.h> |
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#include <asm/arch/ixp425pci.h> |
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#endif |
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#include "actux1_hw.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_early_init_f(void) |
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{ |
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/* CS5: Debug port */ |
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writel(0x9d520003, IXP425_EXP_CS5); |
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/* CS6: HwRel */ |
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writel(0x81860001, IXP425_EXP_CS6); |
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/* CS7: LEDs */ |
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writel(0x80900003, IXP425_EXP_CS7); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = 0x00000100; |
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); |
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); |
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/* Setup GPIOs for PCI INTA */ |
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA); |
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA); |
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/* Setup GPIOs for 33MHz clock output */ |
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); |
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); |
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writel(0x011001FF, IXP425_GPIO_GPCLKR); |
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udelay(533); |
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); |
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ACTUX1_LED1(2); |
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ACTUX1_LED2(2); |
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ACTUX1_LED3(0); |
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ACTUX1_LED4(0); |
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ACTUX1_LED5(0); |
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ACTUX1_LED6(0); |
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ACTUX1_LED7(0); |
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ACTUX1_HS(ACTUX1_HS_DCD); |
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return 0; |
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} |
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/*
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* Check Board Identity |
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*/ |
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int checkboard(void) |
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{ |
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char buf[64]; |
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int i = getenv_f("serial#", buf, sizeof(buf)); |
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puts("Board: AcTux-1 rev."); |
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putc(ACTUX1_BOARDREL + 'A' - 1); |
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if (i > 0) { |
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puts(", serial# "); |
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puts(buf); |
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} |
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putc('\n'); |
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return 0; |
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} |
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/*************************************************************************
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* get_board_rev() - setup to pass kernel board revision information |
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* 0 = reserved |
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* 1 = Rev. A |
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* 2 = Rev. B |
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*************************************************************************/ |
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u32 get_board_rev(void) |
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{ |
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return ACTUX1_BOARDREL; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); |
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return 0; |
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} |
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#ifdef CONFIG_PCI |
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struct pci_controller hose; |
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void pci_init_board(void) |
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{ |
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pci_ixp_init(&hose); |
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} |
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#endif |
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void reset_phy(void) |
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{ |
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u16 id1, id2; |
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/* initialize the PHY */ |
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miiphy_reset("NPE0", CONFIG_PHY_ADDR); |
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miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1); |
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miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2); |
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id2 &= 0xFFF0; /* mask out revision bits */ |
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if (id1 == 0x13 && id2 == 0x78e0) { |
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/*
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* LXT971/LXT972 PHY: set LED outputs: |
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* LED1(green) = Link/ACT, |
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* LED2 (unused) = LINK, |
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* LED3(red) = Coll |
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*/ |
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miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); |
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} else if (id1 == 0x143 && id2 == 0xbc30) { |
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/* BCM5241: default values are OK */ |
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} else |
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printf("unknown ethernet PHY ID: %x %x\n", id1, id2); |
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} |
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@ -1,41 +0,0 @@ |
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/*
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* (C) Copyright 2007 |
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* Michael Schwingen, michael@schwingen.org |
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* |
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* hardware register definitions for the AcTux-1 board. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _ACTUX1_HW_H |
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#define _ACTUX1_HW_H |
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/* 0 = LED off,1 = green, 2 = red, 3 = orange */ |
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#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) |
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#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) |
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#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) |
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#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3) |
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#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4) |
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#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5) |
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#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) |
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#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) |
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#define ACTUX1_HS_DCD 0x01 |
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#define ACTUX1_HS_DSR 0x02 |
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#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS |
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#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) |
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/* GPIO settings */ |
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#define CONFIG_SYS_GPIO_PCI1_INTA 2 |
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#define CONFIG_SYS_GPIO_PCI2_INTA 3 |
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#define CONFIG_SYS_GPIO_I2C_SDA 4 |
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#define CONFIG_SYS_GPIO_I2C_SCL 5 |
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#define CONFIG_SYS_GPIO_DBGJUMPER 9 |
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#define CONFIG_SYS_GPIO_BUTTON1 10 |
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#define CONFIG_SYS_GPIO_DBGSENSE 11 |
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#define CONFIG_SYS_GPIO_DTR 12 |
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#define CONFIG_SYS_GPIO_IORST 13 /* Out */ |
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#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ |
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#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ |
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#endif |
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@ -1,99 +0,0 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") |
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OUTPUT_ARCH (arm) |
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ENTRY (_start) |
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SECTIONS |
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{ |
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. = 0x00000000; |
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. = ALIGN (4); |
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.text : { |
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*(.__image_copy_start) |
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arch/arm/cpu/ixp/start.o(.text*) |
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net/built-in.o(.text*) |
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board/actux1/built-in.o(.text*) |
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arch/arm/cpu/ixp/built-in.o(.text*) |
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drivers/input/built-in.o(.text*) |
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. = env_offset; |
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common/env_embedded.o(.ppcenv) |
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*(.text*) |
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} |
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. = ALIGN(4); |
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.rodata : { |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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. = ALIGN(4); |
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.data : { |
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*(.data*) |
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} |
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. = ALIGN(4); |
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.got : { |
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*(.got) |
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} |
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. =.; |
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. = ALIGN(4); |
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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. = ALIGN (4); |
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.image_copy_end : |
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{ |
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*(.__image_copy_end) |
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} |
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.rel_dyn_start : |
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{ |
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*(.__rel_dyn_start) |
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} |
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.rel.dyn : { |
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*(.rel*) |
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} |
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.rel_dyn_end : |
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{ |
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*(.__rel_dyn_end) |
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} |
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_end = .; |
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/* |
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* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c |
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* __bss_base and __bss_limit are for linker only (overlay ordering) |
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*/ |
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.bss_start __rel_dyn_start (OVERLAY) : { |
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KEEP(*(.__bss_start)); |
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__bss_base = .; |
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} |
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.bss __bss_base (OVERLAY) : { |
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*(.bss*) |
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. = ALIGN(4); |
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__bss_limit = .; |
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} |
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.bss_end __bss_limit (OVERLAY) : { |
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KEEP(*(.__bss_end)); |
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} |
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.dynsym _end : { *(.dynsym) } |
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.dynbss : { *(.dynbss) } |
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.dynstr : { *(.dynstr*) } |
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.dynamic : { *(.dynamic*) } |
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.hash : { *(.hash*) } |
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.plt : { *(.plt*) } |
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.interp : { *(.interp*) } |
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.gnu : { *(.gnu*) } |
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.ARM.exidx : { *(.ARM.exidx*) } |
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} |
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@ -1,226 +0,0 @@ |
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/*
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* (C) Copyright 2007 |
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* Michael Schwingen, michael@schwingen.org |
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* |
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* Configuration settings for the AcTux-1 board. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_IXP425 1 |
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#define CONFIG_ACTUX1 1 |
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#define CONFIG_MACH_TYPE 1479 |
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#define CONFIG_DISPLAY_CPUINFO 1 |
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#define CONFIG_DISPLAY_BOARDINFO 1 |
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#define CONFIG_IXP_SERIAL |
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#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_BOOTDELAY 3 |
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
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#define CONFIG_BOARD_EARLY_INIT_F 1 |
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#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds" |
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/***************************************************************
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* U-boot generic defines start here. |
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***************************************************************/ |
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/*
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* Size of malloc() pool |
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*/ |
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
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/* allow to overwrite serial and ethaddr */ |
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#define CONFIG_ENV_OVERWRITE |
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/* Command line configuration. */ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_ELF |
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#ifdef CONFIG_PCI |
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#define CONFIG_CMD_PCI |
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#define CONFIG_PCI_PNP |
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#define CONFIG_IXP_PCI |
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#define CONFIG_PCI_SCAN_SHOW |
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#define CONFIG_CMD_PCI_ENUM |
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#endif |
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#define CONFIG_BOOTCOMMAND "run boot_flash" |
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/* enable passing of ATAGs */ |
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#define CONFIG_CMDLINE_TAG 1 |
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#define CONFIG_SETUP_MEMORY_TAGS 1 |
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#define CONFIG_INITRD_TAG 1 |
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#define CONFIG_REVISION_TAG 1 |
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#if defined(CONFIG_CMD_KGDB) |
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# define CONFIG_KGDB_BAUDRATE 230400 |
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#endif |
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/* Miscellaneous configurable options */ |
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#define CONFIG_SYS_LONGHELP |
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/* Console I/O Buffer Size */ |
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#define CONFIG_SYS_CBSIZE 256 |
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/* Print Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
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/* max number of command args */ |
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#define CONFIG_SYS_MAXARGS 16 |
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/* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
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#define CONFIG_SYS_MEMTEST_START 0x00400000 |
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#define CONFIG_SYS_MEMTEST_END 0x00800000 |
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/* timer clock - 2* OSC_IN system clock */ |
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#define CONFIG_IXP425_TIMER_CLK 66666666 |
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/* default load address */ |
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#define CONFIG_SYS_LOAD_ADDR 0x00010000 |
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/* valid baudrates */ |
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ |
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115200, 230400 } |
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#define CONFIG_SERIAL_RTS_ACTIVE 1 |
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/* Expansion bus settings */ |
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#define CONFIG_SYS_EXP_CS0 0xbd113842 |
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/* SDRAM settings */ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define PHYS_SDRAM_1 0x00000000 |
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
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#ifdef CONFIG_RAM_32MB |
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# define CONFIG_SYS_SDR_CONFIG 0x18 |
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# define PHYS_SDRAM_1_SIZE 0x02000000 |
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# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a |
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# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 |
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# define CONFIG_SYS_DRAM_SIZE 0x02000000 |
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#else /* 16MB SDRAM */ |
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# define CONFIG_SYS_SDR_CONFIG 0x3A |
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# define PHYS_SDRAM_1_SIZE 0x01000000 |
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# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a |
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# define CONFIG_SYS_SDR_MODE_CONFIG 0x1 |
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# define CONFIG_SYS_DRAM_SIZE 0x01000000 |
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#endif |
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/* FLASH organization */ |
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#define CONFIG_SYS_TEXT_BASE 0x50000000 |
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#ifdef CONFIG_FLASH2X2 |
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# define CONFIG_SYS_MAX_FLASH_BANKS 2 |
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/* max number of sectors on one chip */ |
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# define CONFIG_SYS_MAX_FLASH_SECT 40 |
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# define PHYS_FLASH_1 0x50000000 |
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# define PHYS_FLASH_2 0x50200000 |
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# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } |
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#endif |
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#ifdef CONFIG_FLASH1X8 |
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# define CONFIG_SYS_MAX_FLASH_BANKS 1 |
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/* max number of sectors on one chip */ |
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# define CONFIG_SYS_MAX_FLASH_SECT 140 |
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# define PHYS_FLASH_1 0x50000000 |
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# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } |
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#endif |
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) |
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#define CONFIG_BOARD_SIZE_LIMIT 262144 |
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|
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/* Use common CFI driver */ |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_FLASH_CFI_DRIVER |
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/* no byte writes on IXP4xx */ |
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
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/* print 'E' for empty sector on flinfo */ |
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#define CONFIG_SYS_FLASH_EMPTY_INFO |
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/* Ethernet */ |
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|
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/* include IXP4xx NPE support */ |
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#define CONFIG_IXP4XX_NPE 1 |
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/* NPE0 PHY address */ |
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#define CONFIG_PHY_ADDR 0 |
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/* NPE1 PHY address (HW Release E only) */ |
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#define CONFIG_PHY1_ADDR 1 |
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/* MII PHY management */ |
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#define CONFIG_MII 1 |
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/* Number of ethernet rx buffers & descriptors */ |
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#define CONFIG_SYS_RX_ETH_BUFFER 16 |
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#define CONFIG_RESET_PHY_R 1 |
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|
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#define CONFIG_HAS_ETH1 1 |
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|
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_NET |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_PING |
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#undef CONFIG_CMD_NFS |
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|
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/* BOOTP options */ |
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#define CONFIG_BOOTP_BOOTFILESIZE |
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#define CONFIG_BOOTP_BOOTPATH |
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#define CONFIG_BOOTP_GATEWAY |
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#define CONFIG_BOOTP_HOSTNAME |
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|
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/* Cache Configuration */ |
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#define CONFIG_SYS_CACHELINE_SIZE 32 |
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|
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/*
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* environment organization: |
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* one flash sector, embedded in uboot area (bottom bootblock flash) |
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*/ |
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#define CONFIG_ENV_IS_IN_FLASH 1 |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) |
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#define CONFIG_SYS_USE_PPCENV 1 |
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|
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"npe_ucode=50040000\0" \
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"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
|
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"kerneladdr=50050000\0" \
|
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"kernelfile=actux1/uImage\0" \
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"rootfile=actux1/rootfs\0" \
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"rootaddr=50170000\0" \
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"loadaddr=10000\0" \
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"updateboot_ser=mw.b 10000 ff 40000;" \
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" loady ${loadaddr};" \
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" run eraseboot writeboot\0" \
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"updateboot_net=mw.b 10000 ff 40000;" \
|
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" tftp ${loadaddr} actux1/u-boot.bin;" \
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" run eraseboot writeboot\0" \
|
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"eraseboot=protect off 50000000 50003fff;" \
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" protect off 50006000 5003ffff;" \
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" erase 50000000 50003fff;" \
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" erase 50006000 5003ffff\0" \
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"writeboot=cp.b 10000 50000000 4000;" \
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" cp.b 16000 50006000 3a000\0" \
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"updateucode=loady;" \
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" era ${npe_ucode} +${filesize};" \
|
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" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
|
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"updateroot=tftp ${loadaddr} ${rootfile};" \
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" era ${rootaddr} +${filesize};" \
|
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" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
|
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"updatekern=tftp ${loadaddr} ${kernelfile};" \
|
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" era ${kerneladdr} +${filesize};" \
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" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
|
||||
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
|
||||
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
|
||||
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
|
||||
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
|
||||
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
|
||||
"boot_flash=run flashargs addtty addeth;" \
|
||||
" bootm ${kerneladdr}\0" \
|
||||
"boot_net=run netargs addtty addeth;" \
|
||||
" tftpboot ${loadaddr} ${kernelfile};" \
|
||||
" bootm\0" |
||||
|
||||
/* additions for new relocation code, must be added to all boards */ |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue