This is not used in U-Boot. Drop this option and associated dead code. Signed-off-by: Simon Glass <sjg@chromium.org>master
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/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Andreas Heppel <aheppel@sysgo.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* Initialisation of the PCI-to-ISA bridge and disabling the BIOS |
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* write protection (for flash) in function 0 of the chip. |
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* Enabling function 1 (IDE controller of the chip. |
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*/ |
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#include <common.h> |
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#include <config.h> |
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#include <asm/io.h> |
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#include <pci.h> |
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#include <w83c553f.h> |
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#define out8(addr,val) do { \ |
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out_8((u8*) (addr),(val)); udelay(1); \
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} while (0) |
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#define out16(addr,val) do { \ |
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out_be16((u16*) (addr),(val)); udelay(1); \
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} while (0) |
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extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; |
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void initialise_pic(void); |
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void initialise_dma(void); |
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void initialise_w83c553f(void) |
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{ |
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pci_dev_t devbusfn; |
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unsigned char reg8; |
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unsigned short reg16; |
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unsigned int reg32; |
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devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0); |
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if (devbusfn == -1) |
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{ |
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printf("Error: Cannot find W83C553F controller on any PCI bus."); |
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return; |
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} |
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16); |
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; |
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16); |
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pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8); |
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/* 16 MB ISA memory space */ |
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reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7); |
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reg8 &= ~IPADCR_MBE512; |
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pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8); |
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pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8); |
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/* switch off BIOS write protection */ |
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reg8 |= CSCR_UBIOSCSE; |
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reg8 &= ~CSCR_BIOSWP; |
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pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8); |
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/*
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* Interrupt routing: |
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* - IDE -> IRQ 9/0 |
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* - INTA -> IRQ 10 |
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* - INTB -> IRQ 11 |
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* - INTC -> IRQ 14 |
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* - INTD -> IRQ 15 |
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*/ |
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pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90); |
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pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF); |
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/*
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* Read IDE bus offsets from function 1 device. |
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* We must unmask the LSB indicating that ist is an IO address. |
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*/ |
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devbusfn |= PCI_BDF(0,0,1); |
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/*
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* Switch off legacy IRQ for IDE and IDE port 1. |
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*/ |
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pci_write_config_byte(devbusfn, 0x09, 0x8F); |
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pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32); |
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reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16); |
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pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32); |
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]); |
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ide_bus_offset[0] &= ~1; |
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#if CONFIG_SYS_IDE_MAXBUS > 1 |
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]); |
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ide_bus_offset[1] &= ~1; |
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#endif |
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/*
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* Enable function 1, IDE -> busmastering and IO space access |
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*/ |
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pci_read_config_word(devbusfn, PCI_COMMAND, ®16); |
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reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; |
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pci_write_config_word(devbusfn, PCI_COMMAND, reg16); |
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/*
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* Initialise ISA interrupt controller |
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*/ |
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initialise_pic(); |
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/*
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* Initialise DMA controller |
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*/ |
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initialise_dma(); |
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} |
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void initialise_pic(void) |
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{ |
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out8(W83C553F_PIC1_ICW1, 0x11); |
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out8(W83C553F_PIC1_ICW2, 0x08); |
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out8(W83C553F_PIC1_ICW3, 0x04); |
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out8(W83C553F_PIC1_ICW4, 0x01); |
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out8(W83C553F_PIC1_OCW1, 0xfb); |
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out8(W83C553F_PIC1_ELC, 0x20); |
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out8(W83C553F_PIC2_ICW1, 0x11); |
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out8(W83C553F_PIC2_ICW2, 0x08); |
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out8(W83C553F_PIC2_ICW3, 0x02); |
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out8(W83C553F_PIC2_ICW4, 0x01); |
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out8(W83C553F_PIC2_OCW1, 0xff); |
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out8(W83C553F_PIC2_ELC, 0xce); |
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out8(W83C553F_TMR1_CMOD, 0x74); |
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out8(W83C553F_PIC2_OCW1, 0x20); |
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out8(W83C553F_PIC1_OCW1, 0x20); |
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out8(W83C553F_PIC2_OCW1, 0x2b); |
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out8(W83C553F_PIC1_OCW1, 0x2b); |
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} |
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void initialise_dma(void) |
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{ |
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unsigned int channel; |
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unsigned int rvalue1, rvalue2; |
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/* perform a H/W reset of the devices */ |
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out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00); |
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out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000); |
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/* initialise all channels to a sane state */ |
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for (channel = 0; channel < 4; channel++) { |
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/*
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* dependent upon the channel, setup the specifics: |
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* |
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* demand |
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* address-increment |
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* autoinitialize-disable |
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* verify-transfer |
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*/ |
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switch (channel) { |
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case 0: |
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY); |
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rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL); |
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break; |
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case 1: |
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); |
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY); |
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break; |
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case 2: |
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); |
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY); |
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break; |
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case 3: |
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rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); |
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rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY); |
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break; |
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default: |
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rvalue1 = 0x00; |
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rvalue2 = 0x00; |
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break; |
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} |
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/* write to write mode registers */ |
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out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF); |
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out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF); |
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} |
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/* enable all channels */ |
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out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00); |
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out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000); |
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/*
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* initialize the global DMA configuration |
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* |
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* DACK# active low |
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* DREQ active high |
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* fixed priority |
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* channel group enable |
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*/ |
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out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00); |
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out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000); |
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} |
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