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mpc85xx boards: initdram() cleanup/bugfix

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Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts.  Most
of the initdram() functions were identical, with 2 common differences:

1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others.  I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.

2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document.  It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled.  This seems bad.

The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.c

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
master
Becky Bruce 14 years ago committed by Kumar Gala
parent 6b1ef2a6a5
commit 38dba0c2ff
31 changed files with 121 additions and 820 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 52
      arch/powerpc/cpu/mpc85xx/cpu.c
  2. 10
      arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
  3. 13
      arch/powerpc/include/asm/fsl_ddr_sdram.h
  4. 4
      arch/powerpc/include/asm/fsl_lbc.h
  5. 21
      board/freescale/mpc8536ds/mpc8536ds.c
  6. 52
      board/freescale/mpc8540ads/mpc8540ads.c
  7. 19
      board/freescale/mpc8540ads/tlb.c
  8. 43
      board/freescale/mpc8541cds/mpc8541cds.c
  9. 17
      board/freescale/mpc8544ds/mpc8544ds.c
  10. 38
      board/freescale/mpc8548cds/mpc8548cds.c
  11. 45
      board/freescale/mpc8555cds/mpc8555cds.c
  12. 52
      board/freescale/mpc8560ads/mpc8560ads.c
  13. 19
      board/freescale/mpc8560ads/tlb.c
  14. 38
      board/freescale/mpc8568mds/mpc8568mds.c
  15. 36
      board/freescale/mpc8569mds/mpc8569mds.c
  16. 19
      board/freescale/mpc8572ds/mpc8572ds.c
  17. 13
      board/freescale/p1022ds/p1022ds.c
  18. 15
      board/freescale/p1_p2_rdb/ddr.c
  19. 34
      board/freescale/p2020ds/p2020ds.c
  20. 45
      board/sbc8548/sbc8548.c
  21. 34
      board/sbc8548/tlb.c
  22. 93
      board/sbc8560/sbc8560.c
  23. 15
      board/socrates/sdram.c
  24. 32
      board/stx/stxgp3/stxgp3.c
  25. 33
      board/stx/stxssa/stxssa.c
  26. 37
      board/tqc/tqm85xx/sdram.c
  27. 47
      board/tqc/tqm85xx/tlb.c
  28. 2
      board/xes/common/Makefile
  29. 46
      board/xes/common/fsl_8xxx_ddr.c
  30. 13
      board/xes/xpedite517x/xpedite517x.c
  31. 4
      include/configs/TQM85xx.h

52
arch/powerpc/cpu/mpc85xx/cpu.c
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@ -34,6 +34,7 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
@ -286,6 +287,57 @@ void mpc85xx_reginfo(void)
print_lbc_regs();
}
/* Common ddr init for non-corenet fsl 85xx platforms */
#ifndef CONFIG_FSL_CORENET
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
#if defined(CONFIG_DDR_DLL)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned int x = 10;
unsigned int i;
/*
* Work around to stabilize DDR DLL
*/
out_be32(&gur->ddrdllcr, 0x81000000);
asm("sync;isync;msync");
udelay(200);
while (in_be32(&gur->ddrdllcr) != 0x81000100) {
setbits_be32(&gur->devdisr, 0x00010000);
for (i = 0; i < x; i++)
;
clrbits_be32(&gur->devdisr, 0x00010000);
x++;
}
}
#endif
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
/* Some boards also have sdram on the lbc */
sdram_init();
puts("DDR: ");
return dram_size;
}
#endif
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */

10
arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
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@ -9,6 +9,16 @@
#include <common.h>
#include <asm/fsl_lbc.h>
#ifdef CONFIG_MPC85xx
/* Boards should provide their own version of this if they use lbc sdram */
void __sdram_init(void)
{
/* Do nothing */
}
void sdram_init(void) __attribute__((weak, alias("__sdram_init")));
#endif
void print_lbc_regs(void)
{
int i;

13
arch/powerpc/include/asm/fsl_ddr_sdram.h
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@ -214,6 +214,19 @@ typedef struct memctl_options_s {
extern phys_size_t fsl_ddr_sdram(void);
/*
* The 85xx boards have a common prototype for fixed_sdram so put the
* declaration here.
*/
#ifdef CONFIG_MPC85xx
extern phys_size_t fixed_sdram(void);
#endif
#if defined(CONFIG_DDR_ECC)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
typedef struct fixed_ddr_parm{
int min_freq;
int max_freq;

4
arch/powerpc/include/asm/fsl_lbc.h
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@ -16,6 +16,10 @@
#include <config.h>
#include <common.h>
#ifdef CONFIG_MPC85xx
void sdram_init(void);
#endif
/* BR - Base Registers
*/
#define BR0 0x5000 /* Register offset to immr */

21
board/freescale/mpc8536ds/mpc8536ds.c
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@ -42,8 +42,6 @@
#include "../common/sgmii_riser.h"
phys_size_t fixed_sdram(void);
int board_early_init_f (void)
{
#ifdef CONFIG_MMC
@ -98,25 +96,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
phys_size_t dram_size = 0;
puts("Initializing....");
#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
return dram_size;
}
#if !defined(CONFIG_SPD_EEPROM)
/*
* Fixed sdram init -- doesn't use serial presence detect.

52
board/freescale/mpc8540ads/mpc8540ads.c
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@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);
int checkboard (void)
{
@ -61,54 +59,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/*
* Work around to stabilize DDR DLL
*/
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
}
#endif
#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
dram_size = fixed_sdram();
#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
/*
* Initialize SDRAM.
*/
sdram_init();
puts(" DDR: ");
return dram_size;
}
/*
* Initialize Local Bus
*/
@ -232,7 +182,7 @@ sdram_init(void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

19
board/freescale/mpc8540ads/tlb.c
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@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 8, 9: 128M DDR
* 0x00000000 64M DDR System memory
* 0x04000000 64M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_64M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_64M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

43
board/freescale/mpc8541cds/mpc8541cds.c
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@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
void sdram_init(void);
/*
* I/O Port configuration table
@ -242,48 +241,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
/*
* Work around to stabilize DDR DLL MSYNC_IN.
* Errata DDR9 seems to have been fixed.
* This is now the workaround for Errata DDR11:
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
udelay(200);
}
#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
/*
* SDRAM Initialization
*/
sdram_init();
puts(" DDR: ");
return dram_size;
}
/*
* Initialize Local Bus
*/

17
board/freescale/mpc8544ds/mpc8544ds.c
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@ -68,23 +68,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
return dram_size;
}
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

38
board/freescale/mpc8548cds/mpc8548cds.c
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@ -42,7 +42,6 @@
DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
void sdram_init(void);
int checkboard (void)
{
@ -75,43 +74,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
/*
* Work around to stabilize DDR DLL MSYNC_IN.
* Errata DDR9 seems to have been fixed.
* This is now the workaround for Errata DDR11:
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
udelay(200);
}
#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
/*
* SDRAM Initialization
*/
sdram_init();
puts(" DDR: ");
return dram_size;
}
/*
* Initialize Local Bus
*/

45
board/freescale/mpc8555cds/mpc8555cds.c
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@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
#endif
void local_bus_init(void);
void sdram_init(void);
/*
* I/O Port configuration table
@ -240,50 +239,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
/*
* Work around to stabilize DDR DLL MSYNC_IN.
* Errata DDR9 seems to have been fixed.
* This is now the workaround for Errata DDR11:
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
udelay(200);
}
#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
/*
* SDRAM Initialization
*/
sdram_init();
puts(" DDR: ");
return dram_size;
}
/*
* Initialize Local Bus
*/

52
board/freescale/mpc8560ads/mpc8560ads.c
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@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram(void);
/*
@ -266,54 +264,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/*
* Work around to stabilize DDR DLL
*/
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
}
#endif
#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
dram_size = fixed_sdram();
#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
/*
* Initialize SDRAM.
*/
sdram_init();
puts(" DDR: ");
return dram_size;
}
/*
* Initialize Local Bus
*/
@ -437,7 +387,7 @@ sdram_init(void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

19
board/freescale/mpc8560ads/tlb.c
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@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16K, 1),
#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 8, 9: 128M DDR
* 0x00000000 64M DDR System memory
* 0x04000000 64M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
#error("Update the number of table entries in tlb1_entry")
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_64M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 9, BOOKE_PAGESZ_64M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

38
board/freescale/mpc8568mds/mpc8568mds.c
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@ -101,7 +101,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
};
void local_bus_init(void);
void sdram_init(void);
int board_early_init_f (void)
{
@ -138,43 +137,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
/*
* Work around to stabilize DDR DLL MSYNC_IN.
* Errata DDR9 seems to have been fixed.
* This is now the workaround for Errata DDR11:
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
gur->ddrdllcr = 0x81000000;
asm("sync;isync;msync");
udelay(200);
}
#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
/*
* SDRAM Initialization
*/
sdram_init();
puts(" DDR: ");
return dram_size;
}
/*
* Initialize Local Bus
*/

36
board/freescale/mpc8569mds/mpc8569mds.c
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@ -45,8 +45,6 @@
#include "../common/pq-mds-pib.h"
#endif
phys_size_t fixed_sdram(void);
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDC */
{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
@ -245,40 +243,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
/*
* Work around to stabilize DDR DLL MSYNC_IN.
* Errata DDR9 seems to have been fixed.
* This is now the workaround for Errata DDR11:
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
volatile ccsr_gur_t *gur =
(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
out_be32(&gur->ddrdllcr, 0x81000000);
udelay(200);
#endif
#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
return dram_size;
}
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{

19
board/freescale/mpc8572ds/mpc8572ds.c
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@ -39,8 +39,6 @@
#include "../common/sgmii_riser.h"
long int fixed_sdram(void);
int checkboard (void)
{
u8 vboot;
@ -74,23 +72,6 @@ int checkboard (void)
return 0;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
puts("Initializing....");
#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
return dram_size;
}
#if !defined(CONFIG_SPD_EEPROM)
/*

13
board/freescale/p1022ds/p1022ds.c
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@ -76,19 +76,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
puts("Initializing....\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000;
puts(" DDR: ");
return dram_size;
}
#define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */

15
board/freescale/p1_p2_rdb/ddr.c
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@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
return ddr_size;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
dram_size = fixed_sdram();
set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts("DDR: ");
return dram_size;
}

34
board/freescale/p2020ds/p2020ds.c
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@ -44,8 +44,6 @@
DECLARE_GLOBAL_DATA_PTR;
phys_size_t fixed_sdram(void);
int checkboard(void)
{
u8 sw;
@ -70,31 +68,6 @@ int checkboard(void)
return 0;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = 0;
puts("Initializing....");
#ifdef CONFIG_DDR_SPD
dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram();
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
dram_size,
LAW_TRGT_IF_DDR) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
};
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
puts(" DDR: ");
return dram_size;
}
#if !defined(CONFIG_DDR_SPD)
/*
* Fixed sdram init -- doesn't use serial presence detect.
@ -170,6 +143,13 @@ phys_size_t fixed_sdram(void)
udelay(500);
#endif
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
LAW_TRGT_IF_DDR) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
};
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}

45
board/sbc8548/sbc8548.c
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@ -43,8 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
void sdram_init(void);
long int fixed_sdram (void);
int board_early_init_f (void)
{
@ -69,47 +67,6 @@ int checkboard (void)
return 0;
}
phys_size_t
initdram(int board_type)
{
long dram_size = 0;
puts("Initializing\n");
#if defined(CONFIG_DDR_DLL)
{
/*
* Work around to stabilize DDR DLL MSYNC_IN.
* Errata DDR9 seems to have been fixed.
* This is now the workaround for Errata DDR11:
* Override DLL = 1, Course Adj = 1, Tap Select = 0
*/
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
out_be32(&gur->ddrdllcr, 0x81000000);
asm("sync;isync;msync");
udelay(200);
}
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
dram_size = fixed_sdram ();
#endif
/*
* SDRAM Initialization
*/
sdram_init();
puts(" DDR: ");
return dram_size;
}
/*
* Initialize Local Bus
*/
@ -268,7 +225,7 @@ testdram(void)
* fixed_sdram init -- doesn't use serial presence detect.
* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
************************************************************************/
long int fixed_sdram (void)
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

34
board/sbc8548/tlb.c
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@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 1, BOOKE_PAGESZ_1G, 1),
/*
* TLB 2: 256M Cacheable, non-guarded
* 0x0 256M DDR SDRAM
*/
#if !defined(CONFIG_SPD_EEPROM)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 2, BOOKE_PAGESZ_256M, 1),
#endif
/*
* TLB 3: 64M Non-cacheable, guarded
* TLB 2: 64M Non-cacheable, guarded
* 0xe0000000 1M CCSRBAR
* 0xe2000000 8M PCI1 IO
* 0xe2800000 8M PCIe IO
*/
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
0, 2, BOOKE_PAGESZ_64M, 1),
/*
* TLB 4: 64M Cacheable, non-guarded
* TLB 3: 64M Cacheable, non-guarded
* 0xf0000000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 4, BOOKE_PAGESZ_64M, 1),
0, 3, BOOKE_PAGESZ_64M, 1),
/*
* TLB 5: 64M Cacheable, non-guarded
* TLB 4: 64M Cacheable, non-guarded
* 0xf4000000 64M LBC SDRAM Second half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
0, 4, BOOKE_PAGESZ_64M, 1),
/*
* TLB 6: 16M Cacheable, non-guarded
* TLB 5: 16M Cacheable, non-guarded
* 0xf8000000 1M 7-segment LED display
* 0xf8100000 1M User switches
* 0xf8300000 1M Board revision
@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
0, 5, BOOKE_PAGESZ_16M, 1),
/*
* TLB 7: 4M Non-cacheable, guarded
* TLB 6: 4M Non-cacheable, guarded
* 0xfb800000 4M 1st 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4M, 1),
0, 6, BOOKE_PAGESZ_4M, 1),
/*
* TLB 8: 4M Non-cacheable, guarded
* TLB 7: 4M Non-cacheable, guarded
* 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
CONFIG_SYS_ALT_FLASH + 0x400000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_4M, 1),
0, 7, BOOKE_PAGESZ_4M, 1),
};

93
board/sbc8560/sbc8560.c
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@ -38,8 +38,6 @@
#include <libfdt.h>
#include <fdt_support.h>
long int fixed_sdram (void);
/*
* I/O Port configuration table
*
@ -263,95 +261,6 @@ int checkboard (void)
}
phys_size_t initdram (int board_type)
{
long dram_size = 0;
#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
#endif /* 0 */
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_DDR_DLL)
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
#endif
#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
dram_size = fixed_sdram ();
#endif
#if 0
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
#endif
lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
udelay(200);
temp_lbcdll = gur->lbcdllcr;
gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
asm("sync;isync;msync");
}
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
asm("sync");
(unsigned int) * (ulong *)0 = 0x000000ff;
lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
asm("sync");
lbc->lsrt = CONFIG_SYS_LBC_LSRT;
asm("sync");
lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
asm("sync");
#endif
#endif
#if defined(CONFIG_DDR_ECC)
{
/* Initialize all of memory for ECC, then
* enable errors */
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
/* Enable errors for ECC */
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
}
#endif
return dram_size;
}
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
@ -390,7 +299,7 @@ int testdram (void)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
long int fixed_sdram (void)
phys_size_t fixed_sdram(void)
{
#define CONFIG_SYS_DDR_CONTROL 0xc2000000

15
board/socrates/sdram.c
Unescape View File

@ -39,7 +39,7 @@
* so this should be extended for other future boards
* using this routine!
*/
long int fixed_sdram(void)
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@ -77,19 +77,6 @@ long int fixed_sdram(void)
}
#endif
phys_size_t initdram (int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
dram_size = fixed_sdram();
#endif
return dram_size;
}
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{

32
board/stx/stxgp3/stxgp3.c
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@ -40,8 +40,6 @@
#include <spd_sdram.h>
#include <miiphy.h>
long int fixed_sdram (void);
/*
* I/O Port configuration table
*
@ -277,36 +275,6 @@ show_activity(int flag)
next_led_update += (get_tbclk() / 4);
}
phys_size_t
initdram (int board_type)
{
long dram_size = 0;
#if defined(CONFIG_DDR_DLL)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
}
#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC)
/* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
return dram_size;
}
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)

33
board/stx/stxssa/stxssa.c
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@ -41,8 +41,6 @@
#include <miiphy.h>
#include <netdev.h>
long int fixed_sdram (void);
/*
* I/O Port configuration table
*
@ -294,37 +292,6 @@ show_activity(int flag)
next_led_update += (get_tbclk() / 4);
}
phys_size_t
initdram (int board_type)
{
long dram_size = 0;
#if defined(CONFIG_DDR_DLL)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint temp_ddrdll = 0;
/* Work around to stabilize DDR DLL */
temp_ddrdll = gur->ddrdllcr;
gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
asm("sync;isync;msync");
}
#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#if defined(CONFIG_DDR_ECC)
/* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
return dram_size;
}
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{

37
board/tqc/tqm85xx/sdram.c
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@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl)
return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
}
phys_size_t initdram (int board_type)
{
phys_size_t dram_size = 0;
#if defined(CONFIG_DDR_DLL)
/*
* This DLL-Override only used on TQM8540 and TQM8560
*/
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int i, x;
x = 10;
/*
* Work around to stabilize DDR DLL
*/
gur->ddrdllcr = 0x81000000;
asm ("sync; isync; msync");
udelay (200);
while (gur->ddrdllcr != 0x81000100) {
gur->devdisr = gur->devdisr | 0x00010000;
asm ("sync; isync; msync");
for (i = 0; i < x; i++)
;
gur->devdisr = gur->devdisr & 0xfff7ffff;
asm ("sync; isync; msync");
x++;
}
}
#endif
dram_size = fixed_sdram();
return dram_size;
}
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{

47
board/tqc/tqm85xx/tlb.c
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@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
/*
* TLB 7+8: 2G DDR, cache enabled
* 0x00000000 2G DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#else
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_PCIE1
/*
* TLB 9: 16M Non-cacheable, guarded
@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_64M, 1),
/*
* TLB 8+9: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 9, BOOKE_PAGESZ_256M, 1),
#ifdef CONFIG_PCIE1
/*
* TLB 10: 16M Non-cacheable, guarded

2
board/xes/common/Makefile
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@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o
COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o
COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o

46
board/xes/common/fsl_8xxx_ddr.c
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@ -1,46 +0,0 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/mmu.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = fsl_ddr_sdram();
#ifdef CONFIG_MPC85xx
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize and enable DDR ECC */
ddr_enable_ecc(dram_size);
#endif
return dram_size;
}

13
board/xes/xpedite517x/xpedite517x.c
Unescape View File

@ -22,6 +22,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <fdt_support.h>
@ -71,6 +72,18 @@ int board_early_init_r(void)
return 0;
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size = fsl_ddr_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize and enable DDR ECC */
ddr_enable_ecc(dram_size);
#endif
return dram_size;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{

4
include/configs/TQM85xx.h
Unescape View File

@ -147,6 +147,10 @@
* DDR Setup
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#if defined(CONFIG_TQM_BIGFLASH) || \
(!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
#endif
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#ifdef CONFIG_TQM8548_AG
#define CONFIG_VERY_BIG_RAM

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