Wolfgang Denk
17 years ago
commit
39166b5c9e
@ -1,235 +0,0 @@ |
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/* |
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* Copyright 2007 |
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* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
|
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* Copyright 2004, 2007 Freescale Semiconductor. |
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* Copyright 2002,2003, Motorola Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <ppc_asm.tmpl> |
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#include <ppc_defs.h> |
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#include <asm/cache.h> |
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#include <asm/mmu.h> |
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#include <config.h> |
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#include <mpc85xx.h> |
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|
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#define LAWAR_TRGT_PCI1 0x00000000 |
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#define LAWAR_TRGT_PCI2 0x00100000 |
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#define LAWAR_TRGT_PCIE 0x00200000 |
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#define LAWAR_TRGT_DDR 0x00f00000 |
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|
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/* |
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* TLB0 and TLB1 Entries |
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* |
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* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
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* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
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* these TLB entries are established. |
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* |
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* The TLB entries for DDR are dynamically setup in spd_sdram() |
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* and use TLB1 Entries 8 through 15 as needed according to the |
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* size of DDR memory. |
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* |
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* MAS0: tlbsel, esel, nv |
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* MAS1: valid, iprot, tid, ts, tsize |
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* MAS2: epn, x0, x1, w, i, m, g, e |
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* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
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*/ |
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#define entry_start \ |
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mflr r1 ; \
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bl 0f ;
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|
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#define entry_end \ |
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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|
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.section .bootpg, "ax" |
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.globl tlb1_entry
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tlb1_entry: |
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entry_start |
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|
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/* |
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* Number of TLB0 and TLB1 entries in the following table |
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*/ |
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.long (2f-1f)/16 |
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1: |
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
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/* |
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* TLB0 4K Non-cacheable, guarded |
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* 0xff700000 4K Initial CCSRBAR mapping |
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* |
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* This ends up at a TLB0 Index==0 entry, and must not collide |
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* with other TLB0 Entries. |
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*/ |
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.long FSL_BOOKE_MAS0(0, 0, 0) |
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
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#else |
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#error("Update the number of table entries in tlb1_entry") |
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#endif |
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|
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/* |
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* TLB0 16K Cacheable, guarded |
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* Temporary Global data for initialization |
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* |
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* Use four 4K TLB0 entries. These entries must be cacheable |
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* as they provide the bootstrap memory before the memory |
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* controler and real memory have been configured. |
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* |
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* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
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* and must not collide with other TLB0 entries. |
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*/ |
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.long FSL_BOOKE_MAS0(0, 0, 0) |
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, MAS2_G) |
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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.long FSL_BOOKE_MAS0(0, 0, 0) |
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, MAS2_G) |
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, |
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(MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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.long FSL_BOOKE_MAS0(0, 0, 0) |
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, MAS2_G) |
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, |
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(MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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.long FSL_BOOKE_MAS0(0, 0, 0) |
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, MAS2_G) |
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, |
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(MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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/* TLB 1 Initializations */ |
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/* |
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* TLB 0, 1: 128M Non-cacheable, guarded |
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* 0xf8000000 128M FLASH |
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* Out of reset this entry is only 4K. |
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*/ |
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.long FSL_BOOKE_MAS0(1, 0, 0) |
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
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.long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x4000000, (MAS2_I|MAS2_G)) |
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.long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x4000000, 0, |
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(MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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.long FSL_BOOKE_MAS0(1, 1, 0) |
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
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.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
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.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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/* |
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* TLB 2: 1G Non-cacheable, guarded |
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* 0x80000000 1G PCI1/PCIE 8,9,a,b |
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*/ |
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.long FSL_BOOKE_MAS0(1, 2, 0) |
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) |
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.long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) |
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.long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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/* |
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* TLB 3, 4: 512M Non-cacheable, guarded |
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* 0xc0000000 1G PCI2 |
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*/ |
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.long FSL_BOOKE_MAS0(1, 3, 0) |
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
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.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G)) |
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.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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.long FSL_BOOKE_MAS0(1, 4, 0) |
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
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.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) |
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.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, |
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(MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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/* |
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* TLB 5: 64M Non-cacheable, guarded |
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* 0xe000_0000 1M CCSRBAR |
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* 0xe200_0000 1M PCI1 IO |
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* 0xe210_0000 1M PCI2 IO |
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* 0xe300_0000 1M PCIe IO |
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*/ |
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.long FSL_BOOKE_MAS0(1, 5, 0) |
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
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|
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2: |
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entry_end |
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|
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/* |
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* LAW(Local Access Window) configuration: |
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* |
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* 0x0000_0000 0x7fff_ffff DDR 2G |
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
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* 0xa000_0000 0xbfff_ffff PCIe MEM 512M |
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* 0xc000_0000 0xdfff_ffff PCI2 MEM 512M |
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* 0xe000_0000 0xe000_ffff CCSR 1M |
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* 0xe200_0000 0xe10f_ffff PCI1 IO 1M |
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* 0xe280_0000 0xe20f_ffff PCI2 IO 1M |
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* 0xe300_0000 0xe30f_ffff PCIe IO 1M |
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* 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M |
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* |
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* Notes: |
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
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* If flash is 8M at default position (last 8M), no LAW needed. |
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* |
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* LAW 0 is reserved for boot mapping |
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*/ |
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.section .bootpg, "ax" |
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.globl law_entry
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law_entry: |
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entry_start |
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.long (4f-3f)/8 |
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3: |
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.long 0
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.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_1G)) & ~LAWAR_EN |
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.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff |
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.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
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|
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.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff |
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.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) |
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|
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.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff |
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.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
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|
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.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff |
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.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) |
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|
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.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff |
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.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M) |
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|
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.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff |
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.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M) |
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|
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
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.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff |
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.long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) |
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4: |
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entry_end |
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@ -0,0 +1,61 @@ |
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/*
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/fsl_law.h> |
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#include <asm/mmu.h> |
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|
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/*
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* LAW(Local Access Window) configuration: |
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* |
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* 0x0000_0000 0x7fff_ffff DDR 2G |
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
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* 0xa000_0000 0xbfff_ffff PCIe MEM 512M |
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* 0xc000_0000 0xdfff_ffff PCI2 MEM 512M |
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* 0xe000_0000 0xe000_ffff CCSR 1M |
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* 0xe200_0000 0xe10f_ffff PCI1 IO 1M |
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* 0xe280_0000 0xe20f_ffff PCI2 IO 1M |
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* 0xe300_0000 0xe30f_ffff PCIe IO 1M |
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* 0xf800_0000 0xffff_ffff FLASH (boot bank) 128M |
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* |
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* Notes: |
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
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* If flash is 8M at default position (last 8M), no LAW needed. |
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* |
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* LAW 0 is reserved for boot mapping |
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*/ |
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|
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struct law_entry law_table[] = { |
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SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), |
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SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), |
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SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), |
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SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), |
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SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), |
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SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), |
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
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SET_LAW_ENTRY(8, CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
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}; |
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|
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int num_law_entries = ARRAY_SIZE(law_table); |
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@ -0,0 +1,90 @@ |
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/*
|
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* Copyright 2008 Freescale Semiconductor, Inc. |
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* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/mmu.h> |
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|
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struct fsl_e_tlb_entry tlb_table[] = { |
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/* TLB 0 - for temp stack in cache */ |
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
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MAS3_SX|MAS3_SW|MAS3_SR, 0, |
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0, 0, BOOKE_PAGESZ_4K, 0), |
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
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MAS3_SX|MAS3_SW|MAS3_SR, 0, |
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0, 0, BOOKE_PAGESZ_4K, 0), |
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
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MAS3_SX|MAS3_SW|MAS3_SR, 0, |
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0, 0, BOOKE_PAGESZ_4K, 0), |
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SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
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MAS3_SX|MAS3_SW|MAS3_SR, 0, |
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0, 0, BOOKE_PAGESZ_4K, 0), |
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|
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/* TLB 1 Initializations */ |
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/*
|
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* TLB 0, 1: 128M Non-cacheable, guarded |
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* 0xf8000000 128M FLASH |
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* Out of reset this entry is only 4K. |
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*/ |
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SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, |
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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0, 0, BOOKE_PAGESZ_64M, 1), |
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|
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SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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0, 1, BOOKE_PAGESZ_64M, 1), |
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|
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/*
|
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* TLB 2: 1G Non-cacheable, guarded |
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* 0x80000000 1G PCI1/PCIE 8,9,a,b |
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*/ |
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SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, |
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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0, 2, BOOKE_PAGESZ_1G, 1), |
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|
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/*
|
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* TLB 3, 4: 512M Non-cacheable, guarded |
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* 0xc0000000 1G PCI2 |
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*/ |
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SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, |
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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0, 3, BOOKE_PAGESZ_256M, 1), |
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|
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SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, |
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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0, 4, BOOKE_PAGESZ_256M, 1), |
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|
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/*
|
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* TLB 5: 64M Non-cacheable, guarded |
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* 0xe000_0000 1M CCSRBAR |
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* 0xe200_0000 1M PCI1 IO |
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* 0xe210_0000 1M PCI2 IO |
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* 0xe300_0000 1M PCIe IO |
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*/ |
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SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
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0, 5, BOOKE_PAGESZ_64M, 1), |
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}; |
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|
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int num_tlb_entries = ARRAY_SIZE(tlb_table); |
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@ -1,265 +0,0 @@ |
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/* |
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* Copyright 2004 Freescale Semiconductor. |
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* Copyright (C) 2002,2003, Motorola Inc. |
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* Xianghua Xiao <X.Xiao@motorola.com>
|
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* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4*1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8*1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12*1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12*1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 7: 16K Non-cacheable, guarded |
||||
* 0xf8000000 16K BCSR registers |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) |
||||
.long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/* |
||||
* TLB 8, 9: 128M DDR |
||||
* 0x00000000 64M DDR System memory |
||||
* 0x04000000 64M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
.long FSL_BOOKE_MAS0(1, 8, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1, 9, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
/* |
||||
* This is not so much the SDRAM map as it is the whole localbus map. |
||||
*/ |
||||
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
||||
|
||||
/* |
||||
* Rapid IO at 0xc000_0000 for 512 M |
||||
*/ |
||||
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x05
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4 |
||||
entry_end |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
/* This is not so much the SDRAM map as it is the whole localbus map. */ |
||||
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,130 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7: 16K Non-cacheable, guarded |
||||
* 0xf8000000 16K BCSR registers |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_16K, 1), |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* TLB 8, 9: 128M DDR |
||||
* 0x00000000 64M DDR System memory |
||||
* 0x04000000 64M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 8, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 9, BOOKE_PAGESZ_64M, 1), |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,243 +0,0 @@ |
||||
/* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright 2002,2003, Motorola Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xa0000000 256M PCI2 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xb0000000 256M PCI2 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
* 0xe300_0000 16M PCI2 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 7: 1M Non-cacheable, guarded |
||||
* 0xf8000000 1M CADMUS registers |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe20f_ffff PCI1 IO 1M |
||||
* 0xe210_0000 0xe21f_ffff PCI2 IO 1M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M |
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* The defines below are 1-off of the actual LAWAR0 usage. |
||||
* So LAWAR3 define uses the LAWAR4 register in the ECM. |
||||
*/ |
||||
|
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
|
||||
law_entry: |
||||
entry_start |
||||
.long 6
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 |
||||
entry_end |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe20f_ffff PCI1 IO 1M |
||||
* 0xe210_0000 0xe21f_ffff PCI2 IO 1M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M |
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), |
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,112 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xa0000000 256M PCI2 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xb0000000 256M PCI2 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
* 0xe300_0000 16M PCI2 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7: 1M Non-cacheable, guarded |
||||
* 0xf8000000 1M CADMUS registers |
||||
*/ |
||||
SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_1M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,222 +0,0 @@ |
||||
/* |
||||
* Copyright 2007 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long (2f-1f)/16 |
||||
1: |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, guarded |
||||
* Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 1G Non-cacheable, guarded |
||||
* 0x80000000 1G PCIE 8,9,a,b |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) |
||||
.long FSL_BOOKE_MAS2(CFG_PCIE_PHYS, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCIE_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI_PHYS + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe100_0000 255M PCI IO range |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#ifdef CFG_LBC_CACHE_BASE |
||||
/* |
||||
* TLB 5: 64M Cacheable, non-guarded |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
/* |
||||
* TLB 6: 64M Non-cacheable, guarded |
||||
* 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
2: |
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* LAW 0 is reserved for boot mapping |
||||
*/ |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
|
||||
.long (4f-3f)/8 |
||||
3: |
||||
.long 0
|
||||
.long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN |
||||
|
||||
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
|
||||
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) |
||||
|
||||
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) |
||||
|
||||
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) |
||||
|
||||
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) |
||||
|
||||
.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
|
||||
.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) |
||||
|
||||
/* contains both PCIE3 MEM & IO space */ |
||||
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) |
||||
4: |
||||
entry_end |
||||
@ -0,0 +1,42 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(4, CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
SET_LAW_ENTRY(5, CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), |
||||
SET_LAW_ENTRY(6, CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), |
||||
SET_LAW_ENTRY(7, CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), |
||||
SET_LAW_ENTRY(8, CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), |
||||
/* contains both PCIE3 MEM & IO space */ |
||||
SET_LAW_ENTRY(9, CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,99 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
/*
|
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_64M, 1), |
||||
/*
|
||||
* TLB 1: 1G Non-cacheable, guarded |
||||
* 0x80000000 1G PCIE 8,9,a,b |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCIE_PHYS, CFG_PCIE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI_PHYS + 0x10000000, CFG_PCI_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe100_0000 255M PCI IO range |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
#ifdef CFG_LBC_CACHE_BASE |
||||
/*
|
||||
* TLB 5: 64M Cacheable, non-guarded |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
#endif |
||||
/*
|
||||
* TLB 6: 64M Non-cacheable, guarded |
||||
* 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,252 +0,0 @@ |
||||
/* |
||||
* Copyright 2004, 2007 Freescale Semiconductor. |
||||
* Copyright 2002,2003, Motorola Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long (2f-1f)/16 |
||||
|
||||
1: |
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, guarded |
||||
* Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, (MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, (MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, (MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, (MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_BOOT_BLOCK, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_BOOT_BLOCK, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 1G Non-cacheable, guarded |
||||
* 0x80000000 1G PCI1/PCIE 8,9,a,b |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI_PHYS, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#ifdef CFG_RIO_MEM_PHYS |
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 1M PCI1 IO |
||||
* 0xe210_0000 1M PCI2 IO |
||||
* 0xe300_0000 1M PCIe IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_CACHE_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_CACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 7: 64M Non-cacheable, guarded |
||||
* 0xf8000000 64M CADMUS registers, relocated L2SRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_NONCACHE_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
2: |
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe10f_ffff PCI1 IO 1M |
||||
* 0xe280_0000 0xe20f_ffff PCI2 IO 1M |
||||
* 0xe300_0000 0xe30f_ffff PCIe IO 1M |
||||
* 0xf000_0000 0xf3ff_ffff SDRAM 64M |
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M |
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* LAW 0 is reserved for boot mapping |
||||
*/ |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
|
||||
.long (4f-3f)/8 |
||||
3: |
||||
.long 0
|
||||
.long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN |
||||
|
||||
#ifdef CFG_PCI1_MEM_PHYS |
||||
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
|
||||
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M) |
||||
#endif |
||||
|
||||
#ifdef CFG_PCI2_MEM_PHYS |
||||
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
|
||||
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M) |
||||
#endif |
||||
|
||||
#ifdef CFG_PCIE1_MEM_PHYS |
||||
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
|
||||
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M) |
||||
#endif |
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) |
||||
|
||||
#ifdef CFG_RIO_MEM_PHYS |
||||
.long (CFG_RIO_MEM_PHYS>>12) & 0xfffff |
||||
.long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M) |
||||
#endif |
||||
4: |
||||
entry_end |
||||
@ -0,0 +1,73 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe10f_ffff PCI1 IO 1M |
||||
* 0xe280_0000 0xe20f_ffff PCI2 IO 1M |
||||
* 0xe300_0000 0xe30f_ffff PCIe IO 1M |
||||
* 0xf000_0000 0xf3ff_ffff SDRAM 64M |
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M |
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* LAW 0 is reserved for boot mapping |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifdef CFG_PCI1_MEM_PHYS |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), |
||||
#endif |
||||
#ifdef CFG_PCI2_MEM_PHYS |
||||
SET_LAW_ENTRY(4, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), |
||||
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), |
||||
#endif |
||||
#ifdef CFG_PCIE1_MEM_PHYS |
||||
SET_LAW_ENTRY(6, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), |
||||
SET_LAW_ENTRY(7, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), |
||||
#endif |
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
SET_LAW_ENTRY(8, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
#ifdef CFG_RIO_MEM_PHYS |
||||
SET_LAW_ENTRY(9, CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
#endif |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,104 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 1G Non-cacheable, guarded |
||||
* 0x80000000 1G PCI1/PCIE 8,9,a,b |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
#ifdef CFG_RIO_MEM_PHYS |
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
#endif |
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 1M PCI1 IO |
||||
* 0xe210_0000 1M PCI2 IO |
||||
* 0xe300_0000 1M PCIe IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7: 64M Non-cacheable, guarded |
||||
* 0xf8000000 64M CADMUS registers, relocated L2SRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_64M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,243 +0,0 @@ |
||||
/* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright 2002,2003, Motorola Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xa0000000 256M PCI2 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xb0000000 256M PCI2 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
* 0xe300_0000 16M PCI2 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 7: 1M Non-cacheable, guarded |
||||
* 0xf8000000 1M CADMUS registers |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(CADMUS_BASE_ADDR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CADMUS_BASE_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe20f_ffff PCI1 IO 1M |
||||
* 0xe210_0000 0xe21f_ffff PCI2 IO 1M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M |
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* The defines below are 1-off of the actual LAWAR0 usage. |
||||
* So LAWAR3 define uses the LAWAR4 register in the ECM. |
||||
*/ |
||||
|
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
|
||||
law_entry: |
||||
entry_start |
||||
.long 6
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 |
||||
entry_end |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe20f_ffff PCI1 IO 1M |
||||
* 0xe210_0000 0xe21f_ffff PCI2 IO 1M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M |
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), |
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
SET_LAW_ENTRY(6, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,112 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xa0000000 256M PCI2 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xb0000000 256M PCI2 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
* 0xe300_0000 16M PCI2 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7: 1M Non-cacheable, guarded |
||||
* 0xf8000000 1M CADMUS registers |
||||
*/ |
||||
SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_1M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,266 +0,0 @@ |
||||
/* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 7: 16K Non-cacheable, guarded |
||||
* 0xf8000000 16K BCSR registers |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K) |
||||
.long FSL_BOOKE_MAS2(CFG_BCSR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_BCSR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/* |
||||
* TLB 8, 9: 128M DDR |
||||
* 0x00000000 64M DDR System memory |
||||
* 0x04000000 64M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
.long FSL_BOOKE_MAS0(1, 8, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1, 9, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
/* |
||||
* This is not so much the SDRAM map as it is the whole localbus map. |
||||
*/ |
||||
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) |
||||
|
||||
/* |
||||
* Rapid IO at 0xc000_0000 for 512 M |
||||
*/ |
||||
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x05
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4 |
||||
entry_end |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
/* This is not so much the SDRAM map as it is the whole localbus map. */ |
||||
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,130 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7: 16K Non-cacheable, guarded |
||||
* 0xf8000000 16K BCSR registers |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_16K, 1), |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* TLB 8, 9: 128M DDR |
||||
* 0x00000000 64M DDR System memory |
||||
* 0x04000000 64M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 8, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 9, BOOKE_PAGESZ_64M, 1), |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,236 +0,0 @@ |
||||
/* |
||||
* Copyright 2004-2007 Freescale Semiconductor. |
||||
* Copyright 2002,2003, Motorola Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long (2f-1f)/16 |
||||
|
||||
1: |
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* TLB 1 Initializations */ |
||||
/* |
||||
* TLBe 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH (upper half) |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE + 0x1000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE + 0x1000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLBe 1: 16M Non-cacheable, guarded |
||||
* 0xfe000000 16M FLASH (lower half) |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLBe 2: 1G Non-cacheable, guarded |
||||
* 0x80000000 512M PCI1 MEM |
||||
* 0xa0000000 512M PCIe MEM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLBe 3: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 8M PCI1 IO |
||||
* 0xe280_0000 8M PCIe IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLBe 4: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLBe 5: 256K Non-cacheable, guarded |
||||
* 0xf8000000 32K BCSR |
||||
* 0xf8008000 32K PIB (CS4) |
||||
* 0xf8010000 32K PIB (CS5) |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K) |
||||
.long FSL_BOOKE_MAS2(CFG_BCSR_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_BCSR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
2: |
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
*0) 0x0000_0000 0x7fff_ffff DDR 2G |
||||
*1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB |
||||
*2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB |
||||
*-) 0xe000_0000 0xe00f_ffff CCSR 1M |
||||
*3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M |
||||
*4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M |
||||
*5) 0xc000_0000 0xdfff_ffff SRIO 512MB |
||||
*6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB |
||||
*6.b) 0xf800_0000 0xf800_7fff BCSR 32KB |
||||
*6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB |
||||
*6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB |
||||
*6.e) 0xfe00_0000 0xffff_ffff Flash 32MB |
||||
* |
||||
*Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* The defines below are 1-off of the actual LAWAR0 usage. |
||||
* So LAWAR3 define uses the LAWAR4 register in the ECM. |
||||
*/ |
||||
|
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) |
||||
|
||||
#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M)) |
||||
|
||||
#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ |
||||
#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
|
||||
law_entry: |
||||
entry_start |
||||
.long (4f-3f)/8 |
||||
3: |
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6 |
||||
4: |
||||
entry_end |
||||
@ -0,0 +1,62 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
*0) 0x0000_0000 0x7fff_ffff DDR 2G |
||||
*1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB |
||||
*2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB |
||||
*-) 0xe000_0000 0xe00f_ffff CCSR 1M |
||||
*3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M |
||||
*4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M |
||||
*5) 0xc000_0000 0xdfff_ffff SRIO 512MB |
||||
*6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB |
||||
*6.b) 0xf800_0000 0xf800_7fff BCSR 32KB |
||||
*6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB |
||||
*6.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB |
||||
*6.e) 0xfe00_0000 0xffff_ffff Flash 32MB |
||||
* |
||||
*Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), |
||||
SET_LAW_ENTRY(6, CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ |
||||
SET_LAW_ENTRY(7, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,100 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 Initializations */ |
||||
/*
|
||||
* TLBe 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH (upper half) |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x1000000, CFG_FLASH_BASE + 0x1000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLBe 1: 16M Non-cacheable, guarded |
||||
* 0xfe000000 16M FLASH (lower half) |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLBe 2: 1G Non-cacheable, guarded |
||||
* 0x80000000 512M PCI1 MEM |
||||
* 0xa0000000 512M PCIe MEM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/*
|
||||
* TLBe 3: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 8M PCI1 IO |
||||
* 0xe280_0000 8M PCIe IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLBe 4: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 4, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLBe 5: 256K Non-cacheable, guarded |
||||
* 0xf8000000 32K BCSR |
||||
* 0xf8008000 32K PIB (CS4) |
||||
* 0xf8010000 32K PIB (CS5) |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_BCSR_BASE, CFG_BCSR_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256K, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,178 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
/* TLB1 entries configuration: */ |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
.long 0x0a /* the following data table uses a few of 16 TLB entries */ |
||||
|
||||
.long FSL_BOOKE_MAS0(1,1,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if defined(CFG_FLASH_PORT_WIDTH_16) |
||||
.long FSL_BOOKE_MAS0(1,2,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,3,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x400000,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x400000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
.long FSL_BOOKE_MAS0(1,2,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,3,0) |
||||
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(0,0) |
||||
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
.long FSL_BOOKE_MAS0(1,4,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,5,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x4000000,0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x4000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
.long FSL_BOOKE_MAS0(1,4,0) |
||||
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(0,0) |
||||
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,5,0) |
||||
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(0,0) |
||||
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
.long FSL_BOOKE_MAS0(1,6,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) |
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,(MAS2_I|MAS2_G)) |
||||
#else |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE,0) |
||||
#endif |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,7,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) |
||||
#ifdef CONFIG_L2_INIT_RAM |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0) |
||||
#else |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0) |
||||
#endif |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,8,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,9,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) |
||||
.long FSL_BOOKE_MAS2(CFG_BCSR,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_BCSR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
.long FSL_BOOKE_MAS0(1,15,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
.long FSL_BOOKE_MAS0(1,15,0) |
||||
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(0,0) |
||||
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
entry_end |
||||
|
||||
/* LAW(Local Access Window) configuration: |
||||
* 0000_0000-0800_0000: DDR(128M) -or- larger |
||||
* f000_0000-f3ff_ffff: PCI(256M) |
||||
* f400_0000-f7ff_ffff: RapidIO(128M) |
||||
* f800_0000-ffff_ffff: localbus(128M) |
||||
* f800_0000-fbff_ffff: LBC SDRAM(64M) |
||||
* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) |
||||
* fdf0_0000-fdff_ffff: CCSRBAR(1M) |
||||
* fe00_0000-ffff_ffff: Flash(32M) |
||||
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access |
||||
* Window. |
||||
* Note: If flash is 8M at default position(last 8M),no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#if !defined(CONFIG_RAM_AS_FLASH) |
||||
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR2 0 |
||||
#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x03
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 |
||||
entry_end |
||||
@ -0,0 +1,54 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/* LAW(Local Access Window) configuration:
|
||||
* 0000_0000-0800_0000: DDR(128M) -or- larger |
||||
* f000_0000-f3ff_ffff: PCI(256M) |
||||
* f400_0000-f7ff_ffff: RapidIO(128M) |
||||
* f800_0000-ffff_ffff: localbus(128M) |
||||
* f800_0000-fbff_ffff: LBC SDRAM(64M) |
||||
* fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) |
||||
* fdf0_0000-fdff_ffff: CCSRBAR(1M) |
||||
* fe00_0000-ffff_ffff: Flash(32M) |
||||
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access |
||||
* Window. |
||||
* Note: If flash is 8M at default position(last 8M),no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), |
||||
#ifndef CONFIG_RAM_AS_FLASH |
||||
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), |
||||
#endif |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,78 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
#if defined(CFG_FLASH_PORT_WIDTH_16) |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_4M, 1), |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x400000, CFG_FLASH_BASE + 0x400000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_4M, 1), |
||||
#else |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 4, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
#endif |
||||
|
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
#if defined(CONFIG_RAM_AS_FLASH) |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
#else |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
#endif |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 7, BOOKE_PAGESZ_16K, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 9, BOOKE_PAGESZ_16K, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,251 +0,0 @@ |
||||
/* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 64M FLASH (8,16,32 or 64 MB) |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/* |
||||
* TLB 7: 256M DDR |
||||
* 0x00000000 256M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
|
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
/* |
||||
* This is not so much the SDRAM map as it is the whole localbus map. |
||||
*/ |
||||
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
/* |
||||
* Rapid IO at 0xc000_0000 for 512 M |
||||
*/ |
||||
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x05
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4 |
||||
entry_end |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
/* This is not so much the SDRAM map as it is the whole localbus map. */ |
||||
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,117 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 64M FLASH (8,16,32 or 64 MB) |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* TLB 7: 256M DDR |
||||
* 0x00000000 256M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 7, BOOKE_PAGESZ_256M, 1), |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,251 +0,0 @@ |
||||
/* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 64M FLASH (8,16,32 or 64 MB) |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(0xfc000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(0xfc000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/* |
||||
* TLB 7: 256M DDR |
||||
* 0x00000000 256M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
|
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
/* |
||||
* This is not so much the SDRAM map as it is the whole localbus map. |
||||
*/ |
||||
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
/* |
||||
* Rapid IO at 0xc000_0000 for 512 M |
||||
*/ |
||||
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x05
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4 |
||||
entry_end |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
/* This is not so much the SDRAM map as it is the whole localbus map. */ |
||||
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,117 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 64M FLASH (8,16,32 or 64 MB) |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* TLB 7: 256M DDR |
||||
* 0x00000000 256M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 7, BOOKE_PAGESZ_256M, 1), |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,241 +0,0 @@ |
||||
/* |
||||
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> |
||||
* Copyright 2007 Embedded Specialties, Inc. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright 2002,2003, Motorola Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xe4010000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff800000 16M TLB for 8MB FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, |
||||
(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Cacheable, non-guarded |
||||
* 0x0 256M DDR SDRAM |
||||
*/ |
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
/* |
||||
* TLB 4: 64M Non-cacheable, guarded |
||||
* 0xe0000000 1M CCSRBAR |
||||
* 0xe2000000 16M PCI1 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Cacheable, non-guarded |
||||
* 0xf0000000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 16M Cacheable, non-guarded |
||||
* 0xf8000000 1M 7-segment LED display |
||||
* 0xf8100000 1M User switches |
||||
* 0xf8300000 1M Board revision |
||||
* 0xf8b00000 1M EEPROM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x0fff_ffff DDR 256M |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M |
||||
* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
* |
||||
* The defines below are 1-off of the actual LAWAR0 usage. |
||||
* So LAWAR3 define uses the LAWAR4 register in the ECM. |
||||
*/ |
||||
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
|
||||
law_entry: |
||||
entry_start |
||||
.long 4
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
entry_end |
||||
@ -0,0 +1,57 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x0fff_ffff DDR 256M |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xf8b0_0000 0xf80f_ffff EEPROM 1M |
||||
* 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M |
||||
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
||||
SET_LAW_ENTRY(4, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,108 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff800000 16M TLB for 8MB FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Cacheable, non-guarded |
||||
* 0x0 256M DDR SDRAM |
||||
*/ |
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
#endif |
||||
|
||||
/*
|
||||
* TLB 4: 64M Non-cacheable, guarded |
||||
* 0xe0000000 1M CCSRBAR |
||||
* 0xe2000000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Cacheable, non-guarded |
||||
* 0xf0000000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 16M Cacheable, non-guarded |
||||
* 0xf8000000 1M 7-segment LED display |
||||
* 0xf8100000 1M User switches |
||||
* 0xf8300000 1M Board revision |
||||
* 0xf8b00000 1M EEPROM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_EPLD_BASE, CFG_EPLD_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_16M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,165 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. |
||||
* Added support for Wind River SBC8560 board |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
/* LAW(Local Access Window) configuration: |
||||
* 0000_0000-0800_0000: DDR(512M) -or- larger |
||||
* c000_0000-cfff_ffff: PCI(256M) |
||||
* d000_0000-dfff_ffff: RapidIO(256M) |
||||
* e000_0000-ffff_ffff: localbus(512M) |
||||
* e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 |
||||
* e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 |
||||
* e800_0000-efff_ffff: LBC 128M, nothing here |
||||
* f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 |
||||
* f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 |
||||
* f800_0000-fdff_ffff: LBC 64M, nothing here |
||||
* fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 |
||||
* fd00_0000-fdff_ffff: LBC 16M, nothing here |
||||
* fe00_0000-feff_ffff: LBC 16M, nothing here |
||||
* ff00_0000-ff6f_ffff: LBC 7M, nothing here |
||||
* ff70_0000-ff7f_ffff: CCSRBAR 1M |
||||
* ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 |
||||
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access |
||||
* Window. |
||||
* Note: If flash is 8M at default position(last 8M),no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#define LAWBAR2 ((0xe0000000>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x03
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 |
||||
entry_end |
||||
|
||||
/* TLB1 entries configuration: */ |
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
.long 0x08 /* the following data table uses a few of 16 TLB entries */ |
||||
|
||||
/* TLB for CCSRBAR (IMMR) */ |
||||
|
||||
.long FSL_BOOKE_MAS0(1,1,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* TLB for Local Bus stuff, just map the whole 512M */ |
||||
/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ |
||||
|
||||
.long FSL_BOOKE_MAS0(1,2,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(0xe0000000,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(0xe0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,3,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(0xf0000000,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(0xf0000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
.long FSL_BOOKE_MAS0(1,4,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE,0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,5,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000,0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
.long FSL_BOOKE_MAS0(1,4,0) |
||||
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(0,0) |
||||
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,5,0) |
||||
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(0,0) |
||||
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
.long FSL_BOOKE_MAS0(1,6,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) |
||||
#ifdef CONFIG_L2_INIT_RAM |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0,0,0,1,0,0,0,0) |
||||
#else |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR,0) |
||||
#endif |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1,7,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI_MEM_BASE,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI_MEM_BASE,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
.long FSL_BOOKE_MAS0(1,15,0) |
||||
.long FSL_BOOKE_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT,(MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
.long FSL_BOOKE_MAS0(1,15,0) |
||||
.long FSL_BOOKE_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) |
||||
.long FSL_BOOKE_MAS2(0,0) |
||||
.long FSL_BOOKE_MAS3(0,0,(MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
entry_end |
||||
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/* LAW(Local Access Window) configuration:
|
||||
* 0000_0000-0800_0000: DDR(512M) -or- larger |
||||
* c000_0000-cfff_ffff: PCI(256M) |
||||
* d000_0000-dfff_ffff: RapidIO(256M) |
||||
* e000_0000-ffff_ffff: localbus(512M) |
||||
* e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6 |
||||
* e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1 |
||||
* e800_0000-efff_ffff: LBC 128M, nothing here |
||||
* f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3 |
||||
* f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4 |
||||
* f800_0000-fdff_ffff: LBC 64M, nothing here |
||||
* fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5 |
||||
* fd00_0000-fdff_ffff: LBC 16M, nothing here |
||||
* fe00_0000-feff_ffff: LBC 16M, nothing here |
||||
* ff00_0000-ff6f_ffff: LBC 7M, nothing here |
||||
* ff70_0000-ff7f_ffff: CCSRBAR 1M |
||||
* ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0 |
||||
* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access |
||||
* Window. |
||||
* Note: If flash is 8M at default position(last 8M),no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,65 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB for CCSRBAR (IMMR) */ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_1M, 1), |
||||
|
||||
/* TLB for Local Bus stuff, just map the whole 512M */ |
||||
/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */ |
||||
|
||||
SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
#endif |
||||
|
||||
SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_16K, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_256M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,272 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2004 Embedded Edge, LLC |
||||
* Dan Malek <dan@embeddededge.com>
|
||||
* Copied from ADS85xx. |
||||
* Updates for Silicon Tx GP3 8560. We only support 32-bit flash |
||||
* and DDR with SPD EEPROM configuration. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 7: 16K Non-cacheable, guarded |
||||
* 0xfc000000 16K Configuration Latch register |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64K) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_LCLDEVS_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_LCLDEVS_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/* |
||||
* TLB 8, 9: 128M DDR |
||||
* 0x00000000 64M DDR System memory |
||||
* 0x04000000 64M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
.long FSL_BOOKE_MAS0(1, 8, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(1, 9, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE + 0x4000000, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE + 0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#endif |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xfc00_0000 0xfc00_ffff Config Latch 64K |
||||
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
/* |
||||
* This is not so much the SDRAM map as it is the whole localbus map. |
||||
*/ |
||||
#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
/* |
||||
* Rapid IO at 0xc000_0000 for 512 M |
||||
*/ |
||||
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x05
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4 |
||||
entry_end |
||||
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
* 0xfc00_0000 0xfc00_ffff Config Latch 64K |
||||
* 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
/* This is not so much the SDRAM map as it is the whole localbus map. */ |
||||
SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,130 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 16M Non-cacheable, guarded |
||||
* 0xff000000 16M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Cacheable, non-guarded |
||||
* 0xf000_0000 64M LBC SDRAM |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7: 16K Non-cacheable, guarded |
||||
* 0xfc000000 16K Configuration Latch register |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_LCLDEVS_BASE, CFG_LBC_LCLDEVS_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_16K, 1), |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* TLB 8, 9: 128M DDR |
||||
* 0x00000000 64M DDR System memory |
||||
* 0x04000000 64M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 8, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 9, BOOKE_PAGESZ_64M, 1), |
||||
#endif |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,244 +0,0 @@ |
||||
/* |
||||
* Copyright (C) 2005 Embedded Alley Solutions, Inc. |
||||
* Dan Malek <dan@embeddedalley.com>
|
||||
* Copied from STx GP3. |
||||
* Updates for Silicon Tx GP3 SSA. We only support 32-bit flash |
||||
* and DDR with SPD EEPROM configuration. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 12
|
||||
|
||||
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
||||
/* |
||||
* TLB0 4K Non-cacheable, guarded |
||||
* 0xff700000 4K Initial CCSRBAR mapping |
||||
* |
||||
* This ends up at a TLB0 Index==0 entry, and must not collide |
||||
* with other TLB0 Entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
#else |
||||
#error("Update the number of table entries in tlb1_entry") |
||||
#endif |
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 6M4 FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xa0000000 256M PCI2 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xb0000000 256M PCI2 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
* 0xe300_0000 16M PCI2 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 256M Non-cacheable, guarded |
||||
* 0xf0000000 Local bus expansion option. |
||||
* 0xfb000000 Configuration Latch register (one word) |
||||
* 0xfc000000 Up to 64M flash |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M |
||||
* 0xf000_0000 0xfaff_ffff Local bus 128M |
||||
* 0xfb00_0000 0xfb00_ffff Config Latch 64K |
||||
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM) |
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
#else |
||||
#define LAWBAR0 0 |
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
||||
#endif |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
/* Map the whole localbus, including flash and reset latch. |
||||
*/ |
||||
#define LAWBAR5 ((CFG_LBC_OPTION_BASE>>12) & 0xfffff) |
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 6
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 |
||||
entry_end |
||||
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M |
||||
* 0xf000_0000 0xfaff_ffff Local bus 128M |
||||
* 0xfb00_0000 0xfb00_ffff Config Latch 64K |
||||
* 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), |
||||
#endif |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), |
||||
SET_LAW_ENTRY(3, CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), |
||||
SET_LAW_ENTRY(5, CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), |
||||
/* Map the whole localbus, including flash and reset latch. */ |
||||
SET_LAW_ENTRY(6, CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,106 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/*
|
||||
* TLB 0: 64M Non-cacheable, guarded |
||||
* 0xfc000000 6M4 FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0xa0000000 256M PCI2 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xb0000000 256M PCI2 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
* 0xe300_0000 16M PCI2 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 256M Non-cacheable, guarded |
||||
* 0xf0000000 Local bus expansion option. |
||||
* 0xfb000000 Configuration Latch register (one word) |
||||
* 0xfc000000 Up to 64M flash |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_LBC_OPTION_BASE, CFG_LBC_OPTION_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_256M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,222 +0,0 @@ |
||||
/* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright (C) 2002,2003, Motorola Inc. |
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <ppc_asm.tmpl> |
||||
#include <ppc_defs.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/mmu.h> |
||||
#include <config.h> |
||||
#include <mpc85xx.h> |
||||
|
||||
|
||||
/* |
||||
* TLB0 and TLB1 Entries |
||||
* |
||||
* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
||||
* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
||||
* these TLB entries are established. |
||||
* |
||||
* The TLB entries for DDR are dynamically setup in spd_sdram() |
||||
* and use TLB1 Entries 8 through 15 as needed according to the |
||||
* size of DDR memory. |
||||
* |
||||
* MAS0: tlbsel, esel, nv |
||||
* MAS1: valid, iprot, tid, ts, tsize |
||||
* MAS2: epn, x0, x1, w, i, m, g, e |
||||
* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
||||
*/ |
||||
|
||||
#define entry_start \ |
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \ |
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl tlb1_entry
|
||||
tlb1_entry: |
||||
entry_start |
||||
|
||||
/* |
||||
* Number of TLB0 and TLB1 entries in the following table |
||||
*/ |
||||
.long 13
|
||||
|
||||
/* |
||||
* TLB0 16K Cacheable, non-guarded |
||||
* 0xd001_0000 16K Temporary Global data for initialization |
||||
* |
||||
* Use four 4K TLB0 entries. These entries must be cacheable |
||||
* as they provide the bootstrap memory before the memory |
||||
* controler and real memory have been configured. |
||||
* |
||||
* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
||||
* and must not collide with other TLB0 entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
.long FSL_BOOKE_MAS0(0, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0) |
||||
.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0) |
||||
.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
|
||||
/* |
||||
* TLB 0, 1: 128M Non-cacheable, guarded |
||||
* 0xf8000000 128M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 1, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
.long FSL_BOOKE_MAS0(1, 0, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_FLASH_BASE+0x4000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_FLASH_BASE+0x4000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 2, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 3, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 4, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 5: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 5, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_RIO_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_RIO_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 6: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 6, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
||||
.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
/* |
||||
* TLB 7+8: 512M DDR, cache disabled (needed for memory test) |
||||
* 0x00000000 512M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
.long FSL_BOOKE_MAS0(1, 7, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
.long FSL_BOOKE_MAS0(1, 8, 0) |
||||
.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
||||
.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE+0x10000000, (MAS2_I|MAS2_G)) |
||||
.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE+0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) |
||||
|
||||
entry_end |
||||
|
||||
/* |
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) |
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff) |
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) |
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) |
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
||||
|
||||
/* |
||||
* Rapid IO at 0xc000_0000 for 512 M |
||||
*/ |
||||
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) |
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
||||
|
||||
|
||||
.section .bootpg, "ax" |
||||
.globl law_entry
|
||||
law_entry: |
||||
entry_start |
||||
.long 0x05
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
||||
.long LAWBAR4,LAWAR4 |
||||
entry_end |
||||
@ -0,0 +1,54 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration: |
||||
* |
||||
* 0x0000_0000 0x7fff_ffff DDR 2G |
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M |
||||
* 0xe000_0000 0xe000_ffff CCSR 1M |
||||
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
||||
* 0xf800_0000 0xf80f_ffff BCSR 1M |
||||
* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M |
||||
* |
||||
* Notes: |
||||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
||||
* If flash is 8M at default position (last 8M), no LAW needed. |
||||
*/ |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), |
||||
SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), |
||||
SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), |
||||
SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,114 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
|
||||
/*
|
||||
* TLB 0, 1: 128M Non-cacheable, guarded |
||||
* 0xf8000000 128M FLASH |
||||
* Out of reset this entry is only 4K. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_64M, 1), |
||||
SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded |
||||
* 0x80000000 256M PCI1 MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 3: 256M Non-cacheable, guarded |
||||
* 0x90000000 256M PCI1 MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 4: 256M Non-cacheable, guarded |
||||
* 0xc0000000 256M Rapid IO MEM First half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 5: 256M Non-cacheable, guarded |
||||
* 0xd0000000 256M Rapid IO MEM Second half |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 5, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
/*
|
||||
* TLB 6: 64M Non-cacheable, guarded |
||||
* 0xe000_0000 1M CCSRBAR |
||||
* 0xe200_0000 16M PCI1 IO |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_64M, 1), |
||||
|
||||
/*
|
||||
* TLB 7+8: 512M DDR, cache disabled (needed for memory test) |
||||
* 0x00000000 512M DDR System memory |
||||
* Without SPD EEPROM configured DDR, this must be setup manually. |
||||
* Make sure the TLB count at the top of this table is correct. |
||||
* Likely it needs to be increased by two for these entries. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 7, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_256M, 1), |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -0,0 +1,93 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
void set_tlb(u8 tlb, u32 epn, u64 rpn, |
||||
u8 perms, u8 wimge, |
||||
u8 ts, u8 esel, u8 tsize, u8 iprot) |
||||
{ |
||||
u32 _mas0, _mas1, _mas2, _mas3, _mas7; |
||||
|
||||
_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); |
||||
_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); |
||||
_mas2 = FSL_BOOKE_MAS2(epn, wimge); |
||||
_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms); |
||||
_mas7 = rpn >> 32; |
||||
|
||||
mtspr(MAS0, _mas0); |
||||
mtspr(MAS1, _mas1); |
||||
mtspr(MAS2, _mas2); |
||||
mtspr(MAS3, _mas3); |
||||
#ifdef CONFIG_ENABLE_36BIT_PHYS |
||||
mtspr(MAS7, _mas7); |
||||
#endif |
||||
asm volatile("isync;msync;tlbwe;isync"); |
||||
} |
||||
|
||||
void disable_tlb(u8 esel) |
||||
{ |
||||
u32 _mas0, _mas1, _mas2, _mas3, _mas7; |
||||
|
||||
_mas0 = FSL_BOOKE_MAS0(1, esel, 0); |
||||
_mas1 = 0; |
||||
_mas2 = 0; |
||||
_mas3 = 0; |
||||
_mas7 = 0; |
||||
|
||||
mtspr(MAS0, _mas0); |
||||
mtspr(MAS1, _mas1); |
||||
mtspr(MAS2, _mas2); |
||||
mtspr(MAS3, _mas3); |
||||
#ifdef CONFIG_ENABLE_36BIT_PHYS |
||||
mtspr(MAS7, _mas7); |
||||
#endif |
||||
asm volatile("isync;msync;tlbwe;isync"); |
||||
} |
||||
|
||||
void invalidate_tlb(u8 tlb) |
||||
{ |
||||
if (tlb == 0) |
||||
mtspr(MMUCSR0, 0x4); |
||||
if (tlb == 1) |
||||
mtspr(MMUCSR0, 0x2); |
||||
} |
||||
|
||||
void init_tlbs(void) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < num_tlb_entries; i++) { |
||||
set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn, |
||||
tlb_table[i].perms, tlb_table[i].wimge, |
||||
tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize, |
||||
tlb_table[i].iprot); |
||||
} |
||||
|
||||
return ; |
||||
} |
||||
|
||||
@ -0,0 +1,70 @@ |
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc. |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define LAWAR_EN 0x80000000 |
||||
|
||||
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) |
||||
{ |
||||
volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); |
||||
volatile u32 *lawbar = base + 8 * idx; |
||||
volatile u32 *lawar = base + 8 * idx + 2; |
||||
|
||||
out_be32(lawbar, addr >> 12); |
||||
out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); |
||||
|
||||
return ; |
||||
} |
||||
|
||||
void disable_law(u8 idx) |
||||
{ |
||||
volatile u32 *base = (volatile u32 *)(CFG_IMMR + 0xc08); |
||||
volatile u32 *lawbar = base + 8 * idx; |
||||
volatile u32 *lawar = base + 8 * idx + 2; |
||||
|
||||
out_be32(lawar, 0); |
||||
out_be32(lawbar, 0); |
||||
|
||||
return; |
||||
} |
||||
|
||||
void init_laws(void) |
||||
{ |
||||
int i; |
||||
u8 law_idx = 0; |
||||
|
||||
for (i = 0; i < num_law_entries; i++) { |
||||
if (law_table[i].index != -1) |
||||
law_idx = law_table[i].index; |
||||
|
||||
set_law(law_idx++, law_table[i].addr, |
||||
law_table[i].size, law_table[i].trgt_id); |
||||
} |
||||
|
||||
return ; |
||||
} |
||||
@ -0,0 +1,80 @@ |
||||
#ifndef _FSL_LAW_H_ |
||||
#define _FSL_LAW_H_ |
||||
|
||||
#include <asm/io.h> |
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) |
||||
#define SET_LAW_ENTRY(idx, a, sz, trgt) \ |
||||
{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt } |
||||
|
||||
enum law_size { |
||||
LAW_SIZE_4K = 0xb, |
||||
LAW_SIZE_8K, |
||||
LAW_SIZE_16K, |
||||
LAW_SIZE_32K, |
||||
LAW_SIZE_64K, |
||||
LAW_SIZE_128K, |
||||
LAW_SIZE_256K, |
||||
LAW_SIZE_512K, |
||||
LAW_SIZE_1M, |
||||
LAW_SIZE_2M, |
||||
LAW_SIZE_4M, |
||||
LAW_SIZE_8M, |
||||
LAW_SIZE_16M, |
||||
LAW_SIZE_32M, |
||||
LAW_SIZE_64M, |
||||
LAW_SIZE_128M, |
||||
LAW_SIZE_256M, |
||||
LAW_SIZE_512M, |
||||
LAW_SIZE_1G, |
||||
LAW_SIZE_2G, |
||||
LAW_SIZE_4G, |
||||
LAW_SIZE_8G, |
||||
LAW_SIZE_16G, |
||||
LAW_SIZE_32G, |
||||
}; |
||||
|
||||
enum law_trgt_if { |
||||
LAW_TRGT_IF_PCI = 0x00, |
||||
LAW_TRGT_IF_PCI_2 = 0x01, |
||||
#ifndef CONFIG_MPC8641 |
||||
LAW_TRGT_IF_PCIE_1 = 0x02, |
||||
#endif |
||||
#ifndef CONFIG_MPC8572 |
||||
LAW_TRGT_IF_PCIE_3 = 0x03, |
||||
#endif |
||||
LAW_TRGT_IF_LBC = 0x04, |
||||
LAW_TRGT_IF_CCSR = 0x08, |
||||
LAW_TRGT_IF_DDR_INTRLV = 0x0b, |
||||
LAW_TRGT_IF_RIO = 0x0c, |
||||
LAW_TRGT_IF_DDR = 0x0f, |
||||
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ |
||||
}; |
||||
#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR |
||||
#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI |
||||
#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI |
||||
#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 |
||||
|
||||
#ifdef CONFIG_MPC8641 |
||||
#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC8572 |
||||
#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI |
||||
#endif |
||||
|
||||
struct law_entry { |
||||
int index; |
||||
phys_addr_t addr; |
||||
enum law_size size; |
||||
enum law_trgt_if trgt_id; |
||||
}; |
||||
|
||||
extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); |
||||
extern void disable_law(u8 idx); |
||||
extern void init_laws(void); |
||||
|
||||
/* define in board code */ |
||||
extern struct law_entry law_table[]; |
||||
extern int num_law_entries; |
||||
#endif |
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue