Import k2hk specific DT files from Linux Kernel and enable OF_CONTROL, DM, DM_SERIAL. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>master
parent
8a9bb065da
commit
391839fb04
@ -0,0 +1,425 @@ |
||||
/* |
||||
* Copyright 2013-2014 Texas Instruments, Inc. |
||||
* |
||||
* Keystone 2 Kepler/Hawking SoC clock nodes |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
clocks { |
||||
armpllclk: armpllclk@2620370 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,pll-clock"; |
||||
clocks = <&refclkarm>; |
||||
clock-output-names = "arm-pll-clk"; |
||||
reg = <0x02620370 4>; |
||||
reg-names = "control"; |
||||
}; |
||||
|
||||
mainpllclk: mainpllclk@2310110 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,main-pll-clock"; |
||||
clocks = <&refclksys>; |
||||
reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; |
||||
reg-names = "control", "multiplier", "post-divider"; |
||||
}; |
||||
|
||||
papllclk: papllclk@2620358 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,pll-clock"; |
||||
clocks = <&refclkpass>; |
||||
clock-output-names = "papllclk"; |
||||
reg = <0x02620358 4>; |
||||
reg-names = "control"; |
||||
}; |
||||
|
||||
ddr3apllclk: ddr3apllclk@2620360 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,pll-clock"; |
||||
clocks = <&refclkddr3a>; |
||||
clock-output-names = "ddr-3a-pll-clk"; |
||||
reg = <0x02620360 4>; |
||||
reg-names = "control"; |
||||
}; |
||||
|
||||
ddr3bpllclk: ddr3bpllclk@2620368 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,pll-clock"; |
||||
clocks = <&refclkddr3b>; |
||||
clock-output-names = "ddr-3b-pll-clk"; |
||||
reg = <0x02620368 4>; |
||||
reg-names = "control"; |
||||
}; |
||||
|
||||
clktsip: clktsip { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk16>; |
||||
clock-output-names = "tsip"; |
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <0>; |
||||
}; |
||||
|
||||
clksrio: clksrio { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk1rstiso13>; |
||||
clock-output-names = "srio"; |
||||
reg = <0x0235002c 0xb00>, <0x02350010 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <4>; |
||||
}; |
||||
|
||||
clkhyperlink0: clkhyperlink0 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk12>; |
||||
clock-output-names = "hyperlink-0"; |
||||
reg = <0x02350030 0xb00>, <0x02350014 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <5>; |
||||
}; |
||||
|
||||
clkgem1: clkgem1 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk1>; |
||||
clock-output-names = "gem1"; |
||||
reg = <0x02350040 0xb00>, <0x02350024 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <9>; |
||||
}; |
||||
|
||||
clkgem2: clkgem2 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk1>; |
||||
clock-output-names = "gem2"; |
||||
reg = <0x02350044 0xb00>, <0x02350028 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <10>; |
||||
}; |
||||
|
||||
clkgem3: clkgem3 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk1>; |
||||
clock-output-names = "gem3"; |
||||
reg = <0x02350048 0xb00>, <0x0235002c 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <11>; |
||||
}; |
||||
|
||||
clkgem4: clkgem4 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk1>; |
||||
clock-output-names = "gem4"; |
||||
reg = <0x0235004c 0xb00>, <0x02350030 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <12>; |
||||
}; |
||||
|
||||
clkgem5: clkgem5 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk1>; |
||||
clock-output-names = "gem5"; |
||||
reg = <0x02350050 0xb00>, <0x02350034 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <13>; |
||||
}; |
||||
|
||||
clkgem6: clkgem6 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk1>; |
||||
clock-output-names = "gem6"; |
||||
reg = <0x02350054 0xb00>, <0x02350038 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <14>; |
||||
}; |
||||
|
||||
clkgem7: clkgem7 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk1>; |
||||
clock-output-names = "gem7"; |
||||
reg = <0x02350058 0xb00>, <0x0235003c 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <15>; |
||||
}; |
||||
|
||||
clkddr31: clkddr31 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "ddr3-1"; |
||||
reg = <0x02350060 0xb00>, <0x02350040 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <16>; |
||||
}; |
||||
|
||||
clktac: clktac { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "tac"; |
||||
reg = <0x02350064 0xb00>, <0x02350044 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <17>; |
||||
}; |
||||
|
||||
clkrac01: clkrac01 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "rac-01"; |
||||
reg = <0x02350068 0xb00>, <0x02350044 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <17>; |
||||
}; |
||||
|
||||
clkrac23: clkrac23 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "rac-23"; |
||||
reg = <0x0235006c 0xb00>, <0x02350048 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <18>; |
||||
}; |
||||
|
||||
clkfftc0: clkfftc0 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "fftc-0"; |
||||
reg = <0x02350070 0xb00>, <0x0235004c 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <19>; |
||||
}; |
||||
|
||||
clkfftc1: clkfftc1 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "fftc-1"; |
||||
reg = <0x02350074 0xb00>, <0x0235004c 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <19>; |
||||
}; |
||||
|
||||
clkfftc2: clkfftc2 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "fftc-2"; |
||||
reg = <0x02350078 0xb00>, <0x02350050 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <20>; |
||||
}; |
||||
|
||||
clkfftc3: clkfftc3 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "fftc-3"; |
||||
reg = <0x0235007c 0xb00>, <0x02350050 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <20>; |
||||
}; |
||||
|
||||
clkfftc4: clkfftc4 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "fftc-4"; |
||||
reg = <0x02350080 0xb00>, <0x02350050 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <20>; |
||||
}; |
||||
|
||||
clkfftc5: clkfftc5 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "fftc-5"; |
||||
reg = <0x02350084 0xb00>, <0x02350050 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <20>; |
||||
}; |
||||
|
||||
clkaif: clkaif { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "aif"; |
||||
reg = <0x02350088 0xb00>, <0x02350054 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <21>; |
||||
}; |
||||
|
||||
clktcp3d0: clktcp3d0 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "tcp3d-0"; |
||||
reg = <0x0235008c 0xb00>, <0x02350058 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <22>; |
||||
}; |
||||
|
||||
clktcp3d1: clktcp3d1 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "tcp3d-1"; |
||||
reg = <0x02350090 0xb00>, <0x02350058 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <22>; |
||||
}; |
||||
|
||||
clktcp3d2: clktcp3d2 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "tcp3d-2"; |
||||
reg = <0x02350094 0xb00>, <0x0235005c 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <23>; |
||||
}; |
||||
|
||||
clktcp3d3: clktcp3d3 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "tcp3d-3"; |
||||
reg = <0x02350098 0xb00>, <0x0235005c 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <23>; |
||||
}; |
||||
|
||||
clkvcp0: clkvcp0 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "vcp-0"; |
||||
reg = <0x0235009c 0xb00>, <0x02350060 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <24>; |
||||
}; |
||||
|
||||
clkvcp1: clkvcp1 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "vcp-1"; |
||||
reg = <0x023500a0 0xb00>, <0x02350060 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <24>; |
||||
}; |
||||
|
||||
clkvcp2: clkvcp2 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "vcp-2"; |
||||
reg = <0x023500a4 0xb00>, <0x02350060 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <24>; |
||||
}; |
||||
|
||||
clkvcp3: clkvcp3 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "vcp-3"; |
||||
reg = <0x023500a8 0xb00>, <0x02350060 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <24>; |
||||
}; |
||||
|
||||
clkvcp4: clkvcp4 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "vcp-4"; |
||||
reg = <0x023500ac 0xb00>, <0x02350064 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <25>; |
||||
}; |
||||
|
||||
clkvcp5: clkvcp5 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "vcp-5"; |
||||
reg = <0x023500b0 0xb00>, <0x02350064 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <25>; |
||||
}; |
||||
|
||||
clkvcp6: clkvcp6 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "vcp-6"; |
||||
reg = <0x023500b4 0xb00>, <0x02350064 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <25>; |
||||
}; |
||||
|
||||
clkvcp7: clkvcp7 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "vcp-7"; |
||||
reg = <0x023500b8 0xb00>, <0x02350064 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <25>; |
||||
}; |
||||
|
||||
clkbcp: clkbcp { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "bcp"; |
||||
reg = <0x023500bc 0xb00>, <0x02350068 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <26>; |
||||
}; |
||||
|
||||
clkdxb: clkdxb { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "dxb"; |
||||
reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <27>; |
||||
}; |
||||
|
||||
clkhyperlink1: clkhyperlink1 { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk12>; |
||||
clock-output-names = "hyperlink-1"; |
||||
reg = <0x023500c4 0xb00>, <0x02350070 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <28>; |
||||
}; |
||||
|
||||
clkxge: clkxge { |
||||
#clock-cells = <0>; |
||||
compatible = "ti,keystone,psc-clock"; |
||||
clocks = <&chipclk13>; |
||||
clock-output-names = "xge"; |
||||
reg = <0x023500c8 0xb00>, <0x02350074 0x400>; |
||||
reg-names = "control", "domain"; |
||||
domain-id = <29>; |
||||
}; |
||||
}; |
@ -0,0 +1,182 @@ |
||||
/* |
||||
* Copyright 2013-2014 Texas Instruments, Inc. |
||||
* |
||||
* Keystone 2 Kepler/Hawking EVM device tree |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
/dts-v1/; |
||||
|
||||
#include "keystone.dtsi" |
||||
#include "k2hk.dtsi" |
||||
|
||||
/ { |
||||
compatible = "ti,k2hk-evm","ti,keystone"; |
||||
model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; |
||||
|
||||
soc { |
||||
clocks { |
||||
refclksys: refclksys { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <122880000>; |
||||
clock-output-names = "refclk-sys"; |
||||
}; |
||||
|
||||
refclkpass: refclkpass { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <122880000>; |
||||
clock-output-names = "refclk-pass"; |
||||
}; |
||||
|
||||
refclkarm: refclkarm { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <125000000>; |
||||
clock-output-names = "refclk-arm"; |
||||
}; |
||||
|
||||
refclkddr3a: refclkddr3a { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <100000000>; |
||||
clock-output-names = "refclk-ddr3a"; |
||||
}; |
||||
|
||||
refclkddr3b: refclkddr3b { |
||||
#clock-cells = <0>; |
||||
compatible = "fixed-clock"; |
||||
clock-frequency = <100000000>; |
||||
clock-output-names = "refclk-ddr3b"; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
leds { |
||||
compatible = "gpio-leds"; |
||||
debug1_1 { |
||||
label = "keystone:green:debug1"; |
||||
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ |
||||
}; |
||||
|
||||
debug1_2 { |
||||
label = "keystone:red:debug1"; |
||||
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ |
||||
}; |
||||
|
||||
debug2 { |
||||
label = "keystone:blue:debug2"; |
||||
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ |
||||
}; |
||||
|
||||
debug3 { |
||||
label = "keystone:blue:debug3"; |
||||
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&usb_phy { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usb { |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&aemif { |
||||
cs0 { |
||||
#address-cells = <2>; |
||||
#size-cells = <1>; |
||||
clock-ranges; |
||||
ranges; |
||||
|
||||
ti,cs-chipselect = <0>; |
||||
/* all timings in nanoseconds */ |
||||
ti,cs-min-turnaround-ns = <12>; |
||||
ti,cs-read-hold-ns = <6>; |
||||
ti,cs-read-strobe-ns = <23>; |
||||
ti,cs-read-setup-ns = <9>; |
||||
ti,cs-write-hold-ns = <8>; |
||||
ti,cs-write-strobe-ns = <23>; |
||||
ti,cs-write-setup-ns = <8>; |
||||
|
||||
nand@0,0 { |
||||
compatible = "ti,keystone-nand","ti,davinci-nand"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0 0 0x4000000 |
||||
1 0 0x0000100>; |
||||
|
||||
ti,davinci-chipselect = <0>; |
||||
ti,davinci-mask-ale = <0x2000>; |
||||
ti,davinci-mask-cle = <0x4000>; |
||||
ti,davinci-mask-chipsel = <0>; |
||||
nand-ecc-mode = "hw"; |
||||
ti,davinci-ecc-bits = <4>; |
||||
nand-on-flash-bbt; |
||||
|
||||
partition@0 { |
||||
label = "u-boot"; |
||||
reg = <0x0 0x100000>; |
||||
read-only; |
||||
}; |
||||
|
||||
partition@100000 { |
||||
label = "params"; |
||||
reg = <0x100000 0x80000>; |
||||
read-only; |
||||
}; |
||||
|
||||
partition@180000 { |
||||
label = "ubifs"; |
||||
reg = <0x180000 0x1fe80000>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&i2c0 { |
||||
dtt@50 { |
||||
compatible = "at,24c1024"; |
||||
reg = <0x50>; |
||||
}; |
||||
}; |
||||
|
||||
&spi0 { |
||||
nor_flash: n25q128a11@0 { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
compatible = "Micron,n25q128a11"; |
||||
spi-max-frequency = <54000000>; |
||||
m25p,fast-read; |
||||
reg = <0>; |
||||
|
||||
partition@0 { |
||||
label = "u-boot-spl"; |
||||
reg = <0x0 0x80000>; |
||||
read-only; |
||||
}; |
||||
|
||||
partition@1 { |
||||
label = "misc"; |
||||
reg = <0x80000 0xf80000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&mdio { |
||||
status = "ok"; |
||||
ethphy0: ethernet-phy@0 { |
||||
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; |
||||
reg = <0>; |
||||
}; |
||||
|
||||
ethphy1: ethernet-phy@1 { |
||||
compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; |
||||
reg = <1>; |
||||
}; |
||||
}; |
@ -0,0 +1,208 @@ |
||||
/* |
||||
* Device Tree Source for Keystone 2 Hawking Netcp driver |
||||
* |
||||
* Copyright 2015 Texas Instruments, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
qmss: qmss@2a40000 { |
||||
compatible = "ti,keystone-navigator-qmss"; |
||||
dma-coherent; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
clocks = <&chipclk13>; |
||||
ranges; |
||||
queue-range = <0 0x4000>; |
||||
linkram0 = <0x100000 0x8000>; |
||||
linkram1 = <0x0 0x10000>; |
||||
|
||||
qmgrs { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
qmgr0 { |
||||
managed-queues = <0 0x2000>; |
||||
reg = <0x2a40000 0x20000>, |
||||
<0x2a06000 0x400>, |
||||
<0x2a02000 0x1000>, |
||||
<0x2a03000 0x1000>, |
||||
<0x23a80000 0x20000>, |
||||
<0x2a80000 0x20000>; |
||||
reg-names = "peek", "status", "config", |
||||
"region", "push", "pop"; |
||||
}; |
||||
|
||||
qmgr1 { |
||||
managed-queues = <0x2000 0x2000>; |
||||
reg = <0x2a60000 0x20000>, |
||||
<0x2a06400 0x400>, |
||||
<0x2a04000 0x1000>, |
||||
<0x2a05000 0x1000>, |
||||
<0x23aa0000 0x20000>, |
||||
<0x2aa0000 0x20000>; |
||||
reg-names = "peek", "status", "config", |
||||
"region", "push", "pop"; |
||||
}; |
||||
}; |
||||
queue-pools { |
||||
qpend { |
||||
qpend-0 { |
||||
qrange = <658 8>; |
||||
interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 |
||||
0 43 0xf04 0 44 0xf04 0 45 0xf04 |
||||
0 46 0xf04 0 47 0xf04>; |
||||
}; |
||||
qpend-1 { |
||||
qrange = <8704 16>; |
||||
interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 |
||||
0 51 0xf04 0 52 0xf04 0 53 0xf04 |
||||
0 54 0xf04 0 55 0xf04 0 56 0xf04 |
||||
0 57 0xf04 0 58 0xf04 0 59 0xf04 |
||||
0 60 0xf04 0 61 0xf04 0 62 0xf04 |
||||
0 63 0xf04>; |
||||
qalloc-by-id; |
||||
}; |
||||
qpend-2 { |
||||
qrange = <8720 16>; |
||||
interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 |
||||
0 59 0xf04 0 68 0xf04 0 69 0xf04 |
||||
0 70 0xf04 0 71 0xf04 0 72 0xf04 |
||||
0 73 0xf04 0 74 0xf04 0 75 0xf04 |
||||
0 76 0xf04 0 77 0xf04 0 78 0xf04 |
||||
0 79 0xf04>; |
||||
}; |
||||
}; |
||||
general-purpose { |
||||
gp-0 { |
||||
qrange = <4000 64>; |
||||
}; |
||||
netcp-tx { |
||||
qrange = <640 9>; |
||||
qalloc-by-id; |
||||
}; |
||||
netcpx-tx { |
||||
qrange = <8752 8>; |
||||
qalloc-by-id; |
||||
}; |
||||
}; |
||||
}; |
||||
descriptor-regions { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
region-12 { |
||||
id = <12>; |
||||
region-spec = <8192 128>; /* num_desc desc_size */ |
||||
link-index = <0x4000>; |
||||
}; |
||||
}; |
||||
}; /* qmss */ |
||||
|
||||
knav_dmas: knav_dmas@0 { |
||||
compatible = "ti,keystone-navigator-dma"; |
||||
clocks = <&papllclk>; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
ranges; |
||||
ti,navigator-cloud-address = <0x23a80000 0x23a90000 |
||||
0x23aa0000 0x23ab0000>; |
||||
|
||||
dma_gbe: dma_gbe@0 { |
||||
reg = <0x2004000 0x100>, |
||||
<0x2004400 0x120>, |
||||
<0x2004800 0x300>, |
||||
<0x2004c00 0x120>, |
||||
<0x2005000 0x400>; |
||||
reg-names = "global", "txchan", "rxchan", |
||||
"txsched", "rxflow"; |
||||
}; |
||||
}; |
||||
|
||||
netcp: netcp@2000000 { |
||||
reg = <0x2620110 0x8>; |
||||
reg-names = "efuse"; |
||||
compatible = "ti,netcp-1.0"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
|
||||
/* NetCP address range */ |
||||
ranges = <0 0x2000000 0x100000>; |
||||
|
||||
clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; |
||||
dma-coherent; |
||||
|
||||
ti,navigator-dmas = <&dma_gbe 22>, |
||||
<&dma_gbe 23>, |
||||
<&dma_gbe 8>; |
||||
ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; |
||||
|
||||
netcp-devices { |
||||
ranges; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
gbe@90000 { /* ETHSS */ |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
label = "netcp-gbe"; |
||||
compatible = "ti,netcp-gbe"; |
||||
reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; |
||||
/* enable-ale; */ |
||||
tx-queue = <648>; |
||||
tx-channel = "nettx"; |
||||
|
||||
interfaces { |
||||
gbe0: interface-0 { |
||||
slave-port = <0>; |
||||
link-interface = <1>; |
||||
phy-handle = <ðphy0>; |
||||
}; |
||||
gbe1: interface-1 { |
||||
slave-port = <1>; |
||||
link-interface = <1>; |
||||
phy-handle = <ðphy1>; |
||||
}; |
||||
}; |
||||
|
||||
secondary-slave-ports { |
||||
port-2 { |
||||
slave-port = <2>; |
||||
link-interface = <2>; |
||||
}; |
||||
port-3 { |
||||
slave-port = <3>; |
||||
link-interface = <2>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
netcp-interfaces { |
||||
interface-0 { |
||||
rx-channel = "netrx0"; |
||||
rx-pool = <1024 12>; |
||||
tx-pool = <1024 12>; |
||||
rx-queue-depth = <128 128 0 0>; |
||||
rx-buffer-size = <1518 4096 0 0>; |
||||
rx-queue = <8704>; |
||||
tx-completion-queue = <8706>; |
||||
efuse-mac = <1>; |
||||
netcp-gbe = <&gbe0>; |
||||
|
||||
}; |
||||
interface-1 { |
||||
rx-channel = "netrx1"; |
||||
rx-pool = <1024 12>; |
||||
tx-pool = <1024 12>; |
||||
rx-queue-depth = <128 128 0 0>; |
||||
rx-buffer-size = <1518 4096 0 0>; |
||||
rx-queue = <8705>; |
||||
tx-completion-queue = <8707>; |
||||
efuse-mac = <0>; |
||||
local-mac-address = [02 18 31 7e 3e 6f]; |
||||
netcp-gbe = <&gbe1>; |
||||
}; |
||||
}; |
||||
}; |
@ -0,0 +1,114 @@ |
||||
/* |
||||
* Copyright 2013-2014 Texas Instruments, Inc. |
||||
* |
||||
* Keystone 2 Kepler/Hawking soc specific device tree |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
/ { |
||||
cpus { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
interrupt-parent = <&gic>; |
||||
|
||||
cpu@0 { |
||||
compatible = "arm,cortex-a15"; |
||||
device_type = "cpu"; |
||||
reg = <0>; |
||||
}; |
||||
|
||||
cpu@1 { |
||||
compatible = "arm,cortex-a15"; |
||||
device_type = "cpu"; |
||||
reg = <1>; |
||||
}; |
||||
|
||||
cpu@2 { |
||||
compatible = "arm,cortex-a15"; |
||||
device_type = "cpu"; |
||||
reg = <2>; |
||||
}; |
||||
|
||||
cpu@3 { |
||||
compatible = "arm,cortex-a15"; |
||||
device_type = "cpu"; |
||||
reg = <3>; |
||||
}; |
||||
}; |
||||
|
||||
soc { |
||||
/include/ "k2hk-clocks.dtsi" |
||||
|
||||
dspgpio0: keystone_dsp_gpio@02620240 { |
||||
compatible = "ti,keystone-dsp-gpio"; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
gpio,syscon-dev = <&devctrl 0x240>; |
||||
}; |
||||
|
||||
dspgpio1: keystone_dsp_gpio@2620244 { |
||||
compatible = "ti,keystone-dsp-gpio"; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
gpio,syscon-dev = <&devctrl 0x244>; |
||||
}; |
||||
|
||||
dspgpio2: keystone_dsp_gpio@2620248 { |
||||
compatible = "ti,keystone-dsp-gpio"; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
gpio,syscon-dev = <&devctrl 0x248>; |
||||
}; |
||||
|
||||
dspgpio3: keystone_dsp_gpio@262024c { |
||||
compatible = "ti,keystone-dsp-gpio"; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
gpio,syscon-dev = <&devctrl 0x24c>; |
||||
}; |
||||
|
||||
dspgpio4: keystone_dsp_gpio@2620250 { |
||||
compatible = "ti,keystone-dsp-gpio"; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
gpio,syscon-dev = <&devctrl 0x250>; |
||||
}; |
||||
|
||||
dspgpio5: keystone_dsp_gpio@2620254 { |
||||
compatible = "ti,keystone-dsp-gpio"; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
gpio,syscon-dev = <&devctrl 0x254>; |
||||
}; |
||||
|
||||
dspgpio6: keystone_dsp_gpio@2620258 { |
||||
compatible = "ti,keystone-dsp-gpio"; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
gpio,syscon-dev = <&devctrl 0x258>; |
||||
}; |
||||
|
||||
dspgpio7: keystone_dsp_gpio@262025c { |
||||
compatible = "ti,keystone-dsp-gpio"; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
gpio,syscon-dev = <&devctrl 0x25c>; |
||||
}; |
||||
|
||||
mdio: mdio@02090300 { |
||||
compatible = "ti,keystone_mdio", "ti,davinci_mdio"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x02090300 0x100>; |
||||
status = "disabled"; |
||||
clocks = <&clkcpgmac>; |
||||
clock-names = "fck"; |
||||
bus_freq = <2500000>; |
||||
}; |
||||
/include/ "k2hk-netcp.dtsi" |
||||
}; |
||||
}; |
@ -1,9 +1,13 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_KEYSTONE=y |
||||
CONFIG_TARGET_K2HK_EVM=y |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="k2hk-evm" |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_PROMPT="K2HK EVM # " |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_SPI_FLASH=y |
||||
|
Loading…
Reference in new issue