Wolfgang Denk
18 years ago
commit
3a71b5ca77
@ -0,0 +1,50 @@ |
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#
|
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# (C) Copyright 2006
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
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# See file CREDITS for list of people who contributed to this
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# project.
|
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o sdram.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1 @@ |
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TEXT_BASE = 0xFE000000
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@ -0,0 +1,116 @@ |
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007 |
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* |
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* Author: Scott Wood <scottwood@freescale.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <ft_build.h> |
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#include <pci.h> |
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#include <mpc83xx.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_early_init_f(void) |
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{ |
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#ifndef CFG_8313ERDB_BROKEN_PMC |
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volatile immap_t *im = (immap_t *)CFG_IMMR; |
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) |
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gd->flags |= GD_FLG_SILENT; |
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#endif |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: Freescale MPC8313ERDB\n"); |
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return 0; |
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} |
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|
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static struct pci_region pci_regions[] = { |
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{ |
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bus_start: CFG_PCI1_MEM_BASE, |
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phys_start: CFG_PCI1_MEM_PHYS, |
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size: CFG_PCI1_MEM_SIZE, |
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH |
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}, |
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{ |
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bus_start: CFG_PCI1_MMIO_BASE, |
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phys_start: CFG_PCI1_MMIO_PHYS, |
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size: CFG_PCI1_MMIO_SIZE, |
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flags: PCI_REGION_MEM |
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}, |
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{ |
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bus_start: CFG_PCI1_IO_BASE, |
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phys_start: CFG_PCI1_IO_PHYS, |
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size: CFG_PCI1_IO_SIZE, |
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flags: PCI_REGION_IO |
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} |
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}; |
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void pci_init_board(void) |
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{ |
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volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; |
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; |
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw; |
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struct pci_region *reg[] = { pci_regions }; |
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int warmboot; |
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/* Enable all 3 PCI_CLK_OUTPUTs. */ |
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clk->occr |= 0xe0000000; |
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/*
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* Configure PCI Local Access Windows |
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*/ |
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pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; |
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; |
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pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; |
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; |
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warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; |
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#ifndef CFG_8313ERDB_BROKEN_PMC |
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warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; |
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#endif |
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mpc83xx_pci_init(1, reg, warmboot); |
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} |
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#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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u32 *p; |
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int len; |
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#ifdef CONFIG_PCI |
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ft_pci_setup(blob, bd); |
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#endif |
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ft_cpu_setup(blob, bd); |
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p = ft_get_prop(blob, "/memory/reg", &len); |
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if (p) { |
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*p++ = cpu_to_be32(bd->bi_memstart); |
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*p = cpu_to_be32(bd->bi_memsize); |
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} |
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} |
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#endif |
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@ -0,0 +1,133 @@ |
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/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007 |
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* |
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* Authors: Nick.Spence@freescale.com |
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* Wilson.Lo@freescale.com |
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* scottwood@freescale.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <mpc83xx.h> |
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#include <spd_sdram.h> |
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#include <asm/bitops.h> |
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#include <asm/io.h> |
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#include <asm/processor.h> |
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#ifndef CFG_8313ERDB_BROKEN_PMC |
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static void resume_from_sleep(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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u32 magic = *(u32 *)0; |
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typedef void (*func_t)(void); |
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func_t resume = *(func_t *)4; |
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if (magic == 0xf5153ae5) |
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resume(); |
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gd->flags &= ~GD_FLG_SILENT; |
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puts("\nResume from sleep failed: bad magic word\n"); |
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} |
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#endif |
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|
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/* Fixed sdram init -- doesn't use serial presence detect.
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* |
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* This is useful for faster booting in configs where the RAM is unlikely |
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* to be changed, or for things like NAND booting where space is tight. |
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*/ |
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static long fixed_sdram(void) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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u32 msize = CFG_DDR_SIZE * 1024 * 1024; |
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u32 msize_log2 = __ilog2(msize); |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; |
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); |
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im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; |
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/*
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* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], |
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* or the DDR2 controller may fail to initialize correctly. |
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*/ |
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udelay(50000); |
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im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; |
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im->ddr.cs_config[0] = CFG_DDR_CONFIG; |
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/* Currently we use only one CS, so disable the other bank. */ |
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im->ddr.cs_config[1] = 0; |
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im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; |
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; |
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; |
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; |
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#ifndef CFG_8313ERDB_BROKEN_PMC |
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) |
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im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; |
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else |
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#endif |
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im->ddr.sdram_cfg = CFG_SDRAM_CFG; |
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im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; |
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im->ddr.sdram_mode = CFG_DDR_MODE; |
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im->ddr.sdram_mode2 = CFG_DDR_MODE_2; |
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im->ddr.sdram_interval = CFG_DDR_INTERVAL; |
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sync(); |
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/* enable DDR controller */ |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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return msize; |
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} |
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long int initdram(int board_type) |
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{ |
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volatile immap_t *im = (volatile immap_t *)CFG_IMMR; |
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volatile lbus83xx_t *lbc = &im->lbus; |
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u32 msize; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
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return -1; |
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puts("Initializing\n"); |
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/* DDR SDRAM - Main SODIMM */ |
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msize = fixed_sdram(); |
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/* Local Bus setup lbcr and mrtpr */ |
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lbc->lbcr = CFG_LBC_LBCR; |
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lbc->mrtpr = CFG_LBC_MRTPR; |
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sync(); |
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#ifndef CFG_8313ERDB_BROKEN_PMC |
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if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) |
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resume_from_sleep(); |
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#endif |
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puts(" DDR RAM: "); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return msize; |
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} |
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@ -0,0 +1,123 @@ |
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/* |
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* (C) Copyright 2006 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
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* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc83xx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
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*(.got1) |
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. = ALIGN(16); |
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*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
*(.eh_frame) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
ENTRY(_start) |
||||
@ -0,0 +1,417 @@ |
||||
/*
|
||||
* (C) Copyright 2007 Michal Simek |
||||
* |
||||
* Michal SIMEK <monstr@monstr.eu> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Microblaze FSL support |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <command.h> |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_MFSL) |
||||
#include <asm/asm.h> |
||||
|
||||
int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
unsigned int fslnum; |
||||
unsigned int num; |
||||
unsigned int blocking; |
||||
|
||||
if (argc < 2) { |
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
fslnum = (unsigned int)simple_strtoul (argv[1], NULL, 16); |
||||
blocking = (unsigned int)simple_strtoul (argv[2], NULL, 16); |
||||
if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) { |
||||
puts ("Bad number of FSL\n"); |
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
switch (fslnum) { |
||||
#if (XILINX_FSL_NUMBER > 0) |
||||
case 0: |
||||
switch (blocking) { |
||||
case 0: NGET (num, 0); |
||||
break; |
||||
case 1: NCGET (num, 0); |
||||
break; |
||||
case 2: GET (num, 0); |
||||
break; |
||||
case 3: CGET (num, 0); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 1) |
||||
case 1: |
||||
switch (blocking) { |
||||
case 0: NGET (num, 1); |
||||
break; |
||||
case 1: NCGET (num, 1); |
||||
break; |
||||
case 2: GET (num, 1); |
||||
break; |
||||
case 3: CGET (num, 1); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 2) |
||||
case 2: |
||||
switch (blocking) { |
||||
case 0: NGET (num, 2); |
||||
break; |
||||
case 1: NCGET (num, 2); |
||||
break; |
||||
case 2: GET (num, 2); |
||||
break; |
||||
case 3: CGET (num, 2); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 3) |
||||
case 3: |
||||
switch (blocking) { |
||||
case 0: NGET (num, 3); |
||||
break; |
||||
case 1: NCGET (num, 3); |
||||
break; |
||||
case 2: GET (num, 3); |
||||
break; |
||||
case 3: CGET (num, 3); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 4) |
||||
case 4: |
||||
switch (blocking) { |
||||
case 0: NGET (num, 4); |
||||
break; |
||||
case 1: NCGET (num, 4); |
||||
break; |
||||
case 2: GET (num, 4); |
||||
break; |
||||
case 3: CGET (num, 4); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 5) |
||||
case 5: |
||||
switch (blocking) { |
||||
case 0: NGET (num, 5); |
||||
break; |
||||
case 1: NCGET (num, 5); |
||||
break; |
||||
case 2: GET (num, 5); |
||||
break; |
||||
case 3: CGET (num, 5); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 6) |
||||
case 6: |
||||
switch (blocking) { |
||||
case 0: NGET (num, 6); |
||||
break; |
||||
case 1: NCGET (num, 6); |
||||
break; |
||||
case 2: GET (num, 6); |
||||
break; |
||||
case 3: CGET (num, 6); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 7) |
||||
case 7: |
||||
switch (blocking) { |
||||
case 0: NGET (num, 7); |
||||
break; |
||||
case 1: NCGET (num, 7); |
||||
break; |
||||
case 2: GET (num, 7); |
||||
break; |
||||
case 3: CGET (num, 7); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
default: |
||||
return 1; |
||||
} |
||||
|
||||
printf ("%01x: 0x%08lx - %s %s read\n", fslnum, num, |
||||
blocking < 2 ? "non blocking" : "blocking", |
||||
((blocking == 1) || (blocking == 3)) ? "control" : "data" ); |
||||
return 0; |
||||
} |
||||
|
||||
int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
unsigned int fslnum; |
||||
unsigned int num; |
||||
unsigned int blocking; |
||||
|
||||
if (argc < 3) { |
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
fslnum = (unsigned int)simple_strtoul (argv[1], NULL, 16); |
||||
num = (unsigned int)simple_strtoul (argv[2], NULL, 16); |
||||
blocking = (unsigned int)simple_strtoul (argv[3], NULL, 16); |
||||
if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) { |
||||
printf ("Bad number of FSL\nUsage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
|
||||
switch (fslnum) { |
||||
#if (XILINX_FSL_NUMBER > 0) |
||||
case 0: |
||||
switch (blocking) { |
||||
case 0: NPUT (num, 0); |
||||
break; |
||||
case 1: NCPUT (num, 0); |
||||
break; |
||||
case 2: PUT (num, 0); |
||||
break; |
||||
case 3: CPUT (num, 0); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 1) |
||||
case 1: |
||||
switch (blocking) { |
||||
case 0: NPUT (num, 1); |
||||
break; |
||||
case 1: NCPUT (num, 1); |
||||
break; |
||||
case 2: PUT (num, 1); |
||||
break; |
||||
case 3: CPUT (num, 1); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 2) |
||||
case 2: |
||||
switch (blocking) { |
||||
case 0: NPUT (num, 2); |
||||
break; |
||||
case 1: NCPUT (num, 2); |
||||
break; |
||||
case 2: PUT (num, 2); |
||||
break; |
||||
case 3: CPUT (num, 2); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 3) |
||||
case 3: |
||||
switch (blocking) { |
||||
case 0: NPUT (num, 3); |
||||
break; |
||||
case 1: NCPUT (num, 3); |
||||
break; |
||||
case 2: PUT (num, 3); |
||||
break; |
||||
case 3: CPUT (num, 3); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 4) |
||||
case 4: |
||||
switch (blocking) { |
||||
case 0: NPUT (num, 4); |
||||
break; |
||||
case 1: NCPUT (num, 4); |
||||
break; |
||||
case 2: PUT (num, 4); |
||||
break; |
||||
case 3: CPUT (num, 4); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 5) |
||||
case 5: |
||||
switch (blocking) { |
||||
case 0: NPUT (num, 5); |
||||
break; |
||||
case 1: NCPUT (num, 5); |
||||
break; |
||||
case 2: PUT (num, 5); |
||||
break; |
||||
case 3: CPUT (num, 5); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 6) |
||||
case 6: |
||||
switch (blocking) { |
||||
case 0: NPUT (num, 6); |
||||
break; |
||||
case 1: NCPUT (num, 6); |
||||
break; |
||||
case 2: PUT (num, 6); |
||||
break; |
||||
case 3: CPUT (num, 6); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
#if (XILINX_FSL_NUMBER > 7) |
||||
case 7: |
||||
switch (blocking) { |
||||
case 0: NPUT (num, 7); |
||||
break; |
||||
case 1: NCPUT (num, 7); |
||||
break; |
||||
case 2: PUT (num, 7); |
||||
break; |
||||
case 3: CPUT (num, 7); |
||||
break; |
||||
default: |
||||
return 2; |
||||
} |
||||
break; |
||||
#endif |
||||
default: |
||||
return 1; |
||||
} |
||||
|
||||
printf ("%01x: 0x%08lx - %s %s write\n", fslnum, num, |
||||
blocking < 2 ? "non blocking" : "blocking", |
||||
((blocking == 1) || (blocking == 3)) ? "control" : "data" ); |
||||
return 0; |
||||
|
||||
} |
||||
|
||||
int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
unsigned int reg = 0; |
||||
unsigned int val = 0; |
||||
|
||||
reg = (unsigned int)simple_strtoul (argv[1], NULL, 16); |
||||
val = (unsigned int)simple_strtoul (argv[2], NULL, 16); |
||||
if (argc < 1) { |
||||
printf ("Usage:\n%s\n", cmdtp->usage); |
||||
return 1; |
||||
} |
||||
switch (reg) { |
||||
case 0x1: |
||||
if (argc > 2) { |
||||
MTS (val, rmsr); |
||||
NOP; |
||||
MFS (val, rmsr); |
||||
|
||||
} else { |
||||
MFS (val, rmsr); |
||||
} |
||||
puts ("MSR"); |
||||
break; |
||||
case 0x3: |
||||
MFS (val, rear); |
||||
puts ("EAR"); |
||||
break; |
||||
case 0x5: |
||||
MFS (val, resr); |
||||
puts ("ESR"); |
||||
break; |
||||
default: |
||||
return 1; |
||||
} |
||||
printf (": 0x%08lx\n", val); |
||||
return 0; |
||||
} |
||||
|
||||
/***************************************************/ |
||||
|
||||
U_BOOT_CMD (frd, 3, 1, do_frd, |
||||
"frd - read data from FSL\n", |
||||
"- [fslnum [0|1|2|3]]\n" |
||||
" 0 - non blocking data read\n" |
||||
" 1 - non blocking control read\n" |
||||
" 2 - blocking data read\n" |
||||
" 3 - blocking control read\n"); |
||||
|
||||
|
||||
U_BOOT_CMD (fwr, 4, 1, do_fwr, |
||||
"fwr - write data to FSL\n", |
||||
"- [fslnum [0|1|2|3]]\n" |
||||
" 0 - non blocking data write\n" |
||||
" 1 - non blocking control write\n" |
||||
" 2 - blocking data write\n" |
||||
" 3 - blocking control write\n"); |
||||
|
||||
U_BOOT_CMD (rspr, 3, 1, do_rspr, |
||||
"rmsr - read/write special purpose register\n", |
||||
"- reg_num [write value] read/write special purpose register\n" |
||||
" 0 - MSR - Machine status register\n" |
||||
" 1 - EAR - Exception address register\n" |
||||
" 2 - ESR - Exception status register\n"); |
||||
|
||||
#endif /* CONFIG_MICROBLAZE & CFG_CMD_MFSL */ |
||||
@ -1,68 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2007 Michal Simek |
||||
* |
||||
* Michal SIMEK <monstr@monstr.eu>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
.text |
||||
.globl dcache_enable
|
||||
.ent dcache_enable
|
||||
.align 2
|
||||
dcache_enable: |
||||
/* Make space on stack for a temporary */ |
||||
addi r1, r1, -4 |
||||
/* Save register r12 */ |
||||
swi r12, r1, 0 |
||||
/* Read the MSR register */ |
||||
mfs r12, rmsr |
||||
/* Set the instruction enable bit */ |
||||
ori r12, r12, 0x80 |
||||
/* Save the MSR register */ |
||||
mts rmsr, r12 |
||||
/* Load register r12 */ |
||||
lwi r12, r1, 0 |
||||
/* Return */ |
||||
rtsd r15, 8 |
||||
/* Update stack in the delay slot */ |
||||
addi r1, r1, 4 |
||||
.end dcache_enable
|
||||
|
||||
.text |
||||
.globl dcache_disable
|
||||
.ent dcache_disable
|
||||
.align 2
|
||||
dcache_disable: |
||||
/* Make space on stack for a temporary */ |
||||
addi r1, r1, -4 |
||||
/* Save register r12 */ |
||||
swi r12, r1, 0 |
||||
/* Read the MSR register */ |
||||
mfs r12, rmsr |
||||
/* Clear the data cache enable bit */ |
||||
andi r12, r12, ~0x80 |
||||
/* Save the MSR register */ |
||||
mts rmsr, r12 |
||||
/* Load register r12 */ |
||||
lwi r12, r1, 0 |
||||
/* Return */ |
||||
rtsd r15, 8 |
||||
/* Update stack in the delay slot */ |
||||
addi r1, r1, 4 |
||||
.end dcache_disable
|
||||
@ -1,46 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2007 Michal Simek |
||||
* |
||||
* Michal SIMEK <monstr@monstr.eu>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
.text |
||||
.globl microblaze_disable_interrupts
|
||||
.ent microblaze_disable_interrupts
|
||||
.align 2
|
||||
microblaze_disable_interrupts: |
||||
#Make space on stack for a temporary |
||||
addi r1, r1, -4 |
||||
#Save register r12 |
||||
swi r12, r1, 0 |
||||
#Read the MSR register |
||||
mfs r12, rmsr |
||||
#Clear the interrupt enable bit |
||||
andi r12, r12, ~2 |
||||
#Save the MSR register |
||||
mts rmsr, r12 |
||||
#Load register r12 |
||||
lwi r12, r1, 0 |
||||
#Return |
||||
rtsd r15, 8 |
||||
#Update stack in the delay slot |
||||
addi r1, r1, 4 |
||||
.end microblaze_disable_interrupts
|
||||
@ -1,38 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2007 Michal Simek |
||||
* |
||||
* Michal SIMEK <monstrmonstr.eu> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
.text |
||||
.globl microblaze_enable_interrupts
|
||||
.ent microblaze_enable_interrupts
|
||||
.align 2
|
||||
microblaze_enable_interrupts: |
||||
addi r1, r1, -4 |
||||
swi r12, r1, 0 |
||||
mfs r12, rmsr |
||||
ori r12, r12, 2 |
||||
mts rmsr, r12 |
||||
lwi r12, r1, 0 |
||||
rtsd r15, 8 |
||||
addi r1, r1, 4 |
||||
.end microblaze_enable_interrupts
|
||||
@ -1,69 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2007 Michal Simek |
||||
* |
||||
* Michal SIMEK <monstr@monstr.eu>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
.text |
||||
.globl icache_enable
|
||||
.ent icache_enable
|
||||
.align 2
|
||||
icache_enable: |
||||
/* Make space on stack for a temporary */ |
||||
addi r1, r1, -4 |
||||
/* Save register r12 */ |
||||
swi r12, r1, 0 |
||||
/* Read the MSR register */ |
||||
mfs r12, rmsr |
||||
/* Set the instruction enable bit */ |
||||
ori r12, r12, 0x20 |
||||
/* Save the MSR register */ |
||||
mts rmsr, r12 |
||||
/* Load register r12 */ |
||||
lwi r12, r1, 0 |
||||
/* Return */ |
||||
rtsd r15, 8 |
||||
/* Update stack in the delay slot */ |
||||
addi r1, r1, 4 |
||||
.end icache_enable
|
||||
|
||||
.text |
||||
.globl icache_disable
|
||||
.ent icache_disable
|
||||
.align 2
|
||||
icache_disable: |
||||
/* Make space on stack for a temporary */ |
||||
addi r1, r1, -4 |
||||
/* Save register r12 */ |
||||
swi r12, r1, 0 |
||||
/* Read the MSR register */ |
||||
mfs r12, rmsr |
||||
/* Clear the instruction enable bit */ |
||||
andi r12, r12, ~0x20 |
||||
/* Save the MSR register */ |
||||
mts rmsr, r12 |
||||
/* Load register r12 */ |
||||
lwi r12, r1, 0 |
||||
/* Return */ |
||||
rtsd r15, 8 |
||||
/* Update stack in the delay slot */ |
||||
addi r1, r1, 4 |
||||
.end icache_disable
|
||||
@ -0,0 +1,192 @@ |
||||
/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2007 |
||||
* |
||||
* Author: Scott Wood <scottwood@freescale.com>, |
||||
* with some bits from older board-specific PCI initialization. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <ft_build.h> |
||||
#include <asm/mpc8349_pci.h> |
||||
|
||||
#ifdef CONFIG_83XX_GENERIC_PCI |
||||
#define MAX_BUSES 2 |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static struct pci_controller pci_hose[MAX_BUSES]; |
||||
static int pci_num_buses; |
||||
|
||||
static void pci_init_bus(int bus, struct pci_region *reg) |
||||
{ |
||||
volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; |
||||
volatile pot83xx_t *pot = immr->ios.pot; |
||||
volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus]; |
||||
struct pci_controller *hose = &pci_hose[bus]; |
||||
u32 dev; |
||||
u16 reg16; |
||||
int i; |
||||
|
||||
if (bus == 1) |
||||
pot += 3; |
||||
|
||||
/* Setup outbound translation windows */ |
||||
for (i = 0; i < 3; i++, reg++, pot++) { |
||||
if (reg->size == 0) |
||||
break; |
||||
|
||||
hose->regions[i] = *reg; |
||||
hose->region_count++; |
||||
|
||||
pot->potar = reg->bus_start >> 12; |
||||
pot->pobar = reg->phys_start >> 12; |
||||
pot->pocmr = ~(reg->size - 1) >> 12; |
||||
|
||||
if (reg->flags & PCI_REGION_IO) |
||||
pot->pocmr |= POCMR_IO; |
||||
#ifdef CONFIG_83XX_PCI_STREAMING |
||||
else if (reg->flags & PCI_REGION_PREFETCH) |
||||
pot->pocmr |= POCMR_SE; |
||||
#endif |
||||
|
||||
if (bus == 1) |
||||
pot->pocmr |= POCMR_DST; |
||||
|
||||
pot->pocmr |= POCMR_EN; |
||||
} |
||||
|
||||
/* Point inbound translation at RAM */ |
||||
pci_ctrl->pitar1 = 0; |
||||
pci_ctrl->pibar1 = 0; |
||||
pci_ctrl->piebar1 = 0; |
||||
pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | |
||||
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); |
||||
|
||||
i = hose->region_count++; |
||||
hose->regions[i].bus_start = 0; |
||||
hose->regions[i].phys_start = 0; |
||||
hose->regions[i].size = gd->ram_size; |
||||
hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; |
||||
|
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0xff; |
||||
|
||||
pci_setup_indirect(hose, CFG_IMMR + 0x8300 + bus * 0x80, |
||||
CFG_IMMR + 0x8304 + bus * 0x80); |
||||
|
||||
pci_register_hose(hose); |
||||
|
||||
/*
|
||||
* Write to Command register |
||||
*/ |
||||
reg16 = 0xff; |
||||
dev = PCI_BDF(hose->first_busno, 0, 0); |
||||
pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); |
||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); |
||||
|
||||
#ifdef CONFIG_PCI_SCAN_SHOW |
||||
printf("PCI: Bus Dev VenId DevId Class Int\n"); |
||||
#endif |
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
} |
||||
|
||||
/*
|
||||
* The caller must have already set OCCR, and the PCI_LAW BARs |
||||
* must have been set to cover all of the requested regions. |
||||
* |
||||
* If fewer than three regions are requested, then the region |
||||
* list is terminated with a region of size 0. |
||||
*/ |
||||
void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) |
||||
{ |
||||
volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; |
||||
int i; |
||||
|
||||
if (num_buses > MAX_BUSES) { |
||||
printf("%d PCI buses requsted, %d supported\n", |
||||
num_buses, MAX_BUSES); |
||||
|
||||
num_buses = MAX_BUSES; |
||||
} |
||||
|
||||
pci_num_buses = num_buses; |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal. |
||||
* Power on to RST high must be at least 100 ms as per PCI spec. |
||||
* On warm boots only 1 ms is required. |
||||
*/ |
||||
udelay(warmboot ? 1000 : 100000); |
||||
|
||||
for (i = 0; i < num_buses; i++) |
||||
immr->pci_ctrl[i].gcr = 1; |
||||
|
||||
/*
|
||||
* RST high to first config access must be at least 2^25 cycles |
||||
* as per PCI spec. This could be cut in half if we know we're |
||||
* running at 66MHz. This could be insufficiently long if we're |
||||
* running the PCI bus at significantly less than 33MHz. |
||||
*/ |
||||
udelay(1020000); |
||||
|
||||
for (i = 0; i < num_buses; i++) |
||||
pci_init_bus(i, reg[i]); |
||||
} |
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE |
||||
void ft_pci_setup(void *blob, bd_t *bd) |
||||
{ |
||||
u32 *p; |
||||
int len; |
||||
|
||||
if (pci_num_buses < 1) |
||||
return; |
||||
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len); |
||||
if (p) { |
||||
p[0] = pci_hose[0].first_busno; |
||||
p[1] = pci_hose[0].last_busno; |
||||
} |
||||
|
||||
if (pci_num_buses < 2) |
||||
return; |
||||
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8600/bus-range", &len); |
||||
if (p) { |
||||
p[0] = pci_hose[1].first_busno; |
||||
p[1] = pci_hose[1].last_busno; |
||||
} |
||||
} |
||||
#endif /* CONFIG_OF_FLAT_TREE */ |
||||
|
||||
#endif /* CONFIG_83XX_GENERIC_PCI */ |
||||
@ -0,0 +1,83 @@ |
||||
Freescale MPC8313ERDB Board |
||||
----------------------------------------- |
||||
|
||||
1. Board Switches and Jumpers |
||||
|
||||
SW3 is used to set CFG_RESET_SOURCE. |
||||
|
||||
To boot the image at 0xFE000000 in NOR flash, use these DIP |
||||
switche settings for SW3 SW4: |
||||
|
||||
+------+ +------+ |
||||
| | | **** | |
||||
| **** | | | |
||||
+------+ ON +------+ ON |
||||
4321 4321 |
||||
(where the '*' indicates the position of the tab of the switch.) |
||||
|
||||
2. Memory Map |
||||
The memory map looks like this: |
||||
|
||||
0x0000_0000 0x07ff_ffff DDR 128M |
||||
0x8000_0000 0x8fff_ffff PCI MEM 256M |
||||
0x9000_0000 0x9fff_ffff PCI_MMIO 256M |
||||
0xe000_0000 0xe00f_ffff IMMR 1M |
||||
0xe200_0000 0xe20f_ffff PCI IO 16M |
||||
0xe280_0000 0xe280_7fff NAND FLASH (CS1) 32K |
||||
0xf000_0000 0xf001_ffff VSC7385 (CS2) 128K |
||||
0xfa00_0000 0xfa00_7fff Board Status/ 32K |
||||
LED Control (CS3) |
||||
0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M |
||||
|
||||
3. Definitions |
||||
|
||||
3.1 Explanation of NEW definitions in: |
||||
|
||||
include/configs/MPC8313ERDB.h |
||||
|
||||
CONFIG_MPC83xx MPC83xx family |
||||
CONFIG_MPC831x MPC831x specific |
||||
CONFIG_MPC8313ERDB MPC8313ERDB board specific |
||||
|
||||
4. Compilation |
||||
|
||||
Assuming you're using BASH (or similar) as your shell: |
||||
|
||||
export CROSS_COMPILE=your-cross-compiler-prefix- |
||||
make distclean |
||||
make MPC8313ERDB_33_config |
||||
(or make MPC8313ERDB_66_config, depending on the speed of |
||||
the oscillator on your board) |
||||
make |
||||
|
||||
5. Downloading and Flashing Images |
||||
|
||||
5.1 Reflash U-boot Image using U-boot |
||||
|
||||
=>run tftpflash |
||||
|
||||
You may want to try |
||||
=>tftpboot $loadaddr $uboot |
||||
first, to make sure that the TFTP load will succeed before it |
||||
goes ahead and wipes out your current firmware. And of course, |
||||
have an alternate means of programming the flash available |
||||
if the new u-boot doesn't boot. |
||||
|
||||
5.2 Downloading and Booting Linux Kernel |
||||
|
||||
Ensure that all networking-related environment variables are set |
||||
properly (including ipaddr, serverip, gatewayip (if needed), |
||||
netmask, ethaddr, eth1addr, rootpath (if using NFS root), |
||||
fdtfile, and bootfile). |
||||
|
||||
Then, do one of the following, depending on whether you |
||||
want an NFS root or a ramdisk root: |
||||
|
||||
=>run nfsboot |
||||
or |
||||
=>run ramboot |
||||
|
||||
6 Notes |
||||
|
||||
Booting from NAND flash is not yet supported. |
||||
The console baudrate for MPC8313ERDB is 115200bps. |
||||
@ -0,0 +1,98 @@ |
||||
/*
|
||||
* (C) Copyright 2007 Michal Simek |
||||
* |
||||
* Michal SIMEK <monstr@monstr.eu> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/* FSL macros */ |
||||
#define NGET(val, fslnum) \ |
||||
__asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val)); |
||||
|
||||
#define GET(val, fslnum) \ |
||||
__asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val)); |
||||
|
||||
#define NCGET(val, fslnum) \ |
||||
__asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val)); |
||||
|
||||
#define CGET(val, fslnum) \ |
||||
__asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val)); |
||||
|
||||
#define NPUT(val, fslnum) \ |
||||
__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val)); |
||||
|
||||
#define PUT(val, fslnum) \ |
||||
__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val)); |
||||
|
||||
#define NCPUT(val, fslnum) \ |
||||
__asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val)); |
||||
|
||||
#define CPUT(val, fslnum) \ |
||||
__asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val)); |
||||
|
||||
/* CPU dependent */ |
||||
/* machine status register */ |
||||
#define MFS(val, reg) \ |
||||
__asm__ __volatile__ ("mfs %0," #reg :"=r" (val)); |
||||
|
||||
#define MTS(val, reg) \ |
||||
__asm__ __volatile__ ("mts " #reg ", %0"::"r" (val)); |
||||
|
||||
/* get return address from interrupt */ |
||||
#define R14(val) \ |
||||
__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val)); |
||||
|
||||
#define NOP __asm__ __volatile__ ("nop"); |
||||
|
||||
/* use machine status registe USE_MSR_REG */ |
||||
#ifdef XILINX_USE_MSR_INSTR |
||||
#define MSRSET(val) \ |
||||
__asm__ __volatile__ ("msrset r0," #val ); |
||||
|
||||
#define MSRCLR(val) \ |
||||
__asm__ __volatile__ ("msrclr r0," #val ); |
||||
|
||||
#else |
||||
#define MSRSET(val) \ |
||||
{ \
|
||||
register unsigned tmp; \
|
||||
__asm__ __volatile__ (" \
|
||||
mfs %0, rmsr; \
|
||||
ori %0, %0, "#val"; \
|
||||
mts rmsr, %0; \
|
||||
nop;" \
|
||||
: "=r" (tmp) \
|
||||
: "d" (val) \
|
||||
: "memory"); \
|
||||
} |
||||
|
||||
#define MSRCLR(val) \ |
||||
{ \
|
||||
register unsigned tmp; \
|
||||
__asm__ __volatile__ (" \
|
||||
mfs %0, rmsr; \
|
||||
andi %0, %0, ~"#val"; \
|
||||
mts rmsr, %0; \
|
||||
nop;" \
|
||||
: "=r" (tmp) \
|
||||
: "d" (val) \
|
||||
: "memory"); \
|
||||
} |
||||
#endif |
||||
@ -0,0 +1,561 @@ |
||||
/*
|
||||
* Copyright (C) Freescale Semiconductor, Inc. 2006. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
/*
|
||||
* mpc8313epb board configuration file |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 |
||||
#define CONFIG_MPC83XX 1 |
||||
#define CONFIG_MPC831X 1 |
||||
#define CONFIG_MPC8313 1 |
||||
#define CONFIG_MPC8313ERDB 1 |
||||
|
||||
#define CONFIG_PCI |
||||
#define CONFIG_83XX_GENERIC_PCI |
||||
|
||||
#ifdef CFG_66MHZ |
||||
#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
||||
#elif defined(CFG_33MHZ) |
||||
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
||||
#else |
||||
#error Unknown oscillator frequency. |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
||||
|
||||
#define CFG_IMMR 0xE0000000 |
||||
|
||||
#define CFG_MEMTEST_START 0x00001000 |
||||
#define CFG_MEMTEST_END 0x07f00000 |
||||
|
||||
/* Early revs of this board will lock up hard when attempting
|
||||
* to access the PMC registers, unless a JTAG debugger is |
||||
* connected, or some resistor modifications are made. |
||||
*/ |
||||
#define CFG_8313ERDB_BROKEN_PMC 1 |
||||
|
||||
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
||||
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE |
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
||||
|
||||
/*
|
||||
* Manually set up DDR parameters, as this board does not |
||||
* seem to have the SPD connected to I2C. |
||||
*/ |
||||
#define CFG_DDR_SIZE 128 /* MB */ |
||||
#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ |
||||
| 0x00040000 /* TODO */ \
|
||||
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) |
||||
/* 0x80840102 */ |
||||
|
||||
#define CFG_DDR_TIMING_3 0x00000000 |
||||
#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ |
||||
| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
|
||||
| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
|
||||
| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
|
||||
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) |
||||
/* 0x00220802 */ |
||||
#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ |
||||
| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
|
||||
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
|
||||
| (13 << TIMING_CFG1_REFREC_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) |
||||
/* 0x3935d322 */ |
||||
#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ |
||||
| (31 << TIMING_CFG2_CPO_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
|
||||
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
|
||||
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
|
||||
| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) |
||||
/* 0x0f9048ca */ /* P9-45,may need tuning */ |
||||
#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ |
||||
| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) |
||||
/* 0x03200064 */ |
||||
#if defined(CONFIG_DDR_2T_TIMING) |
||||
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ |
||||
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
|
||||
| SDRAM_CFG_2T_EN \
|
||||
| SDRAM_CFG_DBW_32 ) |
||||
#else |
||||
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ |
||||
| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
|
||||
| SDRAM_CFG_32_BE ) |
||||
/* 0x43080000 */ |
||||
#endif |
||||
#define CFG_SDRAM_CFG2 0x00401000; |
||||
/* set burst length to 8 for 32-bit data path */ |
||||
#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ |
||||
| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) |
||||
/* 0x44400232 */ |
||||
#define CFG_DDR_MODE_2 0x8000C000; |
||||
|
||||
#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
||||
/*0x02000000*/ |
||||
#define CFG_DDRCDR_VALUE ( DDRCDR_EN \ |
||||
| DDRCDR_PZ_NOMZ \
|
||||
| DDRCDR_NZ_NOMZ \
|
||||
| DDRCDR_M_ODR ) |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ |
||||
#define CFG_FLASH_SIZE 8 /* flash size in MB */ |
||||
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */ |
||||
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ |
||||
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
|
||||
BR_V) /* valid */ |
||||
#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ |
||||
| OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_9 \
|
||||
| OR_GPCM_EHTR \
|
||||
| OR_GPCM_EAD ) |
||||
/* 0xFF006FF7 TODO SLOW 16 MB flash size */ |
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs |
||||
*/ |
||||
#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ |
||||
#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ |
||||
| (0xFF << LBCR_BMT_SHIFT) \
|
||||
| 0xF ) /* 0x0004ff0f */ |
||||
|
||||
#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ |
||||
|
||||
/* drivers/nand/nand.c */ |
||||
#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ |
||||
#define CFG_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE |
||||
|
||||
#define CFG_BR1_PRELIM ( CFG_NAND_BASE \ |
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V ) /* valid */ |
||||
#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ |
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR ) |
||||
/* 0xFFFF8396 */ |
||||
#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE |
||||
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ |
||||
|
||||
#define CFG_VSC7385_BASE 0xF0000000 |
||||
|
||||
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ |
||||
#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ |
||||
#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ |
||||
#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ |
||||
#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ |
||||
|
||||
/* local bus read write buffer mapping */ |
||||
#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ |
||||
#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ |
||||
#define CFG_LBLAWBAR3_PRELIM 0xFA000000 |
||||
#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ |
||||
|
||||
/* pass open firmware flat tree */ |
||||
#define CONFIG_OF_FLAT_TREE 1 |
||||
#define CONFIG_OF_BOARD_SETUP 1 |
||||
|
||||
/* maximum size of the flat tree (8K) */ |
||||
#define OF_FLAT_TREE_MAX_SIZE 8192 |
||||
|
||||
#define OF_CPU "PowerPC,8313@0" |
||||
#define OF_SOC "soc8313@e0000000" |
||||
#define OF_TBCLK (bd->bi_busfreq / 4) |
||||
#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" |
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_I2C_MULTI_BUS |
||||
#define CONFIG_I2C_CMD_TREE |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
#define CFG_I2C2_OFFSET 0x3100 |
||||
|
||||
/* TSEC */ |
||||
#define CFG_TSEC1_OFFSET 0x24000 |
||||
#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) |
||||
#define CFG_TSEC2_OFFSET 0x25000 |
||||
#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) |
||||
#define CONFIG_NET_MULTI |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_MMIO_BASE 0x90000000 |
||||
#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE |
||||
#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ |
||||
#define CFG_PCI1_IO_BASE 0x00000000 |
||||
#define CFG_PCI1_IO_PHYS 0xE2000000 |
||||
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
||||
|
||||
/*
|
||||
* TSEC configuration |
||||
*/ |
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_GMII 1 /* MII PHY management */ |
||||
#define CONFIG_MPC83XX_TSEC1 1 |
||||
|
||||
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" |
||||
#define CONFIG_MPC83XX_TSEC2 1 |
||||
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" |
||||
#define TSEC1_PHY_ADDR 0x1c |
||||
#define TSEC2_PHY_ADDR 4 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
|
||||
/* Options are: TSEC[0-1] */ |
||||
#define CONFIG_ETHPRIME "TSEC1" |
||||
|
||||
/*
|
||||
* Configure on-board RTC |
||||
*/ |
||||
#define CONFIG_RTC_DS1337 |
||||
#define CFG_I2C_RTC_ADDR 0x68 |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#else |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_DHCP \
|
||||
| CFG_CMD_I2C \
|
||||
| CFG_CMD_MII \
|
||||
| CFG_CMD_DATE \
|
||||
| CFG_CMD_PCI) |
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
|
||||
#define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \ |
||||
~(CFG_CMD_ENV | CFG_CMD_LOADS)) |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS |
||||
#else |
||||
#define CONFIG_COMMANDS CFG_BASE_COMMANDS |
||||
#endif |
||||
|
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 16384 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
||||
|
||||
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
||||
|
||||
#ifdef CFG_66MHZ |
||||
|
||||
/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ |
||||
/* 0x62040000 */ |
||||
#define CFG_HRCW_LOW (\ |
||||
0x20000000 /* reserved, must be set */ |\
|
||||
HRCWL_DDRCM |\
|
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_2X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_2X1 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
|
||||
#elif defined(CFG_33MHZ) |
||||
|
||||
/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ |
||||
/* 0x65040000 */ |
||||
#define CFG_HRCW_LOW (\ |
||||
0x20000000 /* reserved, must be set */ |\
|
||||
HRCWL_DDRCM |\
|
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_2X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_5X1 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
|
||||
#endif |
||||
|
||||
/* 0xa0606c00 */ |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LALE_NORMAL) |
||||
|
||||
/* System IO Config */ |
||||
#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ |
||||
#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ |
||||
|
||||
#define CFG_HID0_INIT 0x000000000 |
||||
#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
||||
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
||||
|
||||
#define CFG_HID2 HID2_HBE |
||||
|
||||
/* DDR @ 0x00000000 */ |
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* PCI @ 0x80000000 */ |
||||
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) |
||||
#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* PCI2 not supported on 8313 */ |
||||
#define CFG_IBAT3L (0) |
||||
#define CFG_IBAT3U (0) |
||||
#define CFG_IBAT4L (0) |
||||
#define CFG_IBAT4U (0) |
||||
|
||||
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
||||
#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
||||
#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
||||
#define CFG_IBAT6L (0xF0000000 | BATL_PP_10) |
||||
#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT7L (0) |
||||
#define CFG_IBAT7U (0) |
||||
|
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
#define CFG_DBAT4L CFG_IBAT4L |
||||
#define CFG_DBAT4U CFG_IBAT4U |
||||
#define CFG_DBAT5L CFG_IBAT5L |
||||
#define CFG_DBAT5U CFG_IBAT5U |
||||
#define CFG_DBAT6L CFG_IBAT6L |
||||
#define CFG_DBAT6U CFG_IBAT6U |
||||
#define CFG_DBAT7L CFG_IBAT7L |
||||
#define CFG_DBAT7U CFG_IBAT7U |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_ETHADDR 00:E0:0C:00:95:01 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 |
||||
|
||||
#define CONFIG_IPADDR 10.0.0.2 |
||||
#define CONFIG_SERVERIP 10.0.0.1 |
||||
#define CONFIG_GATEWAYIP 10.0.0.1 |
||||
#define CONFIG_NETMASK 255.0.0.0 |
||||
#define CONFIG_NETDEV eth1 |
||||
|
||||
#define CONFIG_HOSTNAME mpc8313erdb |
||||
#define CONFIG_ROOTPATH /nfs/root/path |
||||
#define CONFIG_BOOTFILE uImage |
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
||||
#define CONFIG_FDTFILE mpc8313erdb.dtb |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define XMK_STR(x) #x |
||||
#define MK_STR(x) XMK_STR(x) |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
|
||||
"ethprime=TSEC1\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"fdtaddr=400000\0" \
|
||||
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
|
||||
"console=ttyS0\0" \
|
||||
"setbootargs=setenv bootargs " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
||||
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv rootdev /dev/nfs;" \
|
||||
"run setbootargs;" \
|
||||
"run setipargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv rootdev /dev/ram;" \
|
||||
"run setbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#undef MK_STR |
||||
#undef XMK_STR |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue