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@ -35,81 +35,80 @@ DECLARE_GLOBAL_DATA_PTR; |
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#include <nand.h> |
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#include <linux/mtd/mtd.h> |
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#define SET_CLE 0x10 |
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#define CLR_CLE ~SET_CLE |
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#define SET_ALE 0x08 |
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#define CLR_ALE ~SET_ALE |
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#define SET_CLE 0x10 |
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#define CLR_CLE ~SET_CLE |
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#define SET_ALE 0x08 |
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#define CLR_ALE ~SET_ALE |
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) |
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{ |
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struct nand_chip *this = mtdinfo->priv; |
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; |
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u32 nand_baseaddr = (u32) this->IO_ADDR_W; |
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struct nand_chip *this = mtdinfo->priv; |
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; |
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u32 nand_baseaddr = (u32) this->IO_ADDR_W; |
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switch (cmd) { |
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case NAND_CTL_SETNCE: |
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case NAND_CTL_CLRNCE: |
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break; |
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case NAND_CTL_SETCLE: |
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nand_baseaddr |= SET_CLE; |
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break; |
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case NAND_CTL_CLRCLE: |
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nand_baseaddr &= CLR_CLE; |
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break; |
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case NAND_CTL_SETALE: |
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nand_baseaddr |= SET_ALE; |
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break; |
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case NAND_CTL_CLRALE: |
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nand_baseaddr |= CLR_ALE; |
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break; |
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case NAND_CTL_SETWP: |
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fbcs->csmr2 |= CSMR_WP; |
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break; |
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case NAND_CTL_CLRWP: |
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fbcs->csmr2 &= ~CSMR_WP; |
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break; |
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} |
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this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); |
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switch (cmd) { |
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case NAND_CTL_SETNCE: |
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case NAND_CTL_CLRNCE: |
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break; |
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case NAND_CTL_SETCLE: |
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nand_baseaddr |= SET_CLE; |
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break; |
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case NAND_CTL_CLRCLE: |
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nand_baseaddr &= CLR_CLE; |
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break; |
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case NAND_CTL_SETALE: |
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nand_baseaddr |= SET_ALE; |
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break; |
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case NAND_CTL_CLRALE: |
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nand_baseaddr |= CLR_ALE; |
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break; |
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case NAND_CTL_SETWP: |
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fbcs->csmr2 |= CSMR_WP; |
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break; |
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case NAND_CTL_CLRWP: |
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fbcs->csmr2 &= ~CSMR_WP; |
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break; |
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} |
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this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); |
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} |
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static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) |
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{ |
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struct nand_chip *this = mtdinfo->priv; |
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*((volatile u8 *)(this->IO_ADDR_W)) = byte; |
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struct nand_chip *this = mtdinfo->priv; |
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*((volatile u8 *)(this->IO_ADDR_W)) = byte; |
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} |
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static u8 nand_read_byte(struct mtd_info *mtdinfo) |
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{ |
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struct nand_chip *this = mtdinfo->priv; |
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return (u8) (*((volatile u8 *)this->IO_ADDR_R)); |
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struct nand_chip *this = mtdinfo->priv; |
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return (u8) (*((volatile u8 *)this->IO_ADDR_R)); |
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} |
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static int nand_dev_ready(struct mtd_info *mtdinfo) |
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{ |
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return 1; |
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return 1; |
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} |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
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*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; |
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*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; |
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/* set up pin configuration */ |
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gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; |
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gpio->pddr_timer |= 0x08; |
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gpio->ppd_timer |= 0x08; |
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gpio->pclrr_timer = 0; |
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gpio->podr_timer = 0; |
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/* set up pin configuration */ |
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gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; |
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gpio->pddr_timer |= 0x08; |
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gpio->ppd_timer |= 0x08; |
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gpio->pclrr_timer = 0; |
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gpio->podr_timer = 0; |
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nand->chip_delay = 50; |
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nand->eccmode = NAND_ECC_SOFT; |
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nand->hwcontrol = nand_hwcontrol; |
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nand->read_byte = nand_read_byte; |
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nand->write_byte = nand_write_byte; |
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nand->dev_ready = nand_dev_ready; |
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nand->chip_delay = 50; |
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nand->eccmode = NAND_ECC_SOFT; |
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nand->hwcontrol = nand_hwcontrol; |
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nand->read_byte = nand_read_byte; |
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nand->write_byte = nand_write_byte; |
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nand->dev_ready = nand_dev_ready; |
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return 0; |
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return 0; |
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} |
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#endif |
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