- 16/32 MB and 50/80 MHz support with auto-detection for IP860 - ETH05 and BEDBUG support for CU824 - added support for MicroSys CPC45 - new BOOTROM/FLASH0 and DOC base for PM826 * Patch by Robert Schwebel, 12 Mar 2003: Fix the chpart command on innokom board * Name cleanup: mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h s/PPCBoot/U-Boot/ in some files s/pImage/uImage/ in some files * Patch by Detlev Zundel, 15 Jan 2003: Fix '' command line quoting * Patch by The LEOX team, 19 Jan 2003: - add support for the ELPT860 board - add support for Dallas ds164x RTCmaster
wdenk
22 years ago
parent
1cb8e980c4
commit
3bac351370
@ -0,0 +1,47 @@ |
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#######################################################################
|
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#
|
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# Copyright (C) 2000, 2001, 2002, 2003
|
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# The LEOX team <team@leox.org>, http://www.leox.org
|
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#
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# LEOX.org is about the development of free hardware and software resources
|
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# for system on chip.
|
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#
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# Description: U-Boot port on the LEOX's ELPT860 CPU board
|
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# ~~~~~~~~~~~
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#
|
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#######################################################################
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#######################################################################
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o flash.o
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$(LIB): .depend $(OBJS) |
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$(AR) crv $@ $^
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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|
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#########################################################################
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@ -0,0 +1,424 @@ |
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============================================================================= |
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U-Boot port on the LEOX's ELPT860 CPU board |
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------------------------------------------- |
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LEOX.org is about the development of free hardware and software resources |
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for system on chip. |
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|
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For more information, contact The LEOX team <team@leox.org> |
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|
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References: |
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~~~~~~~~~~ |
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1) Get the last stable release from denx.de: |
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o ftp://ftp.denx.de/pub/u-boot/u-boot-0.2.0.tar.bz2 |
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2) Get the current CVS snapshot: |
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o cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login |
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o cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot |
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|
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============================================================================= |
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|
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The ELPT860 CPU board has the following features: |
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|
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Processor: - MPC860T @ 50MHz |
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- PowerPC Core |
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- 65 MIPS |
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- Caches: D->4KB, I->4KB |
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- CPM: 4 SCCs, 2 SMCs |
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- Ethernet 10/100 |
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- SPI, I2C, PCMCIA, Parallel |
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|
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CPU board: - DRAM: 16 MB |
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- FLASH: 512 KB + (2 * 4 MB) |
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- NVRAM: 128 KB |
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- 1 Serial link |
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- 2 Ethernet 10 BaseT Channels |
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|
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On power-up the processor jumps to the address of 0x02000100 |
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|
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Thus, U-Boot is configured to reside in flash starting at the address of |
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0x02001000. The environment space is located in NVRAM separately from |
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U-Boot, at the address of 0x03000000. |
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|
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============================================================================= |
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|
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U-Boot test results |
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|
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============================================================================= |
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|
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################################################## |
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# Operation on the serial console (SMC1) |
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############################## |
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U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) |
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CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present |
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*** Warning: CPU Core has Silicon Bugs -- Check the Errata *** |
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Board: ### No HW ID - assuming ELPT860 |
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DRAM: 16 MB |
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FLASH: 512 kB |
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In: serial |
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Out: serial |
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Err: serial |
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Net: SCC ETHERNET |
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Type "run nfsboot" to mount root filesystem over NFS |
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|
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Hit any key to stop autoboot: 0 |
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LEOX_elpt860: help |
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askenv - get environment variables from stdin |
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autoscr - run script from memory |
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base - print or set address offset |
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bdinfo - print Board Info structure |
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bootm - boot application image from memory |
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bootp - boot image via network using BootP/TFTP protocol |
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bootd - boot default, i.e., run 'bootcmd' |
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cmp - memory compare |
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coninfo - print console devices and informations |
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cp - memory copy |
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crc32 - checksum calculation |
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echo - echo args to console |
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erase - erase FLASH memory |
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flinfo - print FLASH memory information |
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go - start application at address 'addr' |
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help - print online help |
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iminfo - print header information for application image |
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loadb - load binary file over serial line (kermit mode) |
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loads - load S-Record file over serial line |
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loop - infinite loop on address range |
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md - memory display |
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mm - memory modify (auto-incrementing) |
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mtest - simple RAM test |
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mw - memory write (fill) |
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nm - memory modify (constant address) |
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printenv- print environment variables |
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protect - enable or disable FLASH write protection |
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rarpboot- boot image via network using RARP/TFTP protocol |
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reset - Perform RESET of the CPU |
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run - run commands in an environment variable |
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saveenv - save environment variables to persistent storage |
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setenv - set environment variables |
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sleep - delay execution for some time |
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tftpboot- boot image via network using TFTP protocol |
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and env variables ipaddr and serverip |
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version - print monitor version |
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? - alias for 'help' |
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################################################## |
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# Environment Variables (CFG_ENV_IS_IN_NVRAM) |
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############################## |
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LEOX_elpt860: printenv |
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bootdelay=5 |
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loads_echo=1 |
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baudrate=9600 |
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stdin=serial |
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stdout=serial |
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stderr=serial |
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ethaddr=00:03:ca:00:64:df |
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ipaddr=192.168.0.30 |
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netmask=255.255.255.0 |
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serverip=192.168.0.1 |
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nfsserverip=192.168.0.1 |
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preboot=echo;echo Type "run nfsboot" to mount root filesystem over NFS;echo |
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gatewayip=192.168.0.1 |
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ramargs=setenv bootargs root=/dev/ram rw |
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rootargs=setenv rootpath /tftp/$(ipaddr) |
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nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsserverip):$(rootpath) |
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addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsserverip):$(gatewayip):$(netmask):$(hostname):eth0: |
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ramboot=tftp 400000 /home/leox/pMulti;run ramargs;bootm |
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nfsboot=tftp 400000 /home/leox/uImage;run rootargs;run nfsargs;run addip;bootm |
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bootcmd=run ramboot |
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clocks_in_mhz=1 |
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Environment size: 730/16380 bytes |
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################################################## |
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# Flash Memory Information |
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############################## |
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LEOX_elpt860: flinfo |
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Bank # 1: AMD AM29F040 (4 Mbits) |
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Size: 512 KB in 8 Sectors |
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Sector Start Addresses: |
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02000000 (RO) 02010000 (RO) 02020000 (RO) 02030000 (RO) 02040000 |
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02050000 02060000 02070000 |
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################################################## |
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# Board Information Structure |
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############################## |
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LEOX_elpt860: bdinfo |
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memstart = 0x00000000 |
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memsize = 0x01000000 |
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flashstart = 0x02000000 |
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flashsize = 0x00080000 |
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flashoffset = 0x00030000 |
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sramstart = 0x00000000 |
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sramsize = 0x00000000 |
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immr_base = 0xFF000000 |
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bootflags = 0x00000001 |
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intfreq = 50 MHz |
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busfreq = 50 MHz |
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ethaddr = 00:03:ca:00:64:df |
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IP addr = 192.168.0.30 |
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baudrate = 9600 bps |
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################################################## |
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# Image Download and run over serial port |
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# hello_world (S-Record image) |
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# ===> 1) Enter "loads" command into U-Boot monitor |
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# ===> 2) From TeraTerm's bar menu, Select 'File/Send file...' |
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# Then select 'hello_world.srec' with the file browser |
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############################## |
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U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) |
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CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present |
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*** Warning: CPU Core has Silicon Bugs -- Check the Errata *** |
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Board: ### No HW ID - assuming ELPT860 |
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DRAM: 16 MB |
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FLASH: 512 kB |
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In: serial |
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Out: serial |
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Err: serial |
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Net: SCC ETHERNET |
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Type "run nfsboot" to mount root filesystem over NFS |
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Hit any key to stop autoboot: 0 |
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LEOX_elpt860: loads |
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## Ready for S-Record download ... |
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S804040004F3050154000501709905014C000501388D |
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## First Load Addr = 0x00040000 |
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## Last Load Addr = 0x0005018B |
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## Total Size = 0x0001018C = 65932 Bytes |
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## Start Addr = 0x00040004 |
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LEOX_elpt860: go 40004 This is a test !!! |
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## Starting application at 0x00040004 ... |
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Hello World |
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argc = 6 |
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argv[0] = "40004" |
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argv[1] = "This" |
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argv[2] = "is" |
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argv[3] = "a" |
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argv[4] = "test" |
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argv[5] = "!!!" |
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argv[6] = "<NULL>" |
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Hit any key to exit ... |
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## Application terminated, rc = 0x0 |
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################################################## |
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# Image download and run over ethernet interface |
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# Linux-2.4.4 (uImage) + Root filesystem mounted over NFS |
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############################## |
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U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) |
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CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present |
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*** Warning: CPU Core has Silicon Bugs -- Check the Errata *** |
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Board: ### No HW ID - assuming ELPT860 |
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DRAM: 16 MB |
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FLASH: 512 kB |
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In: serial |
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Out: serial |
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Err: serial |
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Net: SCC ETHERNET |
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Type "run nfsboot" to mount root filesystem over NFS |
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Hit any key to stop autoboot: 0 |
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LEOX_elpt860: run nfsboot |
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ARP broadcast 1 |
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TFTP from server 192.168.0.1; our IP address is 192.168.0.30 |
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Filename '/home/leox/uImage'. |
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Load address: 0x400000 |
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Loading: ################################################################# |
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############################# |
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done |
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Bytes transferred = 477294 (7486e hex) |
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## Booting image at 00400000 ... |
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Image Name: Linux-2.4.4 |
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Image Type: PowerPC Linux Kernel Image (gzip compressed) |
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Data Size: 477230 Bytes = 466 kB = 0 MB |
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Load Address: 00000000 |
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Entry Point: 00000000 |
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Verifying Checksum ... OK |
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Uncompressing Kernel Image ... OK |
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Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 |
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On node 0 totalpages: 4096 |
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zone(0): 4096 pages. |
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zone(1): 0 pages. |
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zone(2): 0 pages. |
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Kernel command line: root=/dev/nfs rw nfsroot=192.168.0.1:/tftp/192.168.0.30 ip=192.168.0.30:192.168.0.1:192.168.0.1:255.255.255.0::eth0: |
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rtsched version <20010618.1050.24> |
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Decrementer Frequency: 3125000 |
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Warning: real time clock seems stuck! |
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Calibrating delay loop... 49.76 BogoMIPS |
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Memory: 14720k available (928k kernel code, 384k data, 44k init, 0k highmem) |
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Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) |
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Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) |
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Page-cache hash table entries: 4096 (order: 2, 16384 bytes) |
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Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) |
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POSIX conformance testing by UNIFIX |
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Linux NET4.0 for Linux 2.4 |
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Based upon Swansea University Computer Society NET3.039 |
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Starting kswapd v1.8 |
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CPM UART driver version 0.03 |
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ttyS0 on SMC1 at 0x0280, BRG1 |
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block: queued sectors max/low 9701kB/3233kB, 64 slots per queue |
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RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize |
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eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df |
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NET4: Linux TCP/IP 1.0 for NET4.0 |
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IP Protocols: ICMP, UDP, TCP |
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IP: routing cache hash table of 512 buckets, 4Kbytes |
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TCP: Hash tables configured (established 1024 bind 1024) |
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NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. |
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Looking up port of RPC 100003/2 on 192.168.0.1 |
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Looking up port of RPC 100005/2 on 192.168.0.1 |
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VFS: Mounted root (nfs filesystem). |
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Freeing unused kernel memory: 44k init |
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INIT: version 2.78 booting |
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Welcome to DENX Embedded Linux Environment |
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Press 'I' to enter interactive startup. |
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Mounting proc filesystem: [ OK ] |
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Configuring kernel parameters: [ OK ] |
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Cannot access the Hardware Clock via any known method. |
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Use the --debug option to see the details of our search for an access method. |
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Setting clock : Wed Dec 31 19:00:11 EST 1969 [ OK ] |
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Activating swap partitions: [ OK ] |
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Setting hostname 192.168.0.30: [ OK ] |
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Finding module dependencies: |
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[ OK ] |
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Checking filesystems |
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Checking all file systems. |
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[ OK ] |
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Mounting local filesystems: [ OK ] |
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Enabling swap space: [ OK ] |
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INIT: Entering runlevel: 3 |
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Entering non-interactive startup |
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Starting system logger: [ OK ] |
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Starting kernel logger: [ OK ] |
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Starting xinetd: [ OK ] |
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|
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192 login: root |
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Last login: Wed Dec 31 19:00:41 on ttyS0 |
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bash-2.04# |
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################################################## |
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# Image download and run over ethernet interface |
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# Linux-2.4.4 + Root filesystem mounted from RAM (pMulti) |
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############################## |
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|
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U-Boot 0.2.2 (Jan 19 2003 - 11:08:39) |
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|
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CPU: XPC860xxZPnnB at 50 MHz: 4 kB I-Cache 4 kB D-Cache FEC present |
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*** Warning: CPU Core has Silicon Bugs -- Check the Errata *** |
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Board: ### No HW ID - assuming ELPT860 |
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DRAM: 16 MB |
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FLASH: 512 kB |
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In: serial |
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Out: serial |
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Err: serial |
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Net: SCC ETHERNET |
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|
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Type "run nfsboot" to mount root filesystem over NFS |
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|
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Hit any key to stop autoboot: 0 |
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LEOX_elpt860: run ramboot |
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ARP broadcast 1 |
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TFTP from server 192.168.0.1; our IP address is 192.168.0.30 |
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Filename '/home/leox/pMulti'. |
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Load address: 0x400000 |
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Loading: ################################################################# |
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################################################################# |
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################################################################# |
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################################################################# |
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################################################################# |
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######################################################## |
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done |
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Bytes transferred = 1947816 (1db8a8 hex) |
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## Booting image at 00400000 ... |
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Image Name: linux-2.4.4-2002-03-21 Multiboot |
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Image Type: PowerPC Linux Multi-File Image (gzip compressed) |
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Data Size: 1947752 Bytes = 1902 kB = 1 MB |
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Load Address: 00000000 |
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Entry Point: 00000000 |
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Contents: |
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Image 0: 477230 Bytes = 466 kB = 0 MB |
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Image 1: 1470508 Bytes = 1436 kB = 1 MB |
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Verifying Checksum ... OK |
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Uncompressing Multi-File Image ... OK |
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Loading Ramdisk to 00e44000, end 00fab02c ... OK |
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Linux version 2.4.4-rthal5 (leox@p5ak6650) (gcc version 2.95.3 20010315 (release/MontaVista)) #1 Wed Jul 3 10:23:53 CEST 2002 |
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On node 0 totalpages: 4096 |
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zone(0): 4096 pages. |
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zone(1): 0 pages. |
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zone(2): 0 pages. |
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Kernel command line: root=/dev/ram rw |
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rtsched version <20010618.1050.24> |
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Decrementer Frequency: 3125000 |
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Warning: real time clock seems stuck! |
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Calibrating delay loop... 49.76 BogoMIPS |
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Memory: 13280k available (928k kernel code, 384k data, 44k init, 0k highmem) |
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Dentry-cache hash table entries: 2048 (order: 2, 16384 bytes) |
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Buffer-cache hash table entries: 1024 (order: 0, 4096 bytes) |
||||
Page-cache hash table entries: 4096 (order: 2, 16384 bytes) |
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Inode-cache hash table entries: 1024 (order: 1, 8192 bytes) |
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POSIX conformance testing by UNIFIX |
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Linux NET4.0 for Linux 2.4 |
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Based upon Swansea University Computer Society NET3.039 |
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Starting kswapd v1.8 |
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CPM UART driver version 0.03 |
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ttyS0 on SMC1 at 0x0280, BRG1 |
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block: queued sectors max/low 8741kB/2913kB, 64 slots per queue |
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RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize |
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eth0: CPM ENET Version 0.2 on SCC1, 00:03:ca:00:64:df |
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RAMDISK: Compressed image found at block 0 |
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Freeing initrd memory: 1436k freed |
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NET4: Linux TCP/IP 1.0 for NET4.0 |
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IP Protocols: ICMP, UDP, TCP |
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IP: routing cache hash table of 512 buckets, 4Kbytes |
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TCP: Hash tables configured (established 1024 bind 1024) |
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IP-Config: Incomplete network configuration information. |
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NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. |
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VFS: Mounted root (ext2 filesystem). |
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Freeing unused kernel memory: 44k iné |
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init started: BusyBox v0.60.2 (2002.07.01-12:06+0000) multi-call Configuring hostname |
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Configuring lo... |
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Configuring eth0... |
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Configuring Gateway... |
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|
||||
Please press Enter to activate this console. |
||||
|
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ELPT860 login: root |
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Password: |
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Welcome to Linux-2.4.4 for ELPT CPU board (MPC860T @ 50MHz) |
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|
||||
a8888b. |
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d888888b. |
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8P"YP"Y88 |
||||
_ _ 8|o||o|88 |
||||
| | |_| 8' .88 |
||||
| | _ ____ _ _ _ _ 8`._.' Y8. |
||||
| | | | _ \| | | |\ \/ / d/ `8b. |
||||
| |___ | | | | | |_| |/ \ .dP . Y8b. |
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|_____||_|_| |_|\____|\_/\_/ d8:' " `::88b. |
||||
d8" `Y88b |
||||
:8P ' :888 |
||||
8a. : _a88P |
||||
._/"Yaa_ : .| 88P| |
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\ YP" `| 8P `. |
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/ \._____.d| .' |
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`--..__)888888P`._.' |
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login[21]: root login on `ttyS0' |
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|
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|
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|
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BusyBox v0.60.3 (2002.07.20-10:39+0000) Built-in shell (ash) |
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Enter 'help' for a list of built-in commands. |
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|
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root@ELPT860:~ # |
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@ -0,0 +1,36 @@ |
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#######################################################################
|
||||
#
|
||||
# Copyright (C) 2000, 2001, 2002, 2003
|
||||
# The LEOX team <team@leox.org>, http://www.leox.org
|
||||
#
|
||||
# LEOX.org is about the development of free hardware and software resources
|
||||
# for system on chip.
|
||||
#
|
||||
# Description: U-Boot port on the LEOX's ELPT860 CPU board
|
||||
# ~~~~~~~~~~~
|
||||
#
|
||||
#######################################################################
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#######################################################################
|
||||
|
||||
#
|
||||
# ELPT860 board
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x02000000
|
||||
#TEXT_BASE = 0x00FB0000
|
||||
@ -0,0 +1,399 @@ |
||||
/*
|
||||
**===================================================================== |
||||
** |
||||
** Copyright (C) 2000, 2001, 2002, 2003 |
||||
** The LEOX team <team@leox.org>, http://www.leox.org
|
||||
** |
||||
** LEOX.org is about the development of free hardware and software resources |
||||
** for system on chip. |
||||
** |
||||
** Description: U-Boot port on the LEOX's ELPT860 CPU board |
||||
** ~~~~~~~~~~~ |
||||
** |
||||
**===================================================================== |
||||
** |
||||
** This program is free software; you can redistribute it and/or |
||||
** modify it under the terms of the GNU General Public License as |
||||
** published by the Free Software Foundation; either version 2 of |
||||
** the License, or (at your option) any later version. |
||||
** |
||||
** This program is distributed in the hope that it will be useful, |
||||
** but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
** GNU General Public License for more details. |
||||
** |
||||
** You should have received a copy of the GNU General Public License |
||||
** along with this program; if not, write to the Free Software |
||||
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
** MA 02111-1307 USA |
||||
** |
||||
**===================================================================== |
||||
*/ |
||||
|
||||
/*
|
||||
** Note 1: In this file, you have to provide the following functions: |
||||
** ------ |
||||
** int board_pre_init(void) |
||||
** int checkboard(void) |
||||
** long int initdram(int board_type) |
||||
** called from 'board_init_f()' into 'common/board.c' |
||||
** |
||||
** void reset_phy(void) |
||||
** called from 'board_init_r()' into 'common/board.c' |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
static long int dram_size (long int, long int *, long int); |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF |
||||
|
||||
const uint init_sdram_table[] = |
||||
{ |
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM) |
||||
*/ |
||||
0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, |
||||
0xFFFFFC04, /* last */ |
||||
/*
|
||||
* SDRAM Initialization (offset 5 in UPMA RAM) |
||||
* |
||||
* This is no UPM entry point. The following definition uses |
||||
* the remaining space to establish an initialization |
||||
* sequence, which is executed by a RUN command. |
||||
* |
||||
*/ |
||||
0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */ |
||||
/*
|
||||
* Burst Read. (Offset 8 in UPMA RAM) |
||||
*/ |
||||
0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */ |
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM) |
||||
*/ |
||||
0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, |
||||
0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */ |
||||
/*
|
||||
* Burst Write. (Offset 20 in UPMA RAM) |
||||
*/ |
||||
0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34, |
||||
0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */ |
||||
}; |
||||
|
||||
const uint sdram_table[] = |
||||
{ |
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM) |
||||
*/ |
||||
0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
|
||||
0xFF0FFC00, /* last */ |
||||
/*
|
||||
* SDRAM Initialization (offset 5 in UPMA RAM) |
||||
* |
||||
* This is no UPM entry point. The following definition uses |
||||
* the remaining space to establish an initialization |
||||
* sequence, which is executed by a RUN command. |
||||
* |
||||
*/ |
||||
0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */ |
||||
/*
|
||||
* Burst Read. (Offset 8 in UPMA RAM) |
||||
*/ |
||||
0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
|
||||
0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00, |
||||
0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
|
||||
0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ |
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM) |
||||
*/ |
||||
0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
|
||||
0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */ |
||||
_NOT_USED_,
|
||||
/*
|
||||
* Burst Write. (Offset 20 in UPMA RAM) |
||||
*/ |
||||
0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
|
||||
0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
|
||||
0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
|
||||
0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ |
||||
/*
|
||||
* Refresh (Offset 30 in UPMA RAM) |
||||
*/ |
||||
0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
|
||||
0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
|
||||
0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */ |
||||
/*
|
||||
* Exception. (Offset 3c in UPMA RAM) |
||||
*/ |
||||
0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */ |
||||
}; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#define CFG_PC4 0x0800 |
||||
|
||||
#define CFG_DS1 CFG_PC4 |
||||
|
||||
/*
|
||||
* Very early board init code (fpga boot, etc.) |
||||
*/ |
||||
int |
||||
board_pre_init (void) |
||||
{ |
||||
volatile immap_t *immr = (immap_t *) CFG_IMMR; |
||||
|
||||
/*
|
||||
* Light up the red led on ELPT860 pcb (DS1) (PCDAT)
|
||||
*/ |
||||
immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */ |
||||
immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */ |
||||
immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */ |
||||
|
||||
return ( 0 ); /* success */ |
||||
} |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
* |
||||
* Test ELPT860 ID string |
||||
* |
||||
* Return 1 if no second DRAM bank, otherwise returns 0 |
||||
*/ |
||||
|
||||
int
|
||||
checkboard (void) |
||||
{ |
||||
unsigned char *s = getenv("serial#"); |
||||
|
||||
if ( !s || strncmp(s, "ELPT860", 7) ) |
||||
printf ("### No HW ID - assuming ELPT860\n"); |
||||
|
||||
return ( 0 ); /* success */ |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
long int
|
||||
initdram (int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size8, size9; |
||||
long int size_b0 = 0; |
||||
|
||||
/*
|
||||
* This sequence initializes SDRAM chips on ELPT860 board |
||||
*/ |
||||
upmconfig(UPMA, (uint *)init_sdram_table,
|
||||
sizeof(init_sdram_table)/sizeof(uint)); |
||||
|
||||
memctl->memc_mptpr = 0x0200; |
||||
memctl->memc_mamr = 0x18002111; |
||||
|
||||
memctl->memc_mar = 0x00000088; |
||||
memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */ |
||||
|
||||
upmconfig(UPMA, (uint *)sdram_table,
|
||||
sizeof(sdram_table)/sizeof(uint)); |
||||
|
||||
/*
|
||||
* Preliminary prescaler for refresh (depends on number of |
||||
* banks): This value is selected for four cycles every 62.4 us |
||||
* with two SDRAM banks or four cycles every 31.2 us with one |
||||
* bank. It will be adjusted after memory sizing. |
||||
*/ |
||||
memctl->memc_mptpr = CFG_MPTPR_2BK_8K; |
||||
|
||||
/*
|
||||
* The following value is used as an address (i.e. opcode) for |
||||
* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If |
||||
* the port size is 32bit the SDRAM does NOT "see" the lower two |
||||
* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for |
||||
* MICRON SDRAMs: |
||||
* -> 0 00 010 0 010 |
||||
* | | | | +- Burst Length = 4 |
||||
* | | | +----- Burst Type = Sequential |
||||
* | | +------- CAS Latency = 2 |
||||
* | +----------- Operating Mode = Standard |
||||
* +-------------- Write Burst Mode = Programmed Burst Length |
||||
*/ |
||||
memctl->memc_mar = 0x00000088; |
||||
|
||||
/*
|
||||
* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at |
||||
* preliminary addresses - these have to be modified after the |
||||
* SDRAM size has been determined. |
||||
*/ |
||||
memctl->memc_or1 = CFG_OR1_PRELIM; |
||||
memctl->memc_br1 = CFG_BR1_PRELIM; |
||||
|
||||
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ |
||||
|
||||
udelay (200); |
||||
|
||||
/* perform SDRAM initializsation sequence */ |
||||
|
||||
memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */ |
||||
udelay (1); |
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
||||
|
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* Check Bank 0 Memory Size for re-configuration |
||||
* |
||||
* try 8 column mode |
||||
*/ |
||||
size8 = dram_size (CFG_MAMR_8COL,
|
||||
(ulong *) SDRAM_BASE1_PRELIM,
|
||||
SDRAM_MAX_SIZE); |
||||
|
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* try 9 column mode |
||||
*/ |
||||
size9 = dram_size (CFG_MAMR_9COL,
|
||||
(ulong *) SDRAM_BASE1_PRELIM,
|
||||
SDRAM_MAX_SIZE); |
||||
|
||||
if ( size8 < size9 ) /* leave configuration at 9 columns */ |
||||
{ |
||||
size_b0 = size9; |
||||
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ |
||||
}
|
||||
else /* back to 8 columns */ |
||||
{ |
||||
size_b0 = size8; |
||||
memctl->memc_mamr = CFG_MAMR_8COL; |
||||
udelay (500); |
||||
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ |
||||
} |
||||
|
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* Adjust refresh rate depending on SDRAM type, both banks |
||||
* For types > 128 MBit leave it at the current (fast) rate |
||||
*/ |
||||
if ( size_b0 < 0x02000000 )
|
||||
{ |
||||
/* reduce to 15.6 us (62.4 us / quad) */ |
||||
memctl->memc_mptpr = CFG_MPTPR_2BK_4K; |
||||
udelay (1000); |
||||
} |
||||
|
||||
/*
|
||||
* Final mapping: map bigger bank first |
||||
*/ |
||||
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; |
||||
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; |
||||
|
||||
{ |
||||
unsigned long reg; |
||||
|
||||
/* adjust refresh rate depending on SDRAM type, one bank */ |
||||
reg = memctl->memc_mptpr; |
||||
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ |
||||
memctl->memc_mptpr = reg; |
||||
} |
||||
|
||||
udelay(10000); |
||||
|
||||
return (size_b0); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines |
||||
* the actually available RAM size between addresses `base' and |
||||
* `base + maxsize'. Some (not all) hardware errors are detected: |
||||
* - short between address lines |
||||
* - short between data lines |
||||
*/ |
||||
|
||||
static long int
|
||||
dram_size (long int mamr_value,
|
||||
long int *base,
|
||||
long int maxsize) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
volatile long int *addr; |
||||
ulong cnt, val; |
||||
ulong save[32]; /* to make test non-destructive */ |
||||
unsigned char i = 0; |
||||
|
||||
memctl->memc_mamr = mamr_value; |
||||
|
||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1)
|
||||
{ |
||||
addr = base + cnt; /* pointer arith! */ |
||||
|
||||
save[i++] = *addr; |
||||
*addr = ~cnt; |
||||
} |
||||
|
||||
/* write 0 to base address */ |
||||
addr = base; |
||||
save[i] = *addr; |
||||
*addr = 0; |
||||
|
||||
/* check at base address */ |
||||
if ( (val = *addr) != 0 )
|
||||
{ |
||||
*addr = save[i]; |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1)
|
||||
{ |
||||
addr = base + cnt; /* pointer arith! */ |
||||
|
||||
val = *addr; |
||||
*addr = save[--i]; |
||||
|
||||
if ( val != (~cnt) )
|
||||
{ |
||||
return (cnt * sizeof(long)); |
||||
} |
||||
} |
||||
|
||||
return (maxsize); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#define CFG_PA1 0x4000 |
||||
#define CFG_PA2 0x2000 |
||||
|
||||
#define CFG_LBKs (CFG_PA2 | CFG_PA1) |
||||
|
||||
void |
||||
reset_phy (void) |
||||
{ |
||||
volatile immap_t *immr = (immap_t *) CFG_IMMR; |
||||
|
||||
/*
|
||||
* Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect |
||||
* and no AUI loopback |
||||
*/ |
||||
immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */ |
||||
immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */ |
||||
immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */ |
||||
} |
||||
@ -0,0 +1,615 @@ |
||||
/*
|
||||
**===================================================================== |
||||
** |
||||
** Copyright (C) 2000, 2001, 2002, 2003 |
||||
** The LEOX team <team@leox.org>, http://www.leox.org
|
||||
** |
||||
** LEOX.org is about the development of free hardware and software resources |
||||
** for system on chip. |
||||
** |
||||
** Description: U-Boot port on the LEOX's ELPT860 CPU board |
||||
** ~~~~~~~~~~~ |
||||
** |
||||
**===================================================================== |
||||
** |
||||
** This program is free software; you can redistribute it and/or |
||||
** modify it under the terms of the GNU General Public License as |
||||
** published by the Free Software Foundation; either version 2 of |
||||
** the License, or (at your option) any later version. |
||||
** |
||||
** This program is distributed in the hope that it will be useful, |
||||
** but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
** GNU General Public License for more details. |
||||
** |
||||
** You should have received a copy of the GNU General Public License |
||||
** along with this program; if not, write to the Free Software |
||||
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
** MA 02111-1307 USA |
||||
** |
||||
**===================================================================== |
||||
*/ |
||||
|
||||
/*
|
||||
** Note 1: In this file, you have to provide the following variable: |
||||
** ------ |
||||
** flash_info_t flash_info[CFG_MAX_FLASH_BANKS] |
||||
** 'flash_info_t' structure is defined into 'include/flash.h' |
||||
** and defined as extern into 'common/cmd_flash.c' |
||||
** |
||||
** Note 2: In this file, you have to provide the following functions: |
||||
** ------ |
||||
** unsigned long flash_init(void) |
||||
** called from 'board_init_r()' into 'common/board.c' |
||||
** |
||||
** void flash_print_info(flash_info_t *info) |
||||
** called from 'do_flinfo()' into 'common/cmd_flash.c' |
||||
** |
||||
** int flash_erase(flash_info_t *info, |
||||
** int s_first, |
||||
** int s_last) |
||||
** called from 'do_flerase()' & 'flash_sect_erase()' into 'common/cmd_flash.c' |
||||
** |
||||
** int write_buff (flash_info_t *info, |
||||
** uchar *src, |
||||
** ulong addr, |
||||
** ulong cnt) |
||||
** called from 'flash_write()' into 'common/cmd_flash.c' |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
|
||||
#ifndef CFG_ENV_ADDR |
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) |
||||
#endif |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Functions |
||||
*/ |
||||
static void flash_get_offsets (ulong base, flash_info_t *info); |
||||
static ulong flash_get_size (volatile unsigned char *addr, flash_info_t *info); |
||||
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data); |
||||
static int write_byte (flash_info_t *info, ulong dest, uchar data); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long
|
||||
flash_init (void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
unsigned long size_b0; |
||||
int i; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
|
||||
{ |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
} |
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */ |
||||
|
||||
size_b0 = flash_get_size ((volatile unsigned char *)FLASH_BASE0_PRELIM,
|
||||
&flash_info[0]); |
||||
|
||||
if ( flash_info[0].flash_id == FLASH_UNKNOWN )
|
||||
{ |
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size_b0, size_b0<<20); |
||||
} |
||||
|
||||
/* Remap FLASH according to real size */ |
||||
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); |
||||
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; |
||||
|
||||
/* Re-do sizing to get full correct info */ |
||||
size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE,
|
||||
&flash_info[0]); |
||||
|
||||
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
/* monitor protection ON by default */ |
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE + CFG_MONITOR_LEN-1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* ENV protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR + CFG_ENV_SIZE-1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
flash_info[0].size = size_b0; |
||||
|
||||
return (size_b0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void
|
||||
flash_get_offsets (ulong base,
|
||||
flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
#define SECTOR_64KB 0x00010000 |
||||
|
||||
/* set up sector start adress table */ |
||||
for (i = 0; i < info->sector_count; i++)
|
||||
{ |
||||
info->start[i] = base + (i * SECTOR_64KB); |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void
|
||||
flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
if ( info->flash_id == FLASH_UNKNOWN )
|
||||
{ |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch ( info->flash_id & FLASH_VENDMASK )
|
||||
{ |
||||
case FLASH_MAN_AMD: printf ("AMD "); break; |
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
||||
case FLASH_MAN_STM: printf ("STM (Thomson) "); break; |
||||
default: printf ("Unknown Vendor "); break; |
||||
} |
||||
|
||||
switch ( info->flash_id & FLASH_TYPEMASK )
|
||||
{ |
||||
case FLASH_AM040: printf ("AM29F040 (4 Mbits)\n"); |
||||
break; |
||||
default: printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld KB in %d Sectors\n",
|
||||
info->size >> 10, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i=0; i<info->sector_count; ++i)
|
||||
{ |
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " " |
||||
); |
||||
} |
||||
printf ("\n"); |
||||
|
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
|
||||
static ulong
|
||||
flash_get_size (volatile unsigned char *addr,
|
||||
flash_info_t *info) |
||||
{ |
||||
short i; |
||||
uchar value; |
||||
ulong base = (ulong)addr; |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0x90; |
||||
|
||||
value = addr[0]; |
||||
|
||||
switch ( value )
|
||||
{ |
||||
/* case AMD_MANUFACT: */ |
||||
case 0x01: |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
/* case FUJ_MANUFACT: */ |
||||
case 0x04: |
||||
info->flash_id = FLASH_MAN_FUJ; |
||||
break; |
||||
/* case STM_MANUFACT: */ |
||||
case 0x20: |
||||
info->flash_id = FLASH_MAN_STM; |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
value = addr[1]; /* device ID */ |
||||
|
||||
switch ( value )
|
||||
{ |
||||
case STM_ID_F040B: |
||||
case AMD_ID_F040B: |
||||
info->flash_id += FLASH_AM040; /* 4 Mbits = 512k * 8 */ |
||||
info->sector_count = 8; |
||||
info->size = 0x00080000; |
||||
break; |
||||
|
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
return (0); /* => no or unknown flash */ |
||||
} |
||||
|
||||
/* set up sector start adress table */ |
||||
for (i = 0; i < info->sector_count; i++)
|
||||
{ |
||||
info->start[i] = base + (i * 0x00010000); |
||||
} |
||||
|
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++)
|
||||
{ |
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
||||
/* D0 = 1 if protected */ |
||||
addr = (volatile unsigned char *)(info->start[i]); |
||||
info->protect[i] = addr[2] & 1; |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if ( info->flash_id != FLASH_UNKNOWN )
|
||||
{ |
||||
addr = (volatile unsigned char *)info->start[0]; |
||||
|
||||
*addr = 0xF0; /* reset bank */ |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int |
||||
flash_erase (flash_info_t *info,
|
||||
int s_first,
|
||||
int s_last) |
||||
{ |
||||
volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); |
||||
int flag, prot, sect, l_sect; |
||||
ulong start, now, last; |
||||
|
||||
if ( (s_first < 0) || (s_first > s_last) )
|
||||
{ |
||||
if ( info->flash_id == FLASH_UNKNOWN )
|
||||
{ |
||||
printf ("- missing\n"); |
||||
}
|
||||
else
|
||||
{ |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return ( 1 ); |
||||
} |
||||
|
||||
if ( (info->flash_id == FLASH_UNKNOWN) || |
||||
(info->flash_id > FLASH_AMD_COMP) )
|
||||
{ |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return ( 1 ); |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect)
|
||||
{ |
||||
if ( info->protect[sect] )
|
||||
{ |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if ( prot )
|
||||
{ |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", prot); |
||||
}
|
||||
else
|
||||
{ |
||||
printf ("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0x80; |
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++)
|
||||
{ |
||||
if (info->protect[sect] == 0) /* not protected */ |
||||
{ |
||||
addr = (volatile unsigned char *)(info->start[sect]); |
||||
addr[0] = 0x30; |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if ( flag ) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if ( l_sect < 0 ) |
||||
goto DONE; |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
addr = (volatile unsigned char *)(info->start[l_sect]); |
||||
while ( (addr[0] & 0x80) != 0x80 )
|
||||
{ |
||||
if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT )
|
||||
{ |
||||
printf ("Timeout\n"); |
||||
return ( 1 ); |
||||
} |
||||
/* show that we're waiting */ |
||||
if ( (now - last) > 1000 ) /* every second */ |
||||
{ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
DONE: |
||||
/* reset to read mode */ |
||||
addr = (volatile unsigned char *)info->start[0]; |
||||
addr[0] = 0xF0; /* reset bank */ |
||||
|
||||
printf (" done\n"); |
||||
|
||||
return ( 0 ); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int
|
||||
write_buff (flash_info_t *info,
|
||||
uchar *src,
|
||||
ulong addr,
|
||||
ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
uchar bdata; |
||||
int i, l, rc; |
||||
|
||||
if ( (info->flash_id & FLASH_TYPEMASK) == FLASH_AM040 ) |
||||
{ |
||||
/* Width of the data bus: 8 bits */ |
||||
|
||||
wp = addr; |
||||
|
||||
while ( cnt ) |
||||
{ |
||||
bdata = *src++; |
||||
|
||||
if ( (rc = write_byte(info, wp, bdata)) != 0 ) |
||||
{ |
||||
return (rc); |
||||
} |
||||
|
||||
++wp; |
||||
--cnt; |
||||
} |
||||
|
||||
return ( 0 ); |
||||
} |
||||
else |
||||
{ |
||||
/* Width of the data bus: 32 bits */ |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ( (l = addr - wp) != 0 )
|
||||
{ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp)
|
||||
{ |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i)
|
||||
{ |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp)
|
||||
{ |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ( (rc = write_word(info, wp, data)) != 0 )
|
||||
{ |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while ( cnt >= 4 )
|
||||
{ |
||||
data = 0; |
||||
for (i=0; i<4; ++i)
|
||||
{ |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ( (rc = write_word(info, wp, data)) != 0 )
|
||||
{ |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if ( cnt == 0 )
|
||||
{ |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp)
|
||||
{ |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp)
|
||||
{ |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int
|
||||
write_word (flash_info_t *info,
|
||||
ulong dest,
|
||||
ulong data) |
||||
{ |
||||
vu_long *addr = (vu_long*)(info->start[0]); |
||||
ulong start; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ( (*((vu_long *)dest) & data) != data )
|
||||
{ |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0x00AA00AA; |
||||
addr[0x02AA] = 0x00550055; |
||||
addr[0x0555] = 0x00A000A0; |
||||
|
||||
*((vu_long *)dest) = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if ( flag ) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
|
||||
{ |
||||
if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
|
||||
{ |
||||
return (1); |
||||
} |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a byte to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int
|
||||
write_byte (flash_info_t *info,
|
||||
ulong dest,
|
||||
uchar data) |
||||
{ |
||||
volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]); |
||||
ulong start; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ( (*((volatile unsigned char *)dest) & data) != data )
|
||||
{ |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0x0555] = 0xAA; |
||||
addr[0x02AA] = 0x55; |
||||
addr[0x0555] = 0xA0; |
||||
|
||||
*((volatile unsigned char *)dest) = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if ( flag ) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
|
||||
{ |
||||
if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
|
||||
{ |
||||
return (1); |
||||
} |
||||
} |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
@ -0,0 +1,146 @@ |
||||
/* |
||||
**===================================================================== |
||||
** |
||||
** Copyright (C) 2000, 2001, 2002, 2003 |
||||
** The LEOX team <team@leox.org>, http://www.leox.org |
||||
** |
||||
** LEOX.org is about the development of free hardware and software resources |
||||
** for system on chip. |
||||
** |
||||
** Description: U-Boot port on the LEOX's ELPT860 CPU board |
||||
** ~~~~~~~~~~~ |
||||
** |
||||
**===================================================================== |
||||
** |
||||
** This program is free software; you can redistribute it and/or |
||||
** modify it under the terms of the GNU General Public License as |
||||
** published by the Free Software Foundation; either version 2 of |
||||
** the License, or (at your option) any later version. |
||||
** |
||||
** This program is distributed in the hope that it will be useful, |
||||
** but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
** GNU General Public License for more details. |
||||
** |
||||
** You should have received a copy of the GNU General Public License |
||||
** along with this program; if not, write to the Free Software |
||||
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
** MA 02111-1307 USA |
||||
** |
||||
**===================================================================== |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_ppc/ppcstring.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
lib_generic/string.o (.text) |
||||
lib_ppc/cache.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_ppc/time.o (.text) |
||||
lib_ppc/ticks.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,140 @@ |
||||
/* |
||||
**===================================================================== |
||||
** |
||||
** Copyright (C) 2000, 2001, 2002, 2003 |
||||
** The LEOX team <team@leox.org>, http://www.leox.org |
||||
** |
||||
** LEOX.org is about the development of free hardware and software resources |
||||
** for system on chip. |
||||
** |
||||
** Description: U-Boot port on the LEOX's ELPT860 CPU board |
||||
** ~~~~~~~~~~~ |
||||
** |
||||
**===================================================================== |
||||
** |
||||
** This program is free software; you can redistribute it and/or |
||||
** modify it under the terms of the GNU General Public License as |
||||
** published by the Free Software Foundation; either version 2 of |
||||
** the License, or (at your option) any later version. |
||||
** |
||||
** This program is distributed in the hope that it will be useful, |
||||
** but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
** GNU General Public License for more details. |
||||
** |
||||
** You should have received a copy of the GNU General Public License |
||||
** along with this program; if not, write to the Free Software |
||||
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
** MA 02111-1307 USA |
||||
** |
||||
**===================================================================== |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
||||
@ -0,0 +1,40 @@ |
||||
#
|
||||
# (C) Copyright 2001-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o flash.o plx9030.o
|
||||
|
||||
$(LIB): .depend $(OBJS) |
||||
$(AR) crv $@ $^
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,36 @@ |
||||
#
|
||||
# (C) Copyright 2001-2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# CPC45 board
|
||||
#
|
||||
|
||||
|
||||
ifeq ($(CONFIG_BOOT_ROM),y) |
||||
TEXT_BASE := 0xFFF00000
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
|
||||
else |
||||
TEXT_BASE := 0xFFF00000
|
||||
endif |
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)
|
||||
@ -0,0 +1,173 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc824x.h> |
||||
#include <asm/processor.h> |
||||
#include <pci.h> |
||||
|
||||
int sysControlDisplay(int digit, uchar ascii_code);
|
||||
extern void Plx9030Init(void); |
||||
|
||||
/* We have to clear the initial data area here. Couldn't have done it
|
||||
* earlier because DRAM had not been initialized. |
||||
*/ |
||||
int board_pre_init(void) |
||||
{ |
||||
|
||||
/* enable DUAL UART Mode on CPC45 */ |
||||
*(uchar*)DUART_DCR |= 0x1; /* set DCM bit */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
/*
|
||||
char revision = BOARD_REV; |
||||
*/ |
||||
ulong busfreq = get_bus_freq(0); |
||||
char buf[32]; |
||||
|
||||
printf("CPC45 "); |
||||
/*
|
||||
printf("Revision %d ", revision); |
||||
*/ |
||||
printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
long int initdram(int board_type) |
||||
{ |
||||
int i, cnt; |
||||
volatile uchar * base = CFG_SDRAM_BASE; |
||||
volatile ulong * addr; |
||||
ulong save[32]; |
||||
ulong val, ret = 0; |
||||
|
||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { |
||||
|
||||
addr = (volatile ulong *)base + cnt; |
||||
save[i++] = *addr; |
||||
*addr = ~cnt; |
||||
} |
||||
|
||||
addr = (volatile ulong *)base; |
||||
save[i] = *addr; |
||||
*addr = 0; |
||||
|
||||
if (*addr != 0) { |
||||
*addr = save[i]; |
||||
goto Done; |
||||
} |
||||
|
||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) { |
||||
addr = (volatile ulong *)base + cnt; |
||||
val = *addr; |
||||
*addr = save[--i]; |
||||
if (val != ~cnt) { |
||||
ulong new_bank0_end = cnt * sizeof(long) - 1; |
||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1); |
||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1); |
||||
mear1 = (mear1 & 0xFFFFFF00) | |
||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); |
||||
emear1 = (emear1 & 0xFFFFFF00) | |
||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); |
||||
mpc824x_mpc107_setreg(MEAR1, mear1); |
||||
mpc824x_mpc107_setreg(EMEAR1, emear1); |
||||
|
||||
ret = cnt * sizeof(long); |
||||
goto Done; |
||||
} |
||||
} |
||||
|
||||
ret = CFG_MAX_RAM_SIZE; |
||||
Done: |
||||
return ret; |
||||
} |
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
#ifndef CONFIG_PCI_PNP |
||||
|
||||
static struct pci_config_table pci_sandpoint_config_table[] = { |
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, |
||||
{ } |
||||
}; |
||||
#endif |
||||
|
||||
|
||||
struct pci_controller hose = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table: pci_sandpoint_config_table, |
||||
#endif |
||||
}; |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
pci_mpc824x_init(&hose); |
||||
|
||||
/* init PCI_to_LOCAL Bus BRIDGE */ |
||||
Plx9030Init(); |
||||
|
||||
sysControlDisplay(0,' '); |
||||
sysControlDisplay(1,'C'); |
||||
sysControlDisplay(2,'P'); |
||||
sysControlDisplay(3,'C'); |
||||
sysControlDisplay(4,' '); |
||||
sysControlDisplay(5,'4'); |
||||
sysControlDisplay(6,'5'); |
||||
sysControlDisplay(7,' '); |
||||
|
||||
} |
||||
|
||||
/**************************************************************************
|
||||
* |
||||
* sysControlDisplay - controls one of the Alphanum. Display digits. |
||||
* |
||||
* This routine will write an ASCII character to the display digit requested. |
||||
* |
||||
* SEE ALSO: |
||||
* |
||||
* RETURNS: NA |
||||
*/ |
||||
|
||||
int sysControlDisplay |
||||
( |
||||
int digit, /* number of digit 0..7 */ |
||||
uchar ascii_code /* ASCII code */ |
||||
) |
||||
{ |
||||
if ((digit < 0) || (digit > 7)) |
||||
return (-1); |
||||
|
||||
*((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code; |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
@ -0,0 +1,493 @@ |
||||
/*
|
||||
* (C) Copyright 2001-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc824x.h> |
||||
#include <asm/processor.h> |
||||
|
||||
#if defined(CFG_ENV_IS_IN_FLASH) |
||||
# ifndef CFG_ENV_ADDR |
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) |
||||
# endif |
||||
# ifndef CFG_ENV_SIZE |
||||
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
||||
# endif |
||||
# ifndef CFG_ENV_SECT_SIZE |
||||
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE |
||||
# endif |
||||
#endif |
||||
|
||||
#define FLASH_BANK_SIZE 0x800000 |
||||
#define MAIN_SECT_SIZE 0x40000 |
||||
#define PARAM_SECT_SIZE 0x8000 |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
||||
|
||||
static int write_data (flash_info_t *info, ulong dest, ulong *data); |
||||
static void write_via_fpu(vu_long *addr, ulong *data); |
||||
static __inline__ unsigned long get_msr(void); |
||||
static __inline__ void set_msr(unsigned long msr); |
||||
|
||||
/*---------------------------------------------------------------------*/ |
||||
#undef DEBUG_FLASH |
||||
|
||||
/*---------------------------------------------------------------------*/ |
||||
#ifdef DEBUG_FLASH |
||||
#define DEBUGF(fmt,args...) printf(fmt ,##args) |
||||
#else |
||||
#define DEBUGF(fmt,args...) |
||||
#endif |
||||
/*---------------------------------------------------------------------*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init(void) |
||||
{ |
||||
int i, j; |
||||
ulong size = 0; |
||||
uchar tempChar; |
||||
|
||||
/* Enable flash writes on CPC45 */ |
||||
|
||||
tempChar = BOARD_CTRL; |
||||
|
||||
tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1); |
||||
|
||||
tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0); |
||||
|
||||
BOARD_CTRL = tempChar; |
||||
|
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
||||
vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE); |
||||
|
||||
addr[0] = 0x00900090; |
||||
|
||||
DEBUGF ("Flash bank # %d:\n" |
||||
"\tManuf. ID @ 0x%08lX: 0x%08lX\n" |
||||
"\tDevice ID @ 0x%08lX: 0x%08lX\n", |
||||
i, |
||||
(ulong)(&addr[0]), addr[0], |
||||
(ulong)(&addr[2]), addr[2]); |
||||
|
||||
|
||||
if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) && |
||||
(addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) |
||||
{ |
||||
|
||||
flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) | |
||||
(INTEL_ID_28F160F3T & FLASH_TYPEMASK); |
||||
|
||||
} else { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
addr[0] = 0xFFFFFFFF; |
||||
goto Done; |
||||
} |
||||
|
||||
DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id); |
||||
|
||||
addr[0] = 0xFFFFFFFF; |
||||
|
||||
flash_info[i].size = FLASH_BANK_SIZE; |
||||
flash_info[i].sector_count = CFG_MAX_FLASH_SECT; |
||||
memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); |
||||
for (j = 0; j < flash_info[i].sector_count; j++) { |
||||
if (j > 30) { |
||||
flash_info[i].start[j] = CFG_FLASH_BASE + |
||||
i * FLASH_BANK_SIZE + |
||||
(MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE; |
||||
} else { |
||||
flash_info[i].start[j] = CFG_FLASH_BASE + |
||||
i * FLASH_BANK_SIZE + |
||||
j * MAIN_SECT_SIZE; |
||||
} |
||||
} |
||||
size += flash_info[i].size; |
||||
} |
||||
|
||||
/* Protect monitor and environment sectors
|
||||
*/ |
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, |
||||
&flash_info[1]); |
||||
#else |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, |
||||
&flash_info[0]); |
||||
#endif |
||||
#endif |
||||
|
||||
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) |
||||
#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, |
||||
&flash_info[1]); |
||||
#else |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, |
||||
&flash_info[0]); |
||||
#endif |
||||
#endif |
||||
|
||||
Done: |
||||
return size; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
switch ((i = info->flash_id & FLASH_VENDMASK)) { |
||||
case (FLASH_MAN_INTEL & FLASH_VENDMASK): |
||||
printf ("Intel: "); |
||||
break; |
||||
default: |
||||
printf ("Unknown Vendor 0x%04x ", i); |
||||
break; |
||||
} |
||||
|
||||
switch ((i = info->flash_id & FLASH_TYPEMASK)) { |
||||
case (INTEL_ID_28F160F3T & FLASH_TYPEMASK): |
||||
printf ("28F160F3T (16Mbit)\n"); |
||||
break; |
||||
default: |
||||
printf ("Unknown Chip Type 0x%04x\n", i); |
||||
goto Done; |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
if ((i % 5) == 0) { |
||||
printf ("\n "); |
||||
} |
||||
printf (" %08lX%s", info->start[i], |
||||
info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf ("\n"); |
||||
|
||||
Done: |
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
int flag, prot, sect; |
||||
ulong start, now, last; |
||||
|
||||
DEBUGF ("Erase flash bank %d sect %d ... %d\n", |
||||
info - &flash_info[0], s_first, s_last); |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) != |
||||
(FLASH_MAN_INTEL & FLASH_VENDMASK)) { |
||||
printf ("Can erase only Intel flash types - aborted\n"); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
vu_long *addr = (vu_long *)(info->start[sect]); |
||||
|
||||
DEBUGF ("Erase sect %d @ 0x%08lX\n", |
||||
sect, (ulong)addr); |
||||
|
||||
/* Disable interrupts which might cause a timeout
|
||||
* here. |
||||
*/ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0] = 0x00500050; /* clear status register */ |
||||
addr[0] = 0x00200020; /* erase setup */ |
||||
addr[0] = 0x00D000D0; /* erase confirm */ |
||||
|
||||
addr[1] = 0x00500050; /* clear status register */ |
||||
addr[1] = 0x00200020; /* erase setup */ |
||||
addr[1] = 0x00D000D0; /* erase confirm */ |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
while (((addr[0] & 0x00800080) != 0x00800080) || |
||||
((addr[1] & 0x00800080) != 0x00800080) ) { |
||||
if ((now=get_timer(start)) > |
||||
CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
addr[0] = 0x00B000B0; /* suspend erase */ |
||||
addr[0] = 0x00FF00FF; /* to read mode */ |
||||
return 1; |
||||
} |
||||
|
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
addr[0] = 0x00FF00FF; |
||||
} |
||||
} |
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
* 4 - Flash not identified |
||||
*/ |
||||
|
||||
#define FLASH_WIDTH 8 /* flash bus width in bytes */ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong wp, cp, msr; |
||||
int l, rc, i; |
||||
ulong data[2]; |
||||
ulong *datah = &data[0]; |
||||
ulong *datal = &data[1]; |
||||
|
||||
DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n", |
||||
addr, (ulong)src, cnt); |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
return 4; |
||||
} |
||||
|
||||
msr = get_msr(); |
||||
set_msr(msr | MSR_FP); |
||||
|
||||
wp = (addr & ~(FLASH_WIDTH-1)); /* get lower aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
*datah = *datal = 0; |
||||
|
||||
for (i = 0, cp = wp; i < l; i++, cp++) { |
||||
if (i >= 4) { |
||||
*datah = (*datah << 8) | |
||||
((*datal & 0xFF000000) >> 24); |
||||
} |
||||
|
||||
*datal = (*datal << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i < FLASH_WIDTH && cnt > 0; ++i) { |
||||
char tmp; |
||||
|
||||
tmp = *src; |
||||
|
||||
src++; |
||||
|
||||
if (i >= 4) { |
||||
*datah = (*datah << 8) | |
||||
((*datal & 0xFF000000) >> 24); |
||||
} |
||||
|
||||
*datal = (*datal << 8) | tmp; |
||||
|
||||
--cnt; ++cp; |
||||
} |
||||
|
||||
for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) { |
||||
if (i >= 4) { |
||||
*datah = (*datah << 8) | |
||||
((*datal & 0xFF000000) >> 24); |
||||
} |
||||
|
||||
*datal = (*datah << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_data(info, wp, data)) != 0) { |
||||
set_msr(msr); |
||||
return (rc); |
||||
} |
||||
|
||||
wp += FLASH_WIDTH; |
||||
} |
||||
|
||||
/*
|
||||
* handle FLASH_WIDTH aligned part |
||||
*/ |
||||
while (cnt >= FLASH_WIDTH) { |
||||
*datah = *(ulong *)src; |
||||
*datal = *(ulong *)(src + 4); |
||||
if ((rc = write_data(info, wp, data)) != 0) { |
||||
set_msr(msr); |
||||
return (rc); |
||||
} |
||||
wp += FLASH_WIDTH; |
||||
cnt -= FLASH_WIDTH; |
||||
src += FLASH_WIDTH; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
set_msr(msr); |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
*datah = *datal = 0; |
||||
for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) { |
||||
char tmp; |
||||
|
||||
tmp = *src; |
||||
|
||||
src++; |
||||
|
||||
if (i >= 4) { |
||||
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); |
||||
} |
||||
|
||||
*datal = (*datal << 8) | tmp; |
||||
|
||||
--cnt; |
||||
} |
||||
|
||||
for (; i < FLASH_WIDTH; ++i, ++cp) { |
||||
if (i >= 4) { |
||||
*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24); |
||||
} |
||||
|
||||
*datal = (*datal << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
rc = write_data(info, wp, data); |
||||
set_msr(msr); |
||||
|
||||
return (rc); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_data (flash_info_t *info, ulong dest, ulong *data) |
||||
{ |
||||
vu_long *addr = (vu_long *)dest; |
||||
ulong start; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if (((addr[0] & data[0]) != data[0]) || |
||||
((addr[1] & data[1]) != data[1]) ) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
|
||||
addr[0] = 0x00400040; /* write setup */ |
||||
write_via_fpu(addr, data); |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
start = get_timer (0); |
||||
|
||||
while (((addr[0] & 0x00800080) != 0x00800080) || |
||||
((addr[1] & 0x00800080) != 0x00800080) ) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
addr[0] = 0x00FF00FF; /* restore read mode */ |
||||
return (1); |
||||
} |
||||
} |
||||
|
||||
addr[0] = 0x00FF00FF; /* restore read mode */ |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void write_via_fpu(vu_long *addr, ulong *data) |
||||
{ |
||||
__asm__ __volatile__ ("lfd 1, 0(%0)" : : "r" (data)); |
||||
__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr)); |
||||
} |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static __inline__ unsigned long get_msr(void) |
||||
{ |
||||
unsigned long msr; |
||||
|
||||
__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :); |
||||
return msr; |
||||
} |
||||
|
||||
static __inline__ void set_msr(unsigned long msr) |
||||
{ |
||||
__asm__ __volatile__ ("mtmsr %0" : : "r" (msr)); |
||||
} |
||||
@ -0,0 +1,174 @@ |
||||
/* Plx9030.c - system configuration module for PLX9030 PCI to Local Bus Bridge */ |
||||
/*
|
||||
* (C) Copyright 2002-2003 |
||||
* Josef Wagner, MicroSys GmbH, wagner@microsys.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Date Modification by |
||||
* ------- ---------------------------------------------- --- |
||||
* 30sep02 converted from VxWorks to LINUX wa |
||||
*/ |
||||
|
||||
|
||||
/*
|
||||
DESCRIPTION |
||||
|
||||
This is the configuration module for the PLX9030 PCI to Local Bus Bridge. |
||||
It configures the Chip select lines for SRAM (CS0), ST16C552 (CS1,CS2), Display and local |
||||
registers (CS3) on CPC45. |
||||
*/ |
||||
|
||||
/* includes */ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <net.h> |
||||
#include <asm/io.h> |
||||
#include <pci.h> |
||||
|
||||
/* imports */ |
||||
|
||||
|
||||
/* defines */ |
||||
#define PLX9030_VENDOR_ID 0x10B5 |
||||
#define PLX9030_DEVICE_ID 0x9030 |
||||
|
||||
#undef PLX_DEBUG |
||||
|
||||
/* PLX9030 register offsets */ |
||||
#define P9030_LAS0RR 0x00 |
||||
#define P9030_LAS1RR 0x04 |
||||
#define P9030_LAS2RR 0x08 |
||||
#define P9030_LAS3RR 0x0c |
||||
#define P9030_EROMRR 0x10 |
||||
#define P9030_LAS0BA 0x14 |
||||
#define P9030_LAS1BA 0x18 |
||||
#define P9030_LAS2BA 0x1c |
||||
#define P9030_LAS3BA 0x20 |
||||
#define P9030_EROMBA 0x24 |
||||
#define P9030_LAS0BRD 0x28 |
||||
#define P9030_LAS1BRD 0x2c |
||||
#define P9030_LAS2BRD 0x30 |
||||
#define P9030_LAS3BRD 0x34 |
||||
#define P9030_EROMBRD 0x38 |
||||
#define P9030_CS0BASE 0x3C |
||||
#define P9030_CS1BASE 0x40 |
||||
#define P9030_CS2BASE 0x44 |
||||
#define P9030_CS3BASE 0x48 |
||||
#define P9030_INTCSR 0x4c |
||||
#define P9030_CNTRL 0x50 |
||||
#define P9030_GPIOC 0x54 |
||||
|
||||
/* typedefs */ |
||||
|
||||
|
||||
/* locals */ |
||||
|
||||
static struct pci_device_id supported[] = { |
||||
{ PLX9030_VENDOR_ID, PLX9030_DEVICE_ID }, |
||||
{ } |
||||
}; |
||||
|
||||
/* forward declarations */ |
||||
void sysOutLong(ulong address, ulong value); |
||||
|
||||
|
||||
/***************************************************************************
|
||||
* |
||||
* Plx9030Init - init CS0..CS3 for CPC45 |
||||
* |
||||
* |
||||
* RETURNS: N/A |
||||
*/ |
||||
|
||||
void Plx9030Init (void) |
||||
{ |
||||
pci_dev_t devno; |
||||
ulong membaseCsr; /* base address of device memory space */ |
||||
int idx = 0; /* general index */ |
||||
|
||||
|
||||
/* find plx9030 device */ |
||||
|
||||
if ((devno = pci_find_devices(supported, idx++)) < 0) |
||||
{ |
||||
printf("No PLX9030 device found !!\n"); |
||||
return; |
||||
} |
||||
|
||||
|
||||
#ifdef PLX_DEBUG |
||||
printf("PLX 9030 device found ! devno = 0x%x\n",devno); |
||||
#endif |
||||
|
||||
membaseCsr = PCI_PLX9030_MEMADDR; |
||||
|
||||
/* set base address */ |
||||
pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, membaseCsr); |
||||
|
||||
/* enable mapped memory and IO addresses */ |
||||
pci_write_config_dword(devno, |
||||
PCI_COMMAND, |
||||
PCI_COMMAND_MEMORY | |
||||
PCI_COMMAND_MASTER); |
||||
|
||||
|
||||
/* configure GBIOC */ |
||||
sysOutLong((membaseCsr + P9030_GPIOC), 0x00000FC0); /* CS2/CS3 enable */ |
||||
|
||||
/* configure CS0 (SRAM) */ |
||||
sysOutLong((membaseCsr + P9030_LAS0BA), 0x00000001); /* enable space base */ |
||||
sysOutLong((membaseCsr + P9030_LAS0RR), 0x0FE00000); /* 2 MByte */ |
||||
sysOutLong((membaseCsr + P9030_LAS0BRD), 0x51928900); /* 4 wait states */ |
||||
sysOutLong((membaseCsr + P9030_CS0BASE), 0x00100001); /* enable 2 MByte */
|
||||
/* remap CS0 (SRAM) */ |
||||
pci_write_config_dword(devno, PCI_BASE_ADDRESS_2, SRAM_BASE); |
||||
|
||||
/* configure CS1 (ST16552 / CHAN A) */ |
||||
sysOutLong((membaseCsr + P9030_LAS1BA), 0x00400001); /* enable space base */ |
||||
sysOutLong((membaseCsr + P9030_LAS1RR), 0x0FFFFF00); /* 256 byte */ |
||||
sysOutLong((membaseCsr + P9030_LAS1BRD), 0x55122900); /* 4 wait states */ |
||||
sysOutLong((membaseCsr + P9030_CS1BASE), 0x00400081); /* enable 256 Byte */
|
||||
/* remap CS1 (ST16552 / CHAN A) */ |
||||
/* remap CS1 (ST16552 / CHAN A) */ |
||||
pci_write_config_dword(devno, PCI_BASE_ADDRESS_3, ST16552_A_BASE); |
||||
|
||||
/* configure CS2 (ST16552 / CHAN B) */ |
||||
sysOutLong((membaseCsr + P9030_LAS2BA), 0x00800001); /* enable space base */ |
||||
sysOutLong((membaseCsr + P9030_LAS2RR), 0x0FFFFF00); /* 256 byte */ |
||||
sysOutLong((membaseCsr + P9030_LAS2BRD), 0x55122900); /* 4 wait states */ |
||||
sysOutLong((membaseCsr + P9030_CS2BASE), 0x00800081); /* enable 256 Byte */
|
||||
/* remap CS2 (ST16552 / CHAN B) */ |
||||
pci_write_config_dword(devno, PCI_BASE_ADDRESS_4, ST16552_B_BASE); |
||||
|
||||
/* configure CS3 (BCSR) */ |
||||
sysOutLong((membaseCsr + P9030_LAS3BA), 0x00C00001); /* enable space base */ |
||||
sysOutLong((membaseCsr + P9030_LAS3RR), 0x0FFFFF00); /* 256 byte */ |
||||
sysOutLong((membaseCsr + P9030_LAS3BRD), 0x55357A80); /* 9 wait states */ |
||||
sysOutLong((membaseCsr + P9030_CS3BASE), 0x00C00081); /* enable 256 Byte */
|
||||
/* remap CS3 (DISPLAY and BCSR) */ |
||||
pci_write_config_dword(devno, PCI_BASE_ADDRESS_5, BCSR_BASE); |
||||
} |
||||
|
||||
void sysOutLong(ulong address, ulong value) |
||||
{ |
||||
*(ulong*)address = cpu_to_le32(value); |
||||
} |
||||
|
||||
@ -0,0 +1,128 @@ |
||||
/* |
||||
* (C) Copyright 2001-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc824x/start.o (.text) |
||||
lib_ppc/board.o (.text) |
||||
lib_ppc/ppcstring.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .; |
||||
common/environment.o (.text) |
||||
|
||||
*(.text) |
||||
|
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
|
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
||||
@ -0,0 +1,24 @@ |
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x80000000
|
||||
@ -0,0 +1,448 @@ |
||||
/*
|
||||
* (C) Copyright 2001-2003 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* |
||||
* Configuration settings for the CPC45 board. |
||||
* |
||||
*/ |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC824X 1 |
||||
#define CONFIG_MPC8245 1 |
||||
#define CONFIG_CPC45 1 |
||||
|
||||
|
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 9600 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_PCI | \
|
||||
0 /* CFG_CMD_DATE */ ) |
||||
|
||||
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
|
||||
*/ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
|
||||
#if 1 |
||||
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */ |
||||
#endif |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* Print Buffer Size
|
||||
*/ |
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) |
||||
|
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_LOAD_ADDR 0x00100000 /* Default load address */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
|
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
|
||||
#if defined(CONFIG_BOOT_ROM) |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#else |
||||
#define CFG_FLASH_BASE 0xFF800000 |
||||
#endif |
||||
|
||||
#define CFG_RESET_ADDRESS 0xFFF00100 |
||||
|
||||
#define CFG_EUMB_ADDR 0xFCE00000 |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00004000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ |
||||
|
||||
/* Maximum amount of RAM.
|
||||
*/ |
||||
#define CFG_MAX_RAM_SIZE 0x10000000 |
||||
|
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
#undef CFG_RAMBOOT |
||||
#else |
||||
#define CFG_RAMBOOT |
||||
#endif |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area |
||||
*/ |
||||
|
||||
/* Size in bytes reserved for initial data
|
||||
*/ |
||||
#define CFG_GBL_DATA_SIZE 128 |
||||
|
||||
#define CFG_INIT_RAM_ADDR 0x40000000 |
||||
#define CFG_INIT_RAM_END 0x1000 |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
|
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
|
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600) |
||||
#define DUART_DCR (CFG_EUMB_ADDR + 0x4511) |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
* For the detail description refer to the MPC8240 user's manual. |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 |
||||
#define CFG_HZ 1000 |
||||
/*
|
||||
* SDRAM Configuration Settings |
||||
* Please note: currently only 64 and 128 MB SDRAM size supported |
||||
* set CFG_SDRAM_SIZE to 64 or 128 |
||||
* Memory configuration using SPD information stored on the SODIMMs |
||||
* not yet supported. |
||||
*/ |
||||
|
||||
#define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */ |
||||
|
||||
/* Bit-field values for MCCR1.
|
||||
*/ |
||||
#define CFG_ROMNAL 0 |
||||
#define CFG_ROMFAL 7 |
||||
|
||||
#if (CFG_SDRAM_SIZE == 64) /* 64 MB */ |
||||
#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */ |
||||
#elif (CFG_SDRAM_SIZE == 128) /* 128 MB */ |
||||
#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */ |
||||
#else |
||||
# error "SDRAM size not supported" |
||||
#endif |
||||
#define CFG_BANK1_ROW 0 |
||||
#define CFG_BANK2_ROW 0 |
||||
#define CFG_BANK3_ROW 0 |
||||
#define CFG_BANK4_ROW 0 |
||||
#define CFG_BANK5_ROW 0 |
||||
#define CFG_BANK6_ROW 0 |
||||
#define CFG_BANK7_ROW 0 |
||||
|
||||
/* Bit-field values for MCCR2.
|
||||
*/ |
||||
#define CFG_REFINT 430 /* Refresh interval */ |
||||
|
||||
/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
|
||||
*/ |
||||
#define CFG_BSTOPRE 192 |
||||
|
||||
/* Bit-field values for MCCR3.
|
||||
*/ |
||||
#define CFG_REFREC 2 /* Refresh to activate interval */ |
||||
#define CFG_RDLAT 3 /* Data latancy from read command */ |
||||
|
||||
/* Bit-field values for MCCR4.
|
||||
*/ |
||||
#define CFG_PRETOACT 2 /* Precharge to activate interval */ |
||||
#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */ |
||||
#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */ |
||||
#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */ |
||||
#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */ |
||||
#define CFG_ACTORW 2 |
||||
#define CFG_REGISTERD_TYPE_BUFFER 1 |
||||
#define CFG_EXTROM 1 |
||||
#define CFG_REGDIMM 0 |
||||
|
||||
/* Memory bank settings.
|
||||
* Only bits 20-29 are actually used from these vales to set the |
||||
* start/end addresses. The upper two bits will always be 0, and the lower |
||||
* 20 bits will be 0x00000 for a start address, or 0xfffff for an end |
||||
* address. Refer to the MPC8240 book. |
||||
*/ |
||||
|
||||
#define CFG_BANK0_START 0x00000000 |
||||
#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1) |
||||
#define CFG_BANK0_ENABLE 1 |
||||
#define CFG_BANK1_START 0x3ff00000 |
||||
#define CFG_BANK1_END 0x3fffffff |
||||
#define CFG_BANK1_ENABLE 0 |
||||
#define CFG_BANK2_START 0x3ff00000 |
||||
#define CFG_BANK2_END 0x3fffffff |
||||
#define CFG_BANK2_ENABLE 0 |
||||
#define CFG_BANK3_START 0x3ff00000 |
||||
#define CFG_BANK3_END 0x3fffffff |
||||
#define CFG_BANK3_ENABLE 0 |
||||
#define CFG_BANK4_START 0x3ff00000 |
||||
#define CFG_BANK4_END 0x3fffffff |
||||
#define CFG_BANK4_ENABLE 0 |
||||
#define CFG_BANK5_START 0x3ff00000 |
||||
#define CFG_BANK5_END 0x3fffffff |
||||
#define CFG_BANK5_ENABLE 0 |
||||
#define CFG_BANK6_START 0x3ff00000 |
||||
#define CFG_BANK6_END 0x3fffffff |
||||
#define CFG_BANK6_ENABLE 0 |
||||
#define CFG_BANK7_START 0x3ff00000 |
||||
#define CFG_BANK7_END 0x3fffffff |
||||
#define CFG_BANK7_ENABLE 0 |
||||
|
||||
#define CFG_ODCR 0xff |
||||
|
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) |
||||
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT) |
||||
#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP) |
||||
|
||||
#define CFG_DBAT0L CFG_IBAT0L |
||||
#define CFG_DBAT0U CFG_IBAT0U |
||||
#define CFG_DBAT1L CFG_IBAT1L |
||||
#define CFG_DBAT1U CFG_IBAT1U |
||||
#define CFG_DBAT2L CFG_IBAT2L |
||||
#define CFG_DBAT2U CFG_IBAT2U |
||||
#define CFG_DBAT3L CFG_IBAT3L |
||||
#define CFG_DBAT3U CFG_IBAT3U |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
||||
#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */ |
||||
#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */ |
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* Warining: environment is not EMBEDDED in the ppcboot code.
|
||||
* It's stored in flash separately. |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7C0000) |
||||
#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */ |
||||
#define CFG_ENV_OFFSET 0 /* starting right at the beginning */ |
||||
#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
#define SRAM_BASE 0x80000000 /* SRAM base address */ |
||||
#define SRAM_END 0x801FFFFF |
||||
|
||||
/*---------------------------------------------------------------------*/ |
||||
/* CPC45 Memory Map */ |
||||
/*---------------------------------------------------------------------*/ |
||||
#define SRAM_BASE 0x80000000 /* SRAM base address */ |
||||
#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ |
||||
#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ |
||||
#define BCSR_BASE 0x80600000 /* board control / status registers */ |
||||
#define DISPLAY_BASE 0x80600040 /* DISPLAY base */ |
||||
#define PCMCIA_MEM_BASE 0x81000000 /* PCMCIA memory window base */ |
||||
#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ |
||||
|
||||
|
||||
/*---------------------------------------------------------------------*/ |
||||
/* CPC45 Control/Status Registers */ |
||||
/*---------------------------------------------------------------------*/ |
||||
#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00)) |
||||
#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01)) |
||||
#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02)) |
||||
#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03)) |
||||
#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04)) |
||||
#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05)) |
||||
#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06)) |
||||
#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06)) |
||||
#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06)) |
||||
#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07)) |
||||
|
||||
/* IRQ_ENA_1 bit definitions */ |
||||
#define I_ENA_1_IERA 0x80 /* INTA enable */ |
||||
#define I_ENA_1_IERB 0x40 /* INTB enable */ |
||||
#define I_ENA_1_IERC 0x20 /* INTC enable */ |
||||
#define I_ENA_1_IERD 0x10 /* INTD enable */ |
||||
|
||||
/* IRQ_STAT_1 bit definitions */ |
||||
#define I_STAT_1_INTA 0x80 /* INTA status */ |
||||
#define I_STAT_1_INTB 0x40 /* INTB status */ |
||||
#define I_STAT_1_INTC 0x20 /* INTC status */ |
||||
#define I_STAT_1_INTD 0x10 /* INTD status */ |
||||
|
||||
/* IRQ_ENA_2 bit definitions */ |
||||
#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */ |
||||
#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */ |
||||
#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */ |
||||
#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */ |
||||
#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */ |
||||
#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */ |
||||
#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */ |
||||
#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */ |
||||
|
||||
/* IRQ_STAT_2 bit definitions */ |
||||
#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */ |
||||
#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */ |
||||
#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */ |
||||
#define I_STAT_2_RTC 0x10 /* RTC IRQ status */ |
||||
#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */ |
||||
#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */ |
||||
#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */ |
||||
#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */ |
||||
|
||||
/* BOARD_CTRL bit definitions */ |
||||
#define USER_LEDS 2 /* 2 user LEDs */ |
||||
|
||||
#if (USER_LEDS == 4) |
||||
#define B_CTRL_WRSE 0x80 |
||||
#define B_CTRL_KRSE 0x40 |
||||
#define B_CTRL_FWRE 0x20 /* Flash write enable */ |
||||
#define B_CTRL_FWPT 0x10 /* Flash write protect */ |
||||
#define B_CTRL_LED3 0x08 /* LED 3 control */ |
||||
#define B_CTRL_LED2 0x04 /* LED 2 control */ |
||||
#define B_CTRL_LED1 0x02 /* LED 1 control */ |
||||
#define B_CTRL_LED0 0x01 /* LED 0 control */ |
||||
#else |
||||
#define B_CTRL_WRSE 0x80 |
||||
#define B_CTRL_KRSE 0x40 |
||||
#define B_CTRL_FWRE_1 0x20 /* Flash write enable */ |
||||
#define B_CTRL_FWPT_1 0x10 /* Flash write protect */ |
||||
#define B_CTRL_LED1 0x08 /* LED 1 control */ |
||||
#define B_CTRL_LED0 0x04 /* LED 0 control */ |
||||
#define B_CTRL_FWRE_0 0x02 /* Flash write enable */ |
||||
#define B_CTRL_FWPT_0 0x01 /* Flash write protect */ |
||||
#endif |
||||
|
||||
/* BOARD_STAT bit definitions */ |
||||
#define B_STAT_WDGE 0x80 |
||||
#define B_STAT_WDGS 0x40 |
||||
#define B_STAT_WRST 0x20 |
||||
#define B_STAT_KRST 0x10 |
||||
#define B_STAT_CSW3 0x08 /* sitch bit 3 status */ |
||||
#define B_STAT_CSW2 0x04 /* sitch bit 2 status */ |
||||
#define B_STAT_CSW1 0x02 /* sitch bit 1 status */ |
||||
#define B_STAT_CSW0 0x01 /* sitch bit 0 status */ |
||||
|
||||
/*---------------------------------------------------------------------*/ |
||||
/* Display addresses */ |
||||
/*---------------------------------------------------------------------*/ |
||||
#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */ |
||||
#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */ |
||||
#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */ |
||||
|
||||
#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */ |
||||
#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */ |
||||
|
||||
#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */ |
||||
#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */ |
||||
#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */ |
||||
#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */ |
||||
#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */ |
||||
#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */ |
||||
#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */ |
||||
#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CONFIG_PCI /* include pci support */ |
||||
#undef CONFIG_PCI_PNP |
||||
|
||||
#define CONFIG_NET_MULTI /* Multi ethernet cards support */ |
||||
|
||||
#define CONFIG_EEPRO100 |
||||
|
||||
#define PCI_ENET0_IOADDR 0x00104000 |
||||
#define PCI_ENET0_MEMADDR 0x82000000 |
||||
#define PCI_PLX9030_MEMADDR 0x82100000 |
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,390 @@ |
||||
/*
|
||||
**===================================================================== |
||||
** |
||||
** Copyright (C) 2000, 2001, 2002, 2003 |
||||
** The LEOX team <team@leox.org>, http://www.leox.org
|
||||
** |
||||
** LEOX.org is about the development of free hardware and software resources |
||||
** for system on chip. |
||||
** |
||||
** Description: U-Boot port on the LEOX's ELPT860 CPU board |
||||
** ~~~~~~~~~~~ |
||||
** |
||||
**===================================================================== |
||||
** |
||||
** This program is free software; you can redistribute it and/or |
||||
** modify it under the terms of the GNU General Public License as |
||||
** published by the Free Software Foundation; either version 2 of |
||||
** the License, or (at your option) any later version. |
||||
** |
||||
** This program is distributed in the hope that it will be useful, |
||||
** but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
** GNU General Public License for more details. |
||||
** |
||||
** You should have received a copy of the GNU General Public License |
||||
** along with this program; if not, write to the Free Software |
||||
** Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
** MA 02111-1307 USA |
||||
** |
||||
**===================================================================== |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */ |
||||
#define CONFIG_MPC860T 1 |
||||
#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */ |
||||
#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
||||
|
||||
/* BOOT arguments */ |
||||
#define CONFIG_PREBOOT \ |
||||
"echo;" \
|
||||
"echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"rootargs=setenv rootpath /tftp/$(ipaddr)\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):eth0:off panic=1\0" \
|
||||
"ramboot=tftp 400000 /home/paugaml/pMulti;" \
|
||||
"run ramargs;bootm\0" \
|
||||
"nfsboot=tftp 400000 /home/paugaml/uImage;" \
|
||||
"run rootargs;run nfsargs;run addip;bootm\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND "run ramboot" |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */ |
||||
#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x00100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*
|
||||
* Environment Variables and Storages |
||||
*/ |
||||
#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */ |
||||
|
||||
#undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */ |
||||
#undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */ |
||||
|
||||
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CONFIG_ETHADDR 00:01:77:00:60:40 |
||||
#define CONFIG_IPADDR 192.168.0.30 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
|
||||
#define CONFIG_SERVERIP 192.168.0.1 |
||||
#define CONFIG_GATEWAYIP 192.168.0.1 |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x02000000 |
||||
#define CFG_NVRAM_BASE 0x03000000 |
||||
|
||||
#if defined(CFG_ENV_IS_IN_FLASH) |
||||
# if defined(DEBUG) |
||||
# define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */ |
||||
# else |
||||
# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
# endif |
||||
#else |
||||
# if defined(DEBUG) |
||||
# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
# else |
||||
# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
# endif |
||||
#endif |
||||
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#if defined(CFG_ENV_IS_IN_FLASH) |
||||
# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
||||
# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization |
||||
*/ |
||||
#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ |
||||
#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */ |
||||
/* 8 top NVRAM locations */ |
||||
|
||||
#if defined(CFG_ENV_IS_IN_NVRAM) |
||||
# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */ |
||||
# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP) |
||||
#else |
||||
# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC11) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
* Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC |
||||
* enabled |
||||
*/ |
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit - leave PLL multiplication factor unchanged ! |
||||
*/ |
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#define CFG_SCCR (SCCR_TBS | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#ifdef DEBUG |
||||
# define CFG_DER 0xFFE7400F /* Debug Enable Register */ |
||||
#else |
||||
# define CFG_DER 0 |
||||
#endif |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* ~~~~~~~~~~~~~~~~~~~~~~ |
||||
* |
||||
* BR0 and OR0 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */ |
||||
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */ |
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK) |
||||
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
/*
|
||||
* BR1 and OR1 (SDRAM) |
||||
* |
||||
*/ |
||||
#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */ |
||||
#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */ |
||||
|
||||
/* SDRAM timing: */ |
||||
#define CFG_OR_TIMING_SDRAM 0x00000000 |
||||
|
||||
#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM ) |
||||
#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
||||
|
||||
/*
|
||||
* BR2 and OR2 (NVRAM) |
||||
* |
||||
*/ |
||||
#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */ |
||||
#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */ |
||||
|
||||
#define CFG_OR2_PRELIM 0xFFF80160 |
||||
#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) |
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler |
||||
*/ |
||||
|
||||
/* periodic timer for refresh */ |
||||
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
|
||||
/* 8 column SDRAM */ |
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
/* 9 column SDRAM */ |
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Definitions |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
|
||||
/*
|
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,200 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* ARIO Data Networks, Inc. dchiu@ariodata.com |
||||
*
|
||||
* modified for DS164x: |
||||
* The LEOX team <team@leox.org>, http://www.leox.org
|
||||
* |
||||
* Based on MontaVista DS1743 code and U-Boot mc146818 code |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Date & Time support for the DS164x RTC |
||||
*/ |
||||
|
||||
/* #define RTC_DEBUG */ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <rtc.h> |
||||
|
||||
|
||||
#if defined(CONFIG_RTC_DS164x) && (CONFIG_COMMANDS & CFG_CMD_DATE) |
||||
|
||||
static uchar rtc_read(unsigned int addr ); |
||||
static void rtc_write(unsigned int addr, uchar val); |
||||
static uchar bin2bcd(unsigned int n); |
||||
static unsigned bcd2bin(uchar c); |
||||
|
||||
#define RTC_EPOCH 2000 /* century */ |
||||
|
||||
/*
|
||||
* DS164x registers layout |
||||
*/ |
||||
#define RTC_BASE ( CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE ) |
||||
|
||||
#define RTC_YEAR ( RTC_BASE + 0x07 ) |
||||
#define RTC_MONTH ( RTC_BASE + 0x06 ) |
||||
#define RTC_DAY_OF_MONTH ( RTC_BASE + 0x05 ) |
||||
#define RTC_DAY_OF_WEEK ( RTC_BASE + 0x04 ) |
||||
#define RTC_HOURS ( RTC_BASE + 0x03 ) |
||||
#define RTC_MINUTES ( RTC_BASE + 0x02 ) |
||||
#define RTC_SECONDS ( RTC_BASE + 0x01 ) |
||||
#define RTC_CONTROL ( RTC_BASE + 0x00 ) |
||||
|
||||
#define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */ |
||||
#define RTC_CA_WRITE 0x80 |
||||
#define RTC_CA_READ 0x40 |
||||
#define RTC_CONTROLB RTC_SECONDS /* OSC=bit7 */ |
||||
#define RTC_CB_OSC_DISABLE 0x80 |
||||
#define RTC_CONTROLC RTC_DAY_OF_WEEK /* FT=bit6 */ |
||||
#define RTC_CC_FREQ_TEST 0x40 |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
void rtc_get( struct rtc_time *tmp ) |
||||
{ |
||||
uchar sec, min, hour; |
||||
uchar mday, wday, mon, year; |
||||
|
||||
uchar reg_a; |
||||
|
||||
reg_a = rtc_read( RTC_CONTROLA ); |
||||
/* lock clock registers for read */ |
||||
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); |
||||
|
||||
sec = rtc_read( RTC_SECONDS ); |
||||
min = rtc_read( RTC_MINUTES ); |
||||
hour = rtc_read( RTC_HOURS ); |
||||
mday = rtc_read( RTC_DAY_OF_MONTH ); |
||||
wday = rtc_read( RTC_DAY_OF_WEEK ); |
||||
mon = rtc_read( RTC_MONTH ); |
||||
year = rtc_read( RTC_YEAR ); |
||||
|
||||
/* unlock clock registers after read */ |
||||
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); |
||||
|
||||
#ifdef RTC_DEBUG |
||||
printf( "Get RTC year: %02x mon: %02x mday: %02x wday: %02x " |
||||
"hr: %02x min: %02x sec: %02x\n", |
||||
year, mon, mday, wday, |
||||
hour, min, sec ); |
||||
#endif |
||||
tmp->tm_sec = bcd2bin( sec & 0x7F ); |
||||
tmp->tm_min = bcd2bin( min & 0x7F ); |
||||
tmp->tm_hour = bcd2bin( hour & 0x3F ); |
||||
tmp->tm_mday = bcd2bin( mday & 0x3F ); |
||||
tmp->tm_mon = bcd2bin( mon & 0x1F ); |
||||
tmp->tm_wday = bcd2bin( wday & 0x07 ); |
||||
|
||||
/* glue year in century (2000) */ |
||||
tmp->tm_year = bcd2bin( year ) + RTC_EPOCH; |
||||
|
||||
tmp->tm_yday = 0; |
||||
tmp->tm_isdst= 0; |
||||
#ifdef RTC_DEBUG |
||||
printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
||||
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
||||
tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); |
||||
#endif |
||||
} |
||||
|
||||
void rtc_set( struct rtc_time *tmp ) |
||||
{ |
||||
uchar reg_a; |
||||
|
||||
#ifdef RTC_DEBUG |
||||
printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
||||
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
||||
tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
||||
#endif |
||||
/* lock clock registers for write */ |
||||
reg_a = rtc_read( RTC_CONTROLA ); |
||||
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); |
||||
|
||||
rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); |
||||
|
||||
rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); |
||||
rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); |
||||
rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); |
||||
rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); |
||||
rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); |
||||
|
||||
/* break year in century */ |
||||
rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); |
||||
|
||||
/* unlock clock registers after read */ |
||||
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); |
||||
} |
||||
|
||||
void rtc_reset (void) |
||||
{ |
||||
uchar reg_a, reg_b; |
||||
|
||||
reg_a = rtc_read( RTC_CONTROLA ); |
||||
reg_b = rtc_read( RTC_CONTROLB ); |
||||
|
||||
if ( reg_b & RTC_CB_OSC_DISABLE ) |
||||
{ |
||||
printf( "real-time-clock was stopped. Now starting...\n" ); |
||||
reg_a |= RTC_CA_WRITE; |
||||
reg_b &= ~RTC_CB_OSC_DISABLE; |
||||
|
||||
rtc_write( RTC_CONTROLA, reg_a ); |
||||
rtc_write( RTC_CONTROLB, reg_b ); |
||||
} |
||||
|
||||
/* make sure read/write clock register bits are cleared */ |
||||
reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); |
||||
rtc_write( RTC_CONTROLA, reg_a ); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
static uchar rtc_read( unsigned int addr ) |
||||
{ |
||||
uchar val = *(volatile unsigned char*)(addr); |
||||
|
||||
#ifdef RTC_DEBUG |
||||
printf( "rtc_read: %x:%x\n", addr, val ); |
||||
#endif |
||||
return( val ); |
||||
} |
||||
|
||||
static void rtc_write( unsigned int addr, uchar val ) |
||||
{ |
||||
#ifdef RTC_DEBUG |
||||
printf( "rtc_write: %x:%x\n", addr, val ); |
||||
#endif |
||||
*(volatile unsigned char*)(addr) = val; |
||||
} |
||||
|
||||
static unsigned bcd2bin (uchar n) |
||||
{ |
||||
return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F)); |
||||
} |
||||
|
||||
static unsigned char bin2bcd (unsigned int n) |
||||
{ |
||||
return (((n / 10) << 4) | (n % 10)); |
||||
} |
||||
|
||||
#endif /* CONFIG_RTC_DS164x && CFG_CMD_DATE */ |
||||
Loading…
Reference in new issue