Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

sh: sh_eth: Add support SH7724

Browse Source 
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
master
Nobuhiro Iwamatsu 13 years ago committed by Nobuhiro Iwamatsu
parent e37ae40e9d
commit 3bb4cc312d
2 changed files with 60 additions and 23 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 42
      drivers/net/sh_eth.c
  2. 41
      drivers/net/sh_eth.h

42
drivers/net/sh_eth.c
Unescape View File

@ -1,8 +1,8 @@
/*
* sh_eth.c - Driver for Renesas SH7763's ethernet controler.
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (c) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
@ -371,7 +371,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(0, TFTR(port));
outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
outl(RMCR_RST, RMCR(port));
#ifndef CONFIG_CPU_SH7757
#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
outl(0, RPADIR(port));
#endif
outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
@ -393,16 +393,19 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(val, MALR(port));
outl(RFLR_RFL_MIN, RFLR(port));
#ifndef CONFIG_CPU_SH7757
#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
outl(0, PIPR(port));
#endif
#if !defined(CONFIG_CPU_SH7724)
outl(APR_AP, APR(port));
outl(MPR_MP, MPR(port));
#ifdef CONFIG_CPU_SH7757
outl(TPAUSER_UNLIMITED, TPAUSER(port));
#else
#endif
#if defined(CONFIG_CPU_SH7763)
outl(TPAUSER_TPAUSE, TPAUSER(port));
#elif defined(CONFIG_CPU_SH7757)
outl(TPAUSER_UNLIMITED, TPAUSER(port));
#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (ret) {
@ -412,33 +415,34 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
phy = port_info->phydev;
phy_startup(phy);
val = 0;
/* Set the transfer speed */
#ifdef CONFIG_CPU_SH7763
if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/");
#ifdef CONFIG_CPU_SH7763
outl(GECMR_100B, GECMR(port));
#elif defined(CONFIG_CPU_SH7757)
outl(1, RTRATE(port));
#elif defined(CONFIG_CPU_SH7724)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/");
#ifdef CONFIG_CPU_SH7763
outl(GECMR_10B, GECMR(port));
}
#endif
#if defined(CONFIG_CPU_SH7757)
if (phy->speed == 100) {
printf("100Base/");
outl(1, RTRATE(port));
} else if (phy->speed == 10) {
printf("10Base/");
#elif defined(CONFIG_CPU_SH7757)
outl(0, RTRATE(port));
}
#endif
}
/* Check if full duplex mode is supported by the phy */
if (phy->duplex) {
printf("Full\n");
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
} else {
printf("Half\n");
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
}
return ret;

41
drivers/net/sh_eth.h
Unescape View File

@ -1,8 +1,8 @@
/*
* sh_eth.h - Driver for Renesas SuperH ethernet controler.
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (c) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
@ -162,6 +162,32 @@ struct sh_eth_dev {
#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
#elif defined(CONFIG_CPU_SH7724)
#define BASE_IO_ADDR 0xA4600000
#define TDLAR(port) (BASE_IO_ADDR + 0x0018)
#define RDLAR(port) (BASE_IO_ADDR + 0x0020)
#define EDMR(port) (BASE_IO_ADDR + 0x0000)
#define EDTRR(port) (BASE_IO_ADDR + 0x0008)
#define EDRRR(port) (BASE_IO_ADDR + 0x0010)
#define EESR(port) (BASE_IO_ADDR + 0x0028)
#define EESIPR(port) (BASE_IO_ADDR + 0x0030)
#define TRSCER(port) (BASE_IO_ADDR + 0x0038)
#define TFTR(port) (BASE_IO_ADDR + 0x0048)
#define FDR(port) (BASE_IO_ADDR + 0x0050)
#define RMCR(port) (BASE_IO_ADDR + 0x0058)
#define FCFTR(port) (BASE_IO_ADDR + 0x0070)
#define ECMR(port) (BASE_IO_ADDR + 0x0100)
#define RFLR(port) (BASE_IO_ADDR + 0x0108)
#define ECSIPR(port) (BASE_IO_ADDR + 0x0118)
#define PIR(port) (BASE_IO_ADDR + 0x0120)
#define APR(port) (BASE_IO_ADDR + 0x0154)
#define MPR(port) (BASE_IO_ADDR + 0x0158)
#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
#define MALR(port) (BASE_IO_ADDR + 0x01c8)
#endif
/*
@ -183,7 +209,7 @@ enum DMAC_M_BIT {
EDMR_SRST = 0x03,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
#elif defined CONFIG_CPU_SH7757
#elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
EDMR_SRST = 0x01,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
@ -325,7 +351,8 @@ enum FCFTR_BIT {
/* Transfer descriptor bit */
enum TD_STS_BIT {
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757)
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
|| defined(CONFIG_CPU_SH7724)
TD_TACT = 0x80000000,
#else
TD_TACT = 0x7fffffff,
@ -350,6 +377,10 @@ enum FELIC_MODE_BIT {
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
#endif
};
#ifdef CONFIG_CPU_SH7763
@ -357,6 +388,8 @@ enum FELIC_MODE_BIT {
ECMR_TXF | ECMR_MCT)
#elif CONFIG_CPU_SH7757
#define ECMR_CHG_DM (ECMR_ZPF)
#elif CONFIG_CPU_SH7724
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
#endif

Write Preview
Loading…
Cancel
Save