Add support for VoiceBlue board. * Patch by Ladislav Michl, 05 Apr 2005: Fix netboot_common() prototypes. * Cleanup.master
wdenk
20 years ago
parent
b304c96871
commit
3c2b3d454d
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# (C) Copyright 2000-2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de
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#
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# (C) Copyright 2005
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# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License version 2 as
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# published by the Free Software Foundation.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := voiceblue.o
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SOBJS := setup.o
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gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
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LOAD_ADDR = 0x10400000
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all: $(LIB) eeprom.srec eeprom.bin |
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS) $(SOBJS)
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eeprom.srec: eeprom.o |
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$(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ \
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-L../../examples -lstubs \
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-L../../lib_generic -lgeneric \
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-L$(gcclibdir) -lgcc
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$(OBJCOPY) -O srec $(<:.o=) $@
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eeprom.bin: eeprom.srec |
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$(OBJCOPY) -O binary $< $@ 2>/dev/null
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clean: |
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rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin
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distclean: clean |
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rm -f $(LIB) core config.tmp *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,16 @@ |
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#
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# Linux-Kernel is expected to be at 1000'8000,
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# entry 1000'8000 (mem base + reserved)
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#
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sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp |
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ifeq ($(VOICEBLUE_SMALL_FLASH),y) |
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# We load ourself to internal SRAM at 2001'2000
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# Check map file when changing TEXT_BASE.
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# Everything has fit into 192kB internal SRAM!
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TEXT_BASE = 0x20012000
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else |
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# Running in SDRAM...
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TEXT_BASE = 0x13000000
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endif |
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@ -0,0 +1,140 @@ |
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/*
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* (C) Copyright 2005 |
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* Ladislav Michl, 2N Telekomunikace, michl@2n.cz |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Some code shamelessly stolen back from Robin Getz. |
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*/ |
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#define DEBUG |
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#include <common.h> |
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#include <exports.h> |
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#include "../drivers/smc91111.h" |
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#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE |
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static int verify_macaddr(char *); |
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static int set_mac(char *); |
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int eeprom(int argc, char *argv[]) |
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{ |
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app_startup(argv); |
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if (get_version() != XF_VERSION) { |
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printf("Wrong XF_VERSION.\n"); |
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printf("Application expects ABI version %d\n", XF_VERSION); |
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printf("Actual U-Boot ABI version %d\n", (int)get_version()); |
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return 1; |
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} |
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if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { |
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printf("SMSC91111 not found.\n"); |
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return 2; |
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} |
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if (argc != 2) { |
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printf("VoiceBlue EEPROM writer\n"); |
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printf("Built: %s at %s\n", __DATE__ , __TIME__ ); |
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printf("Usage:\n\t<mac_address>"); |
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return 3; |
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} |
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set_mac(argv[1]); |
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if (verify_macaddr(argv[1])) { |
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printf("*** ERROR ***\n"); |
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return 4; |
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} |
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return 0; |
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} |
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static u16 read_eeprom_reg(u16 reg) |
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{ |
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int timeout; |
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SMC_SELECT_BANK(2); |
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SMC_outw(reg, PTR_REG); |
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SMC_SELECT_BANK(1); |
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SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, |
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CTL_REG); |
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timeout = 100; |
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while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) |
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udelay(100); |
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if (timeout == 0) { |
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printf("Timeout Reading EEPROM register %02x\n", reg); |
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return 0; |
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} |
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return SMC_inw (GP_REG); |
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} |
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static int write_eeprom_reg(u16 value, u16 reg) |
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{ |
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int timeout; |
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SMC_SELECT_BANK(2); |
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SMC_outw(reg, PTR_REG); |
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SMC_SELECT_BANK(1); |
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SMC_outw(value, GP_REG); |
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SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); |
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timeout = 100; |
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while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) |
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udelay (100); |
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if (timeout == 0) { |
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printf("Timeout Writing EEPROM register %02x\n", reg); |
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return 0; |
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} |
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return 1; |
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} |
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static int verify_macaddr(char *s) |
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{ |
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u16 reg; |
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int i, err = 0; |
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printf("Verifying MAC Address: "); |
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err = i = 0; |
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for (i = 0; i < 3; i++) { |
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reg = read_eeprom_reg(0x20 + i); |
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printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); |
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err |= reg != ((u16 *)s)[i]; |
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} |
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return err ? 0 : 1; |
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} |
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static int set_mac(char *s) |
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{ |
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int i; |
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char *e, eaddr[6]; |
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/* turn string into mac value */ |
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for (i = 0; i < 6; i++) { |
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eaddr[i] = simple_strtoul(s, &e, 16); |
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s = (*e) ? e+1 : e; |
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} |
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for (i = 0; i < 3; i++) |
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write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); |
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return 0; |
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} |
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@ -0,0 +1,280 @@ |
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/* |
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* Board specific setup info |
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* |
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* (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
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* (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License |
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* version 2 published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <version.h> |
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_TEXT_BASE: |
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.word TEXT_BASE /* SDRAM load addr from config.mk */ |
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OMAP5910_LPG1_BASE: .word 0xfffbd000 |
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OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 |
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OMAP5910_MPU_TC_BASE: .word 0xfffecc00 |
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OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 |
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OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 |
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OMAP5910_DPLL1_BASE: .word 0xfffecf00 |
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OMAP5910_GPIO_BASE: .word 0xfffce000 |
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OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 |
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OMAP5910_MPUI_BASE: .word 0xfffec900 |
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_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL |
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_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK |
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OMAP5910_MPUI_CTRL: .word 0x0000ff1b |
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VAL_EMIFS_CS0_CONFIG: .word 0x00009090 |
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VAL_EMIFS_CS1_CONFIG: .word 0x00003031 |
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VAL_EMIFS_CS2_CONFIG: .word 0x00003031 |
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VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 |
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VAL_EMIFS_DYN_WAIT: .word 0x00000000 |
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/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ |
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/* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ |
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VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) |
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VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 |
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VAL_EMIFF_MRS: .word 0x00000037 |
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/* |
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* GPIO04 - D4 (Onboard LED) |
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* GPIO07 - LAN91C111 reset |
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*/ |
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GPIO_DIRECTION: |
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.word 0x0000ff6f
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/* |
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* Disable everything, but D4 LED (connected through invertor) |
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*/ |
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GPIO_OUTPUT: |
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.word 0x00000010
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MUX_CONFIG_BASE: |
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.word 0xfffe1000
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MUX_CONFIG_VALUES: |
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.align 4
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.word 0x00000000 @ FUNC_MUX_CTRL_0
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.word 0x00000000 @ FUNC_MUX_CTRL_1
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.word 0x00000000 @ FUNC_MUX_CTRL_2
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.word 0x00000000 @ FUNC_MUX_CTRL_3
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.word 0x00000000 @ FUNC_MUX_CTRL_4
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.word 0x12082480 @ FUNC_MUX_CTRL_5
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.word 0x00000004 @ FUNC_MUX_CTRL_6
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.word 0x00000003 @ FUNC_MUX_CTRL_7
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.word 0x10001200 @ FUNC_MUX_CTRL_8
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.word 0x01201012 @ FUNC_MUX_CTRL_9
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.word 0x02081248 @ FUNC_MUX_CTRL_A
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.word 0x00001248 @ FUNC_MUX_CTRL_B
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.word 0x12240000 @ FUNC_MUX_CTRL_C
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.word 0x00002000 @ FUNC_MUX_CTRL_D
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.word 0x00000000 @ PULL_DWN_CTRL_0
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.word 0x0000085f @ PULL_DWN_CTRL_1
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.word 0x01001000 @ PULL_DWN_CTRL_2
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.word 0x00000000 @ PULL_DWN_CTRL_3
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.word 0x00000000 @ GATE_INH_CTRL_0
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.word 0x00000000 @ VOLTAGE_CTRL_0
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.word 0x00000000 @ TEST_DBG_CTRL_0
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.word 0x00000006 @ MOD_CONF_CTRL_0
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.word 0x0000eaef @ COMP_MODE_CTRL_0
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MUX_CONFIG_OFFSETS: |
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.align 1
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.byte 0x00 @ FUNC_MUX_CTRL_0
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.byte 0x04 @ FUNC_MUX_CTRL_1
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.byte 0x08 @ FUNC_MUX_CTRL_2
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.byte 0x10 @ FUNC_MUX_CTRL_3
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.byte 0x14 @ FUNC_MUX_CTRL_4
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.byte 0x18 @ FUNC_MUX_CTRL_5
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.byte 0x1c @ FUNC_MUX_CTRL_6
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.byte 0x20 @ FUNC_MUX_CTRL_7
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.byte 0x24 @ FUNC_MUX_CTRL_8
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.byte 0x28 @ FUNC_MUX_CTRL_9
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.byte 0x2c @ FUNC_MUX_CTRL_A
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.byte 0x30 @ FUNC_MUX_CTRL_B
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.byte 0x34 @ FUNC_MUX_CTRL_C
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.byte 0x38 @ FUNC_MUX_CTRL_D
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.byte 0x40 @ PULL_DWN_CTRL_0
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.byte 0x44 @ PULL_DWN_CTRL_1
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.byte 0x48 @ PULL_DWN_CTRL_2
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.byte 0x4c @ PULL_DWN_CTRL_3
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.byte 0x50 @ GATE_INH_CTRL_0
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.byte 0x60 @ VOLTAGE_CTRL_0
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.byte 0x70 @ TEST_DBG_CTRL_0
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.byte 0x80 @ MOD_CONF_CTRL_0
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.byte 0x0c @ COMP_MODE_CTRL_0
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.byte 0xff
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.globl platformsetup
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platformsetup: |
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/* Improve performance a bit... */ |
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mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
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mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
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mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
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orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
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mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
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mov r1, #0x00 |
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mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
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nop |
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nop |
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nop |
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nop |
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/* Setup clocking mode */ |
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ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
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ldrh r1, [r0, #0x18] @ get reset status
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bic r1, r1, #(7 << 11) @ clear clock select
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orr r1, r1, #(2 << 11) @ set synchronous scalable
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mov r2, #0 @ set wait counter to 100 clock cycles
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icache_loop: |
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cmp r2, #0x01 |
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streqh r1, [r0, #0x18] |
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add r2, r2, #0x01 |
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cmp r2, #0x10 |
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bne icache_loop |
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nop |
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/* Setup clock divisors */ |
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ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
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ldr r1, _OMAP5910_ARM_CKCTL |
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orr r1, r1, #0x2000 @ enable DSP clock
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strh r1, [r0, #0x00] @ setup clock divisors
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/* Setup DPLL to generate requested freq */ |
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ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
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mov r1, #0x0010 @ set PLL_ENABLE
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orr r1, r1, #0x2000 @ set IOB to new locking
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orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
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orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
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strh r1, [r0] @ write
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locking: |
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ldrh r1, [r0] @ get DPLL value
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tst r1, #0x01 |
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beq locking @ while LOCK not set
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/* Enable clock */ |
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ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
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mov r1, #(1 << 10) @ disable idle mode do not check
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@ nWAKEUP pin, other remain active
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strh r1, [r0, #0x04] |
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ldr r1, _OMAP5910_ARM_EN_CLK |
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strh r1, [r0, #0x08] |
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mov r1, #0x003f @ FLASH.RP not enabled in idle and
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@ max delayed ( 32 x CLKIN )
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strh r1, [r0, #0x0c] |
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/* Configure 5910 pins functions to match our board. */ |
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ldr r0, MUX_CONFIG_BASE |
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adr r1, MUX_CONFIG_VALUES |
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adr r2, MUX_CONFIG_OFFSETS |
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next_mux_cfg: |
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ldrb r3, [r2], #1 |
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ldr r4, [r1], #4 |
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cmp r3, #0xff |
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strne r4, [r0, r3] |
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bne next_mux_cfg |
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/* Configure GPIO pins (also enables onboard LED) */ |
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ldr r0, OMAP5910_GPIO_BASE |
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ldr r1, GPIO_OUTPUT |
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strh r1, [r0, #0x04] |
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ldr r1, GPIO_DIRECTION |
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strh r1, [r0, #0x08] |
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/* EnablePeripherals */ |
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ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit
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mov r1, #0x0001 @ Peripheral enable
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strh r1, [r0, #0x14] |
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/* Program LED Pulse Generator */ |
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ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator
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mov r1, #0x7F @ Set obscure frequency in
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strb r1, [r0, #0x00] @ LCR
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mov r1, #0x01 @ Enable clock (CLK_EN) in
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strb r1, [r0, #0x04] @ PMR
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/* TIPB Lock UART1 */ |
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ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
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mov r1, #1 @ ARM allocated
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strh r1, [r0,#0x04] @ clear IRQ line and status bits
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strh r1, [r0,#0x00] |
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ldrh r1, [r0,#0x04] |
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/* Disable watchdog */ |
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ldr r0, OMAP5910_MPU_WD_TIMER_BASE |
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mov r1, #0xf5 |
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strh r1, [r0, #0x8] |
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mov r1, #0xa0 |
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strh r1, [r0, #0x8] |
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/* Enable MCLK */ |
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ldr r0, OMAP5910_ULPD_PWR_MNG_BASE |
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mov r1, #0x6 |
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strh r1, [r0, #0x34] |
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strh r1, [r0, #0x34] |
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/* Setup clock divisors */ |
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ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
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mov r1, #0x0010 @ set PLL_ENABLE
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orr r1, r1, #0x2000 @ set IOB to new locking
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strh r1, [r0] @ write
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ulocking: |
||||
ldrh r1, [r0] @ get DPLL value
|
||||
tst r1, #1 |
||||
beq ulocking @ while LOCK not set
|
||||
|
||||
/* EMIF init */ |
||||
ldr r0, OMAP5910_MPU_TC_BASE |
||||
ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG
|
||||
bic r1, r1, #0x0c @ pwr down disabled, flash WP
|
||||
orr r1, r1, #0x01 |
||||
str r1, [r0, #0x0c] |
||||
|
||||
ldr r1, VAL_EMIFS_CS0_CONFIG |
||||
str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
|
||||
ldr r1, VAL_EMIFS_CS1_CONFIG |
||||
str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG
|
||||
ldr r1, VAL_EMIFS_CS2_CONFIG |
||||
str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG
|
||||
ldr r1, VAL_EMIFS_CS3_CONFIG |
||||
str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG
|
||||
ldr r1, VAL_EMIFS_DYN_WAIT |
||||
str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT
|
||||
|
||||
/* Setup SDRAM */ |
||||
ldr r1, VAL_EMIFF_SDRAM_CONFIG |
||||
str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG
|
||||
ldr r1, VAL_EMIFF_SDRAM_CONFIG2 |
||||
str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2
|
||||
ldr r1, VAL_EMIFF_MRS |
||||
str r1, [r0, #0x24] @ EMIFF_MRS
|
||||
/* SDRAM needs 100us to stabilize */ |
||||
mov r0, #0x4000 |
||||
sdelay: |
||||
subs r0, r0, #0x1 |
||||
bne sdelay |
||||
|
||||
/* back to arch calling code */ |
||||
mov pc, lr |
||||
.end |
||||
@ -0,0 +1,55 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/arm925t/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
.bss : { *(.bss) } |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,152 @@ |
||||
/*
|
||||
* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License |
||||
* version 2 as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
int board_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
unsigned int val; |
||||
|
||||
*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa; |
||||
|
||||
/* arch number of VoiceBlue board */ |
||||
/* TODO: use define from asm/mach-types.h */ |
||||
gd->bd->bi_arch_number = 218; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x10000100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff; |
||||
|
||||
/* Take the Ethernet controller out of reset and wait
|
||||
* for the EEPROM load to complete. */ |
||||
*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; |
||||
udelay(10); /* doesn't work before interrupt_init call */ |
||||
*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; |
||||
udelay(500); |
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifndef VOICEBLUE_SMALL_FLASH |
||||
|
||||
#include <jffs2/jffs2.h> |
||||
|
||||
extern flash_info_t flash_info[]; |
||||
static struct part_info partinfo; |
||||
static int current_part = -1; |
||||
|
||||
/* Partition table (Linux MTD see it this way)
|
||||
* |
||||
* 0 - U-Boot |
||||
* 1 - env |
||||
* 2 - redundant env |
||||
* 3 - data1 (jffs2) |
||||
* 4 - data2 (jffs2) |
||||
*/ |
||||
|
||||
static struct { |
||||
ulong offset; |
||||
ulong size; |
||||
} part[5]; |
||||
|
||||
static void partition_flash(flash_info_t *info) |
||||
{ |
||||
char mtdparts[128]; |
||||
int i, n, size, psize; |
||||
const ulong plen[3] = { CFG_MONITOR_LEN, CFG_ENV_SIZE, CFG_ENV_SIZE }; |
||||
|
||||
size = n = 0; |
||||
for (i = 0; i < 4; i++) { |
||||
part[i].offset = info->start[n]; |
||||
psize = i < 3 ? plen[i] : (info->size - size) / 2; |
||||
while (part[i].size < psize) { |
||||
if (++n > info->sector_count) { |
||||
printf("Partitioning error. System halted.\n"); |
||||
while (1) ; |
||||
} |
||||
part[i].size += info->start[n] - info->start[n - 1]; |
||||
} |
||||
size += part[i].size; |
||||
} |
||||
part[4].offset = info->start[n]; |
||||
part[4].size = info->start[info->sector_count - 1] - info->start[n]; |
||||
|
||||
sprintf(mtdparts, "omapflash.0:" |
||||
"%dk(U-Boot)ro,%dk(env),%dk(r_env),%dk(data1),-(data2)", |
||||
part[0].size >> 10, part[1].size >> 10, |
||||
part[2].size >> 10, part[3].size >> 10); |
||||
setenv ("mtdparts", mtdparts); |
||||
} |
||||
|
||||
struct part_info* jffs2_part_info(int part_num) |
||||
{ |
||||
void *jffs2_priv_saved = partinfo.jffs2_priv; |
||||
|
||||
if (part_num != 3 && part_num != 4) |
||||
return NULL; |
||||
|
||||
if (current_part != part_num) { |
||||
memset(&partinfo, 0, sizeof(partinfo)); |
||||
current_part = part_num; |
||||
partinfo.offset = (char*) part[part_num].offset; |
||||
partinfo.size = part[part_num].size; |
||||
partinfo.usr_priv = ¤t_part; |
||||
partinfo.jffs2_priv = jffs2_priv_saved; |
||||
} |
||||
|
||||
return &partinfo; |
||||
} |
||||
|
||||
#endif |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
*((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55; |
||||
|
||||
#ifndef VOICEBLUE_SMALL_FLASH |
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf("Unknown flash. System halted.\n"); |
||||
while (1) ; |
||||
} |
||||
partition_flash(&flash_info[0]); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
*((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00; |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,253 @@ |
||||
/*
|
||||
* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl |
||||
* |
||||
* Configuation settings for the TI OMAP VoiceBlue board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License |
||||
* version 2 as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <configs/omap1510.h> |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP1510 1 /* which is in a 5910 */ |
||||
|
||||
/* Input clock of PLL */ |
||||
#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */ |
||||
#define CONFIG_XTAL_FREQ 12000000 |
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
|
||||
#define CONFIG_MISC_INIT_R /* There is nothing to really init */ |
||||
#define BOARD_LATE_INIT /* but we flash the LEDs here */ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
/*
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE SZ_64M |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_2 0x0c000000 |
||||
|
||||
#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ |
||||
|
||||
/*
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_FLASH_CFI /* Flash is CFI conformant */ |
||||
#define CFG_FLASH_CFI_DRIVER /* Use the common driver */ |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
#ifdef VOICEBLUE_SMALL_FLASH |
||||
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 } |
||||
#else |
||||
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } |
||||
#endif |
||||
|
||||
/* FIXME: Does not work on AMD flash */ |
||||
/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */ |
||||
#define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */ |
||||
|
||||
#define CFG_MONITOR_BASE PHYS_FLASH_1 |
||||
#define CFG_MONITOR_LEN SZ_128K |
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#ifdef VOICEBLUE_SMALL_FLASH |
||||
#define CFG_ENV_IS_NOWHERE |
||||
#define CFG_ENV_SIZE SZ_1K |
||||
#else |
||||
#define CFG_ENV_IS_IN_FLASH |
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) |
||||
#define CFG_ENV_SIZE SZ_8K |
||||
#define CFG_ENV_SECT_SIZE SZ_64K |
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CFG_JFFS_CUSTOM_PART /* see board/voiceblue/jffs2parts.c */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#ifdef VOICEBLUE_SMALL_FLASH |
||||
#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE) |
||||
#else |
||||
#define CFG_MALLOC_LEN (SZ_4M - CFG_GBL_DATA_SIZE) |
||||
#endif |
||||
|
||||
/*
|
||||
* The stack size is set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE SZ_8K /* regular stack */ |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_DRIVER_SMC91111 |
||||
#define CONFIG_SMC91111_BASE 0x08000300 |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE (-4) |
||||
#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ |
||||
#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ |
||||
|
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#ifdef VOICEBLUE_SMALL_FLASH |
||||
#define CONFIG_COMMANDS (CFG_CMD_BDI | \ |
||||
CFG_CMD_LOADB | \
|
||||
CFG_CMD_IMI | \
|
||||
CFG_CMD_FLASH | \
|
||||
CFG_CMD_MEMORY | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_BOOTD | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_RUN) |
||||
#else |
||||
#define CONFIG_COMMANDS (CFG_CMD_BDI | \ |
||||
CFG_CMD_LOADB | \
|
||||
CFG_CMD_IMI | \
|
||||
CFG_CMD_FLASH | \
|
||||
CFG_CMD_MEMORY | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_ENV | \
|
||||
CFG_CMD_BOOTD | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_RUN | \
|
||||
CFG_CMD_JFFS2) |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT |
||||
#define CONFIG_LOOPW |
||||
|
||||
#ifdef VOICEBLUE_SMALL_FLASH |
||||
#define CONFIG_BOOTDELAY 0 |
||||
#undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/ |
||||
#define CFG_AUTOLOAD "n" /* No autoload */ |
||||
#define CONFIG_PREBOOT "run setup" |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"setup=setenv bootargs console=ttyS0,$(baudrate) " \
|
||||
"root=/dev/nfs ip=dhcp\0" \
|
||||
"update=erase c000000 c03ffff; " \
|
||||
"cp.b 10400000 c000000 $(filesize)\0" |
||||
#else |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
||||
#define CFG_AUTOLOAD "n" /* No autoload */ |
||||
#define CONFIG_BOOTCOMMAND "run nboot" |
||||
#define CONFIG_PREBOOT "run setup" |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"ospart=0\0" \
|
||||
"swapos=no\0" \
|
||||
"setpart=" \
|
||||
"if test $swapos = yes; then " \
|
||||
"if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\
|
||||
"setenv swapos no; saveenv; " \
|
||||
"else " \
|
||||
"if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\
|
||||
"fi\0" \
|
||||
"setup=setenv bootargs console=ttyS0,$baudrate " \
|
||||
"mtdparts=$mtdparts\0" \
|
||||
"nfsargs=setenv bootargs $bootargs " \
|
||||
"root=/dev/nfs ip=dhcp; run setpart\0" \
|
||||
"flashargs=setenv bootargs $bootargs " \
|
||||
"root=/dev/mtdblock$partition " \
|
||||
"rootfstype=jffs2; run setpart\0" \
|
||||
"nboot=run nfsargs; bootp; tftp; bootm\0" \
|
||||
"fboot=run flashargs; fsload /boot/uImage; bootm\0" |
||||
#endif |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#ifndef VOICEBLUE_SMALL_FLASH |
||||
#define CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#endif |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "# " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM_1 |
||||
#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
|
||||
/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
|
||||
* This time is further subdivided by a local divisor. |
||||
*/ |
||||
#define CFG_TIMERBASE OMAP1510_TIMER1_BASE |
||||
#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ |
||||
#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) |
||||
|
||||
#define OMAP5910_DPLL_DIV 1 |
||||
#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ |
||||
(1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ) |
||||
|
||||
#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */ |
||||
#define OMAP5910_LCD_DIV 2 /* CKL/4 */ |
||||
#define OMAP5910_ARM_DIV 0 /* CKL/1 */ |
||||
#define OMAP5910_DSP_DIV 0 /* CKL/1 */ |
||||
#define OMAP5910_TC_DIV 1 /* CKL/2 */ |
||||
#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */ |
||||
#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */ |
||||
|
||||
#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */ |
||||
#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \ |
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(OMAP5910_LCD_DIV << 2) | \
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(OMAP5910_ARM_DIV << 4) | \
|
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(OMAP5910_DSP_DIV << 6) | \
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(OMAP5910_TC_DIV << 8) | \
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(OMAP5910_DSP_MMU_DIV << 10) | \
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(OMAP5910_ARM_TIM_SEL << 12)) |
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|
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#define VOICEBLUE_LED_REG 0x04030000 |
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|
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#endif /* __CONFIG_H */ |
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Reference in new issue