Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

driver/ddr/altera: Add the sdram calibration portion

Browse Source 
This patch adds the DDR calibration portion of the Altera SDRAM driver.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
master
Dinh Nguyen 10 years ago committed by Marek Vasut
parent 9bbd2132e3
commit 3da428595e
7 changed files with 4985 additions and 0 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 11
      drivers/ddr/altera/Makefile
  2. 4051
      drivers/ddr/altera/sequencer.c
  3. 322
      drivers/ddr/altera/sequencer.h
  4. 128
      drivers/ddr/altera/sequencer_auto.h
  5. 84
      drivers/ddr/altera/sequencer_auto_ac_init.h
  6. 268
      drivers/ddr/altera/sequencer_auto_inst_init.h
  7. 121
      drivers/ddr/altera/sequencer_defines.h

11
drivers/ddr/altera/Makefile
Unescape View File

@ -0,0 +1,11 @@
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
# Copyright (C) 2014 Altera Corporation <www.altera.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o

4051
drivers/ddr/altera/sequencer.c
View File

File diff suppressed because it is too large Load Diff

322
drivers/ddr/altera/sequencer.h
Unescape View File

@ -0,0 +1,322 @@
/*
* Copyright Altera Corporation (C) 2012-2015
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _SEQUENCER_H_
#define _SEQUENCER_H_
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
#define RW_MGR_RUN_SINGLE_GROUP (BASE_RW_MGR)
#define RW_MGR_RUN_ALL_GROUPS (BASE_RW_MGR + 0x0400)
#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020)
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
#define NUM_SHADOW_REGS 1
#define RW_MGR_RESET_READ_DATAPATH (BASE_RW_MGR + 0x1000)
#define RW_MGR_SET_CS_AND_ODT_MASK (BASE_RW_MGR + 0x1400)
#define RW_MGR_RANK_NONE 0xFF
#define RW_MGR_RANK_ALL 0x00
#define RW_MGR_ODT_MODE_OFF 0
#define RW_MGR_ODT_MODE_READ_WRITE 1
#define NUM_CALIB_REPEAT 1
#define NUM_READ_TESTS 7
#define NUM_READ_PB_TESTS 7
#define NUM_WRITE_TESTS 15
#define NUM_WRITE_PB_TESTS 31
#define PASS_ALL_BITS 1
#define PASS_ONE_BIT 0
/* calibration stages */
#define CAL_STAGE_NIL 0
#define CAL_STAGE_VFIFO 1
#define CAL_STAGE_WLEVEL 2
#define CAL_STAGE_LFIFO 3
#define CAL_STAGE_WRITES 4
#define CAL_STAGE_FULLTEST 5
#define CAL_STAGE_REFRESH 6
#define CAL_STAGE_CAL_SKIPPED 7
#define CAL_STAGE_CAL_ABORTED 8
#define CAL_STAGE_VFIFO_AFTER_WRITES 9
/* calibration substages */
#define CAL_SUBSTAGE_NIL 0
#define CAL_SUBSTAGE_GUARANTEED_READ 1
#define CAL_SUBSTAGE_DQS_EN_PHASE 2
#define CAL_SUBSTAGE_VFIFO_CENTER 3
#define CAL_SUBSTAGE_WORKING_DELAY 1
#define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
#define CAL_SUBSTAGE_WLEVEL_COPY 3
#define CAL_SUBSTAGE_WRITES_CENTER 1
#define CAL_SUBSTAGE_READ_LATENCY 1
#define CAL_SUBSTAGE_REFRESH 1
#define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS)
#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \
RW_MGR_MEM_IF_READ_DQS_WIDTH ? \
RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \
RW_MGR_MEM_IF_READ_DQS_WIDTH)
#define MAX_DQ (RW_MGR_MEM_DATA_WIDTH)
#define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH)
/* length of VFIFO, from SW_MACROS */
#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
/* MarkW: how should these base addresses be done for A-V? */
#define BASE_PTR_MGR 0x00040000
#define BASE_SCC_MGR 0x00058000
#define BASE_REG_FILE 0x00070000
#define BASE_TIMER 0x00078000
#define BASE_PHY_MGR 0x00088000
#define BASE_RW_MGR 0x00090000
#define BASE_DATA_MGR 0x00098000
#define BASE_MMR 0x000C0000
#define BASE_TRK_MGR 0x000D0000
#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000)
#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100)
#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200)
#define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300)
#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400)
#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500)
#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700)
#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
/* HHP-HPS-specific versions of some commands */
#define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600)
#define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800)
#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00)
#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00)
#define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00)
#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000
#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000
#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
#define PHY_MGR_CAL_RESET (0)
#define PHY_MGR_CAL_SUCCESS (1)
#define PHY_MGR_CAL_FAIL (2)
#define CALIB_SKIP_DELAY_LOOPS (1 << 0)
#define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
#define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
#define CALIB_SKIP_VFIFO (1 << 3)
#define CALIB_SKIP_LFIFO (1 << 4)
#define CALIB_SKIP_WLEVEL (1 << 5)
#define CALIB_SKIP_WRITES (1 << 6)
#define CALIB_SKIP_FULL_TEST (1 << 7)
#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
#define CALIB_IN_RTL_SIM (1 << 8)
/* Scan chain manager command addresses */
#define READ_SCC_OCT_OUT2_DELAY 0
#define READ_SCC_DQ_OUT2_DELAY 0
#define READ_SCC_DQS_IO_OUT2_DELAY 0
#define READ_SCC_DM_IO_OUT2_DELAY 0
/* HHP-HPS-specific values */
#define SCC_MGR_HHP_EXTRAS_OFFSET 0
#define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
/* PHY Debug mode flag constants */
#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
/* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
* otherwise, revert to defaults
* Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 =
* 200.75us @ 266MHz
*/
#ifdef TINIT_CNTR0_VAL
#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
#else
#define SEQ_TINIT_CNTR0_VAL 0
#endif
#ifdef TINIT_CNTR1_VAL
#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
#else
#define SEQ_TINIT_CNTR1_VAL 202
#endif
#ifdef TINIT_CNTR2_VAL
#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
#else
#define SEQ_TINIT_CNTR2_VAL 131
#endif
/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 =
* 500.86us @ 266MHz
*/
#ifdef TRESET_CNTR0_VAL
#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
#else
#define SEQ_TRESET_CNTR0_VAL 2
#endif
#ifdef TRESET_CNTR1_VAL
#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
#else
#define SEQ_TRESET_CNTR1_VAL 252
#endif
#ifdef TRESET_CNTR2_VAL
#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
#else
#define SEQ_TRESET_CNTR2_VAL 131
#endif
#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
struct socfpga_sdr_rw_load_manager {
u32 load_cntr0;
u32 load_cntr1;
u32 load_cntr2;
u32 load_cntr3;
};
struct socfpga_sdr_rw_load_jump_manager {
u32 load_jump_add0;
u32 load_jump_add1;
u32 load_jump_add2;
u32 load_jump_add3;
};
struct socfpga_sdr_reg_file {
u32 signature;
u32 debug_data_addr;
u32 cur_stage;
u32 fom;
u32 failing_stage;
u32 debug1;
u32 debug2;
u32 dtaps_per_ptap;
u32 trk_sample_count;
u32 trk_longidle;
u32 delays;
u32 trk_rw_mgr_addr;
u32 trk_read_dqs_width;
u32 trk_rfsh;
};
/* parameter variable holder */
struct param_type {
uint32_t dm_correct_mask;
uint32_t read_correct_mask;
uint32_t read_correct_mask_vg;
uint32_t write_correct_mask;
uint32_t write_correct_mask_vg;
/* set a particular entry to 1 if we need to skip a particular rank */
uint32_t skip_ranks[MAX_RANKS];
/* set a particular entry to 1 if we need to skip a particular group */
uint32_t skip_groups;
/* set a particular entry to 1 if the shadow register
(which represents a set of ranks) needs to be skipped */
uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
};
/* global variable holder */
struct gbl_type {
uint32_t phy_debug_mode_flags;
/* current read latency */
uint32_t curr_read_lat;
/* current write latency */
uint32_t curr_write_lat;
/* error code */
uint32_t error_substage;
uint32_t error_stage;
uint32_t error_group;
/* figure-of-merit in, figure-of-merit out */
uint32_t fom_in;
uint32_t fom_out;
/*USER Number of RW Mgr NOP cycles between
write command and write data */
uint32_t rw_wl_nop_cycles;
};
struct socfpga_sdr_scc_mgr {
u32 dqs_ena;
u32 dqs_io_ena;
u32 dq_ena;
u32 dm_ena;
u32 __padding1[4];
u32 update;
u32 __padding2[7];
u32 active_rank;
};
/* PHY manager configuration registers. */
struct socfpga_phy_mgr_cfg {
u32 phy_rlat;
u32 reset_mem_stbl;
u32 mux_sel;
u32 cal_status;
u32 cal_debug_info;
u32 vfifo_rd_en_ovrd;
u32 afi_wlat;
u32 afi_rlat;
};
/* PHY manager command addresses. */
struct socfpga_phy_mgr_cmd {
u32 inc_vfifo_fr;
u32 inc_vfifo_hard_phy;
u32 fifo_reset;
u32 inc_vfifo_fr_hr;
u32 inc_vfifo_qr;
};
struct socfpga_data_mgr {
u32 __padding1;
u32 t_wl_add;
u32 mem_t_add;
u32 t_rl_add;
};
#endif /* _SEQUENCER_H_ */

128
drivers/ddr/altera/sequencer_auto.h
Unescape View File

@ -0,0 +1,128 @@
/*
* Copyright Altera Corporation (C) 2012-2015
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define RW_MGR_READ_B2B_WAIT2 0x6A
#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
#define RW_MGR_REFRESH_ALL 0x14
#define RW_MGR_ZQCL 0x06
#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
#define RW_MGR_ACTIVATE_0_AND_1 0x0D
#define RW_MGR_MRS2_MIRR 0x0A
#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
#define RW_MGR_ACTIVATE_1 0x0F
#define RW_MGR_MRS2 0x04
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
#define RW_MGR_MRS1 0x03
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_IDLE_LOOP1 0x7A
#else
#define RW_MGR_IDLE_LOOP1 0x7C
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
#define RW_MGR_MRS3 0x05
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_IDLE_LOOP2 0x79
#else
#define RW_MGR_IDLE_LOOP2 0x7B
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_RDIMM_CMD 0x78
#else
#define RW_MGR_RDIMM_CMD 0x7A
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
#define RW_MGR_GUARANTEED_READ_CONT 0x53
#define RW_MGR_MRS3_MIRR 0x0B
#define RW_MGR_IDLE 0x00
#define RW_MGR_READ_B2B 0x58
#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
#define RW_MGR_GUARANTEED_WRITE 0x17
#define RW_MGR_PRECHARGE_ALL 0x12
#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define RW_MGR_SGLE_READ 0x7C
#else
#define RW_MGR_SGLE_READ 0x7E
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_MRS0_USER_MIRR 0x0C
#define RW_MGR_RETURN 0x01
#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
#define RW_MGR_MRS0_USER 0x07
#define RW_MGR_GUARANTEED_READ 0x4B
#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
#define RW_MGR_INIT_RESET_1_CKE_0 0x73
#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
#define RW_MGR_MRS0_DLL_RESET 0x02
#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
#define RW_MGR_CLEAR_DQS_ENABLE 0x48
#define RW_MGR_MRS1_MIRR 0x09
#define RW_MGR_READ_B2B_WAIT1 0x60
#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
#define RW_MGR_CONTENT_REFRESH_ALL 0x000980
#define RW_MGR_CONTENT_ZQCL 0x008380
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
#define RW_MGR_CONTENT_MRS2_MIRR 0x008580
#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
#define RW_MGR_CONTENT_ACTIVATE_1 0x000880
#define RW_MGR_CONTENT_MRS2 0x008280
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
#define RW_MGR_CONTENT_MRS1 0x008200
#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
#define RW_MGR_CONTENT_MRS3 0x008300
#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
#define RW_MGR_CONTENT_RDIMM_CMD 0x009180
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
#define RW_MGR_CONTENT_MRS3_MIRR 0x008600
#define RW_MGR_CONTENT_IDLE 0x080000
#define RW_MGR_CONTENT_READ_B2B 0x040E88
#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
#define RW_MGR_CONTENT_SGLE_READ 0x040F08
#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
#define RW_MGR_CONTENT_RETURN 0x080680
#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
#define RW_MGR_CONTENT_MRS0_USER 0x008100
#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168
#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
#define RW_MGR_CONTENT_MRS1_MIRR 0x008500
#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680

84
drivers/ddr/altera/sequencer_auto_ac_init.h
Unescape View File

@ -0,0 +1,84 @@
/*
* Copyright Altera Corporation (C) 2012-2015
*
* SPDX-License-Identifier: BSD-3-Clause
*/
const uint32_t ac_rom_init[] = {
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
0x20700000,
0x20780000,
0x10080831,
0x10080930,
0x10090004,
0x100a0008,
0x100b0000,
0x10380400,
0x10080849,
0x100808c8,
0x100a0004,
0x10090010,
0x100b0000,
0x30780000,
0x38780000,
0x30780000,
0x10680000,
0x106b0000,
0x10280400,
0x10480000,
0x1c980000,
0x1c9b0000,
0x1c980008,
0x1c9b0008,
0x38f80000,
0x3cf80000,
0x38780000,
0x18180000,
0x18980000,
0x13580000,
0x135b0000,
0x13580008,
0x135b0008,
0x33780000,
0x10580008,
0x10780000
#else
0x20700000,
0x20780000,
0x10080431,
0x10080530,
0x10090004,
0x100a0008,
0x100b0000,
0x10380400,
0x10080449,
0x100804c8,
0x100a0004,
0x10090010,
0x100b0000,
0x30780000,
0x38780000,
0x30780000,
0x10680000,
0x106b0000,
0x10280400,
0x10480000,
0x1c980000,
0x1c9b0000,
0x1c980008,
0x1c9b0008,
0x38f80000,
0x3cf80000,
0x38780000,
0x18180000,
0x18980000,
0x13580000,
0x135b0000,
0x13580008,
0x135b0008,
0x33780000,
0x10580008,
0x10780000
#endif /* CONFIG_SOCFPGA_ARRIA5 */
};

268
drivers/ddr/altera/sequencer_auto_inst_init.h
Unescape View File

@ -0,0 +1,268 @@
/*
* Copyright Altera Corporation (C) 2012-2015
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
const u32 inst_rom_init[] = {
0x80000,
0x80680,
0x8180,
0x8200,
0x8280,
0x8300,
0x8380,
0x8100,
0x8480,
0x8500,
0x8580,
0x8600,
0x8400,
0x800,
0x8680,
0x880,
0xa680,
0x80680,
0x900,
0x80680,
0x980,
0x8680,
0x80680,
0xb68,
0xcce8,
0xae8,
0x8ce8,
0xb88,
0xec88,
0xa08,
0xac88,
0x80680,
0xce00,
0xcd80,
0xe700,
0xc00,
0x20ce0,
0x20ce0,
0x20ce0,
0x20ce0,
0xd00,
0x680,
0x680,
0x680,
0x680,
0x60e80,
0x61080,
0x61080,
0x61080,
0xa680,
0x8680,
0x80680,
0xce00,
0xcd80,
0xe700,
0xc00,
0x30ce0,
0x30ce0,
0x30ce0,
0x30ce0,
0xd00,
0x680,
0x680,
0x680,
0x680,
0x70e80,
0x71080,
0x71080,
0x71080,
0xa680,
0x8680,
0x80680,
0x1158,
0x6d8,
0x80680,
0x1168,
0x7e8,
0x7e8,
0x87e8,
0x40fe8,
0x410e8,
0x410e8,
0x410e8,
0x1168,
0x7e8,
0x7e8,
0xa7e8,
0x80680,
0x40e88,
0x41088,
0x41088,
0x41088,
0x40f68,
0x410e8,
0x410e8,
0x410e8,
0xa680,
0x40fe8,
0x410e8,
0x410e8,
0x410e8,
0x41008,
0x41088,
0x41088,
0x41088,
0x1100,
0xc680,
0x8680,
0xe680,
0x80680,
0x0,
0x8000,
0xa000,
0xc000,
0x80000,
0x80,
0x8080,
0xa080,
0xc080,
0x80080,
0x9180,
0x8680,
0xa680,
0x80680,
0x40f08,
0x80680
};
#else
const u32 inst_rom_init[] = {
0x80000,
0x80680,
0x8180,
0x8200,
0x8280,
0x8300,
0x8380,
0x8100,
0x8480,
0x8500,
0x8580,
0x8600,
0x8400,
0x800,
0x8680,
0x880,
0xa680,
0x80680,
0x900,
0x80680,
0x980,
0x8680,
0x80680,
0xb68,
0xcce8,
0xae8,
0x8ce8,
0xb88,
0xec88,
0xa08,
0xac88,
0x80680,
0xce00,
0xcd80,
0xe700,
0xc00,
0x20ce0,
0x20ce0,
0x20ce0,
0x20ce0,
0xd00,
0x680,
0x680,
0x680,
0x680,
0x60e80,
0x61080,
0x61080,
0x61080,
0xa680,
0x8680,
0x80680,
0xce00,
0xcd80,
0xe700,
0xc00,
0x30ce0,
0x30ce0,
0x30ce0,
0x30ce0,
0xd00,
0x680,
0x680,
0x680,
0x680,
0x70e80,
0x71080,
0x71080,
0x71080,
0xa680,
0x8680,
0x80680,
0x1158,
0x6d8,
0x80680,
0x1168,
0x7e8,
0x7e8,
0x87e8,
0x40fe8,
0x410e8,
0x410e8,
0x410e8,
0x1168,
0x7e8,
0x7e8,
0xa7e8,
0x80680,
0x40e88,
0x41088,
0x41088,
0x41088,
0x40f68,
0x410e8,
0x410e8,
0x410e8,
0xa680,
0x40fe8,
0x410e8,
0x410e8,
0x410e8,
0x41008,
0x41088,
0x41088,
0x41088,
0x1100,
0xc680,
0x8680,
0xe680,
0x80680,
0x0,
0x0,
0xa000,
0x8000,
0x80000,
0x80,
0x80,
0x80,
0x80,
0xa080,
0x8080,
0x80080,
0x9180,
0x8680,
0xa680,
0x80680,
0x40f08,
0x80680
};
#endif /* CONFIG_SOCFPGA_ARRIA5 */

121
drivers/ddr/altera/sequencer_defines.h
Unescape View File

@ -0,0 +1,121 @@
/*
* Copyright Altera Corporation (C) 2012-2015
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _SEQUENCER_DEFINES_H_
#define _SEQUENCER_DEFINES_H_
#define AC_ROM_MR1_MIRR 0000000000100
#define AC_ROM_MR1_OCD_ENABLE
#define AC_ROM_MR2_MIRR 0000000010000
#define AC_ROM_MR3_MIRR 0000000000000
#define AC_ROM_MR0_CALIB
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000
#define AC_ROM_MR0_DLL_RESET 0100100110000
#define AC_ROM_MR0_MIRR 0100001001001
#define AC_ROM_MR0 0100000110001
#else
#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
#define AC_ROM_MR0_DLL_RESET 0010100110000
#define AC_ROM_MR0_MIRR 0010001001001
#define AC_ROM_MR0 0010000110001
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define AC_ROM_MR1 0000000000100
#define AC_ROM_MR2 0000000001000
#define AC_ROM_MR3 0000000000000
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define AFI_CLK_FREQ 534
#else
#define AFI_CLK_FREQ 401
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define AFI_RATE_RATIO 1
#define AVL_CLK_FREQ 67
#define BFM_MODE 0
#define BURST2 0
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define CALIB_LFIFO_OFFSET 8
#define CALIB_VFIFO_OFFSET 6
#else
#define CALIB_LFIFO_OFFSET 7
#define CALIB_VFIFO_OFFSET 5
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define GUARANTEED_READ_BRINGUP_TEST 0
#define HARD_PHY 1
#define HARD_VFIFO 1
#define HPS_HW 1
#define HR_DDIO_OUT_HAS_THREE_REGS 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define IO_DELAY_PER_OPA_TAP 234
#else
#define IO_DELAY_PER_OPA_TAP 312
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define IO_DLL_CHAIN_LENGTH 8
#define IO_DM_OUT_RESERVE 0
#define IO_DQDQS_OUT_PHASE_MAX 0
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define IO_DQS_EN_DELAY_MAX 15
#define IO_DQS_EN_DELAY_OFFSET 16
#else
#define IO_DQS_EN_DELAY_MAX 31
#define IO_DQS_EN_DELAY_OFFSET 0
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define IO_DQS_EN_PHASE_MAX 7
#define IO_DQS_IN_DELAY_MAX 31
#define IO_DQS_IN_RESERVE 4
#define IO_DQS_OUT_RESERVE 6
#define IO_DQ_OUT_RESERVE 0
#define IO_IO_IN_DELAY_MAX 31
#define IO_IO_OUT1_DELAY_MAX 31
#define IO_IO_OUT2_DELAY_MAX 0
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MARGIN_VARIATION_TEST 0
#define MAX_LATENCY_COUNT_WIDTH 5
#define MEM_ADDR_WIDTH 13
#define READ_VALID_FIFO_SIZE 16
#ifdef CONFIG_SOCFPGA_ARRIA5
/* The if..else... is not required if generated by tools */
#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
#else
#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
#endif /* CONFIG_SOCFPGA_ARRIA5 */
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_ADDRESS_WIDTH 15
#define RW_MGR_MEM_BANK_WIDTH 3
#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
#define RW_MGR_MEM_CLK_EN_WIDTH 1
#define RW_MGR_MEM_CONTROL_WIDTH 1
#define RW_MGR_MEM_DATA_MASK_WIDTH 5
#define RW_MGR_MEM_DATA_WIDTH 40
#define RW_MGR_MEM_DQ_PER_READ_DQS 8
#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
#define RW_MGR_MEM_ODT_WIDTH 1
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
#define RW_MGR_MR0_BL 1
#define RW_MGR_MR0_CAS_LATENCY 3
#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
#define SKEW_CALIBRATION 0
#define TINIT_CNTR1_VAL 32
#define TINIT_CNTR2_VAL 32
#define TINIT_CNTR0_VAL 132
#define TRESET_CNTR1_VAL 99
#define TRESET_CNTR2_VAL 10
#define TRESET_CNTR0_VAL 132
#endif /* _SEQUENCER_DEFINES_H_ */
Write Preview
Loading…
Cancel
Save