From 3dc80934f4651a3ef243a393be04b1f7f71daf24 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 22 Aug 2018 16:18:34 +0200 Subject: [PATCH] net: gem: Do not setup any clock for Xilinx SoC Versal Xilinx SoC Versal is using fixed clock where setting rate is not supported. That's why workaround the driver till real clock driver is supported. Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index e22d048..bc33126 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -461,6 +461,7 @@ static int zynq_gem_init(struct udevice *dev) break; } +#if !defined(CONFIG_ARCH_VERSAL) ret = clk_set_rate(&priv->clk, clk_rate); if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { dev_err(dev, "failed to set tx clock rate\n"); @@ -472,6 +473,9 @@ static int zynq_gem_init(struct udevice *dev) dev_err(dev, "failed to enable tx clock\n"); return ret; } +#else + debug("requested clk_rate %ld\n", clk_rate); +#endif setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK);