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@ -15,6 +15,13 @@ |
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#include <linux/compiler.h> |
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#include <part.h> |
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#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) |
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#define MMC_SUPPORTS_TUNING |
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#endif |
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) |
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#define MMC_SUPPORTS_TUNING |
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#endif |
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/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ |
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#define SD_VERSION_SD (1U << 31) |
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#define MMC_VERSION_MMC (1U << 30) |
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@ -52,12 +59,17 @@ |
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#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) |
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#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) |
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#define MMC_MODE_HS (1 << 0) |
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#define MMC_MODE_HS_52MHz (1 << 1) |
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#define MMC_MODE_4BIT (1 << 2) |
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#define MMC_MODE_8BIT (1 << 3) |
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#define MMC_MODE_SPI (1 << 4) |
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#define MMC_MODE_DDR_52MHz (1 << 5) |
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#define MMC_CAP(mode) (1 << mode) |
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#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS)) |
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#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52) |
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#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52) |
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#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200) |
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#define MMC_MODE_8BIT BIT(30) |
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#define MMC_MODE_4BIT BIT(29) |
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#define MMC_MODE_1BIT BIT(28) |
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#define MMC_MODE_SPI BIT(27) |
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#define SD_DATA_4BIT 0x00040000 |
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@ -82,6 +94,8 @@ |
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#define MMC_CMD_SET_BLOCKLEN 16 |
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#define MMC_CMD_READ_SINGLE_BLOCK 17 |
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#define MMC_CMD_READ_MULTIPLE_BLOCK 18 |
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#define MMC_CMD_SEND_TUNING_BLOCK 19 |
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#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21 |
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#define MMC_CMD_SET_BLOCK_COUNT 23 |
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#define MMC_CMD_WRITE_SINGLE_BLOCK 24 |
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#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 |
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@ -109,12 +123,34 @@ |
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#define SD_CMD_APP_SEND_OP_COND 41 |
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#define SD_CMD_APP_SEND_SCR 51 |
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static inline bool mmc_is_tuning_cmd(uint cmdidx) |
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{ |
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if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) || |
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(cmdidx == MMC_CMD_SEND_TUNING_BLOCK)) |
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return true; |
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return false; |
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} |
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/* SCR definitions in different words */ |
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#define SD_HIGHSPEED_BUSY 0x00020000 |
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#define SD_HIGHSPEED_SUPPORTED 0x00020000 |
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#define UHS_SDR12_BUS_SPEED 0 |
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#define HIGH_SPEED_BUS_SPEED 1 |
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#define UHS_SDR25_BUS_SPEED 1 |
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#define UHS_SDR50_BUS_SPEED 2 |
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#define UHS_SDR104_BUS_SPEED 3 |
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#define UHS_DDR50_BUS_SPEED 4 |
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#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED) |
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#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED) |
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#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED) |
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#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED) |
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#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED) |
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#define OCR_BUSY 0x80000000 |
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#define OCR_HCS 0x40000000 |
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#define OCR_S18R 0x1000000 |
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#define OCR_VOLTAGE_MASK 0x007FFF80 |
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#define OCR_ACCESS_MODE 0x60000000 |
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@ -206,11 +242,23 @@ |
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#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ |
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| EXT_CSD_CARD_TYPE_DDR_1_2V) |
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#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */ |
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/* SDR mode @1.8V I/O */ |
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#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */ |
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/* SDR mode @1.2V I/O */ |
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#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ |
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EXT_CSD_CARD_TYPE_HS200_1_2V) |
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#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ |
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#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ |
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#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ |
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#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ |
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#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ |
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#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */ |
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#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ |
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#define EXT_CSD_TIMING_HS 1 /* HS */ |
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#define EXT_CSD_TIMING_HS200 2 /* HS200 */ |
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#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) |
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#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) |
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@ -265,6 +313,20 @@ |
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#define ENHNCD_SUPPORT (0x2) |
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#define PART_ENH_ATTRIB (0x1f) |
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#define MMC_QUIRK_RETRY_SEND_CID BIT(0) |
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#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1) |
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enum mmc_voltage { |
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MMC_SIGNAL_VOLTAGE_000 = 0, |
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MMC_SIGNAL_VOLTAGE_120 = 1, |
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MMC_SIGNAL_VOLTAGE_180 = 2, |
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MMC_SIGNAL_VOLTAGE_330 = 4, |
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}; |
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#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\ |
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MMC_SIGNAL_VOLTAGE_180 |\
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MMC_SIGNAL_VOLTAGE_330) |
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/* Maximum block size for MMC */ |
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#define MMC_MAX_BLOCK_LEN 512 |
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@ -347,6 +409,14 @@ struct dm_mmc_ops { |
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int (*set_ios)(struct udevice *dev); |
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/**
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* send_init_stream() - send the initialization stream: 74 clock cycles |
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* This is used after power up before sending the first command |
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* |
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* @dev: Device to update |
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*/ |
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void (*send_init_stream)(struct udevice *dev); |
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/**
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* get_cd() - See whether a card is present |
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* |
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* @dev: Device to check |
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@ -361,6 +431,30 @@ struct dm_mmc_ops { |
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* @return 0 if write-enabled, 1 if write-protected, -ve on error |
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*/ |
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int (*get_wp)(struct udevice *dev); |
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#ifdef MMC_SUPPORTS_TUNING |
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/**
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* execute_tuning() - Start the tuning process |
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* |
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* @dev: Device to start the tuning |
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* @opcode: Command opcode to send |
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* @return 0 if OK, -ve on error |
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*/ |
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int (*execute_tuning)(struct udevice *dev, uint opcode); |
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#endif |
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) |
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/**
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* wait_dat0() - wait until dat0 is in the target state |
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* (CLK must be running during the wait) |
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* |
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* @dev: Device to check |
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* @state: target state |
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* @timeout: timeout in us |
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* @return 0 if dat0 is in the target state, -ve on error |
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*/ |
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int (*wait_dat0)(struct udevice *dev, int state, int timeout); |
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#endif |
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}; |
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#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) |
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@ -368,13 +462,19 @@ struct dm_mmc_ops { |
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int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
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struct mmc_data *data); |
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int dm_mmc_set_ios(struct udevice *dev); |
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void dm_mmc_send_init_stream(struct udevice *dev); |
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int dm_mmc_get_cd(struct udevice *dev); |
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int dm_mmc_get_wp(struct udevice *dev); |
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int dm_mmc_execute_tuning(struct udevice *dev, uint opcode); |
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int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout); |
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/* Transition functions for compatibility */ |
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int mmc_set_ios(struct mmc *mmc); |
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void mmc_send_init_stream(struct mmc *mmc); |
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int mmc_getcd(struct mmc *mmc); |
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int mmc_getwp(struct mmc *mmc); |
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int mmc_execute_tuning(struct mmc *mmc, uint opcode); |
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int mmc_wait_dat0(struct mmc *mmc, int state, int timeout); |
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#else |
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struct mmc_ops { |
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@ -406,6 +506,50 @@ struct sd_ssr { |
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unsigned int erase_offset; /* In milliseconds */ |
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}; |
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enum bus_mode { |
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MMC_LEGACY, |
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SD_LEGACY, |
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MMC_HS, |
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SD_HS, |
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MMC_HS_52, |
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MMC_DDR_52, |
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UHS_SDR12, |
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UHS_SDR25, |
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UHS_SDR50, |
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UHS_DDR50, |
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UHS_SDR104, |
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MMC_HS_200, |
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MMC_MODES_END |
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}; |
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const char *mmc_mode_name(enum bus_mode mode); |
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void mmc_dump_capabilities(const char *text, uint caps); |
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static inline bool mmc_is_mode_ddr(enum bus_mode mode) |
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{ |
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if (mode == MMC_DDR_52) |
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return true; |
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) |
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else if (mode == UHS_DDR50) |
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return true; |
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#endif |
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else |
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return false; |
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} |
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#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \ |
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MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
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MMC_CAP(UHS_DDR50)) |
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static inline bool supports_uhs(uint caps) |
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{ |
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) |
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return (caps & UHS_CAPS) ? true : false; |
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#else |
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return false; |
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#endif |
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} |
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/*
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* With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device |
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* with mmc_get_mmc_dev(). |
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@ -421,9 +565,12 @@ struct mmc { |
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void *priv; |
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uint has_init; |
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int high_capacity; |
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bool clk_disable; /* true if the clock can be turned off */ |
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uint bus_width; |
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uint clock; |
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enum mmc_voltage signal_voltage; |
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uint card_caps; |
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uint host_caps; |
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uint ocr; |
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uint dsr; |
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uint dsr_imp; |
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@ -436,18 +583,27 @@ struct mmc { |
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u8 wr_rel_set; |
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u8 part_config; |
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uint tran_speed; |
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uint legacy_speed; /* speed for the legacy mode provided by the card */ |
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uint read_bl_len; |
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#if CONFIG_IS_ENABLED(MMC_WRITE) |
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uint write_bl_len; |
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uint erase_grp_size; /* in 512-byte sectors */ |
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#endif |
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#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) |
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uint hc_wp_grp_size; /* in 512-byte sectors */ |
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#endif |
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#if CONFIG_IS_ENABLED(MMC_WRITE) |
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struct sd_ssr ssr; /* SD status register */ |
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#endif |
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u64 capacity; |
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u64 capacity_user; |
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u64 capacity_boot; |
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u64 capacity_rpmb; |
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u64 capacity_gp[4]; |
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#ifndef CONFIG_SPL_BUILD |
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u64 enh_user_start; |
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u64 enh_user_size; |
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#endif |
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#if !CONFIG_IS_ENABLED(BLK) |
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struct blk_desc block_dev; |
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#endif |
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@ -457,7 +613,21 @@ struct mmc { |
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int ddr_mode; |
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#if CONFIG_IS_ENABLED(DM_MMC) |
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struct udevice *dev; /* Device for this MMC controller */ |
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#if CONFIG_IS_ENABLED(DM_REGULATOR) |
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struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/ |
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struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/ |
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#endif |
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#endif |
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u8 *ext_csd; |
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u32 cardtype; /* cardtype read from the MMC */ |
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enum mmc_voltage current_voltage; |
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enum bus_mode selected_mode; /* mode currently used */ |
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enum bus_mode best_mode; /* best mode is the supported mode with the
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* highest bandwidth. It may not always be the |
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* operating mode due to limitations when |
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* accessing the boot partitions |
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*/ |
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u32 quirks; |
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}; |
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struct mmc_hwpart_conf { |
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@ -507,8 +677,36 @@ void mmc_destroy(struct mmc *mmc); |
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int mmc_unbind(struct udevice *dev); |
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int mmc_initialize(bd_t *bis); |
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int mmc_init(struct mmc *mmc); |
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int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error); |
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/**
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* mmc_of_parse() - Parse the device tree to get the capabilities of the host |
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* |
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* @dev: MMC device |
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* @cfg: MMC configuration |
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* @return 0 if OK, -ve on error |
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*/ |
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int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg); |
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int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); |
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void mmc_set_clock(struct mmc *mmc, uint clock); |
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/**
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* mmc_voltage_to_mv() - Convert a mmc_voltage in mV |
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* |
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* @voltage: The mmc_voltage to convert |
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* @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value) |
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*/ |
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int mmc_voltage_to_mv(enum mmc_voltage voltage); |
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/**
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* mmc_set_clock() - change the bus clock |
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* @mmc: MMC struct |
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* @clock: bus frequency in Hz |
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* @disable: flag indicating if the clock must on or off |
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* @return 0 if OK, -ve on error |
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*/ |
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int mmc_set_clock(struct mmc *mmc, uint clock, bool disable); |
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struct mmc *find_mmc_device(int dev_num); |
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int mmc_set_dev(int dev_num); |
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void print_mmc_devices(char separator); |
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Tom Rini
6 years ago