Whitebox
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

NAND: Update 4xx NDFC driver to match updated nand subsystem

Browse Source 
This patch changes the 4xx NAND driver ndfc.c to match the new
infrastructure from the updated NAND subsystem. This NAND
subsystem was recently synced again with the Linux 2.6.22 MTD/NAND
subsystem.

Tested successfully on AMCC Sequoia and Bamboo.

Signed-off-by: Stefan Roese <sr@denx.de>
master
Stefan Roese 18 years ago committed by Scott Wood
parent 1207226452
commit 3df2ece0f0
1 changed files with 41 additions and 42 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 83
      cpu/ppc4xx/ndfc.c

83
cpu/ppc4xx/ndfc.c
Unescape View File

@ -44,49 +44,39 @@
#include <asm/io.h>
#include <ppc4xx.h>
static u8 hwctl = 0;
/*
* We need to store the info, which chip-select (CS) is used for the
* chip number. For example on Sequoia NAND chip #0 uses
* CS #3.
*/
static int ndfc_cs[NDFC_MAX_BANKS];
static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
hwctl |= 0x1;
else
hwctl &= ~0x1;
if ( ctrl & NAND_ALE )
hwctl |= 0x2;
else
hwctl &= ~0x2;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
if (cmd == NAND_CMD_NONE)
return;
static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
return (in_8((u8 *)(base + NDFC_DATA)));
if (ctrl & NAND_CLE)
out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
else
out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
}
static int ndfc_dev_ready(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
while (!(in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY))
;
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
return 1;
return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
}
static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
u32 ccr;
ccr = in_be32((u32 *)(base + NDFC_CCR));
@ -98,7 +88,7 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
const u_char *dat, u_char *ecc_code)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
u32 ecc;
u8 *p = (u8 *)&ecc;
@ -123,7 +113,7 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
uint32_t *p = (uint32_t *) buf;
for (;len > 0; len -= 4)
@ -138,7 +128,7 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
uint32_t *p = (uint32_t *) buf;
for (; len > 0; len -= 4)
@ -148,7 +138,7 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
uint32_t *p = (uint32_t *) buf;
for (; len > 0; len -= 4)
@ -165,24 +155,37 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
* Don't use "chip" to address the NAND device,
* generate the cs from the address where it is encoded.
*/
int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
int cs = ndfc_cs[chip];
/* Set NandFlash Core Configuration Register */
/* 1 col x 2 rows */
out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);
}
int board_nand_init(struct nand_chip *nand)
{
int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
static int chip = 0;
nand->cmd_ctrl = ndfc_hwcontrol;
nand->read_byte = ndfc_read_byte;
nand->read_buf = ndfc_read_buf;
nand->dev_ready = ndfc_dev_ready;
/*
* Save chip-select for this chip #
*/
ndfc_cs[chip] = cs;
/*
* Select required NAND chip in NDFC
*/
board_nand_select_device(nand, chip);
nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
nand->cmd_ctrl = ndfc_hwcontrol;
nand->chip_delay = 50;
nand->read_buf = ndfc_read_buf;
nand->dev_ready = ndfc_dev_ready;
nand->ecc.correct = nand_correct_data;
nand->ecc.hwctl = ndfc_enable_hwecc;
nand->ecc.calculate = ndfc_calculate_ecc;
@ -203,11 +206,7 @@ int board_nand_init(struct nand_chip *nand)
mtebc(pb0ap, CFG_EBC_PB0AP);
#endif
/*
* Select required NAND chip in NDFC
*/
board_nand_select_device(nand, cs);
out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);
chip++;
return 0;
}

Write Preview
Loading…
Cancel
Save