Add IDMA example code (tested on 8260 only) * Add support for Purple Board (MIPS64 5Kc) * Add support for MIPS64 5Kc CPUs * Fix missing setting of "loadaddr" and "bootfile" on ARM and MIPS * Patch by Denis Peter, 04 Apr 2003: - update MIP405-4 board * Patches by Denis Peter, 03 April 2003: - fix PCI IRQs on MPL boards - fix two more un-relocated pointer problems * Fix behaviour of "run" command: - print error message iv variable does not exist - terminate processing of arguments in case of error * Patches by Peter Figuli, 10 Mar 2003 - Add support for BTUART on PXA platform - Add support for WEP EP250 (PXA) board * Fix flash problems on INCA-IP; add tool to allow bruning images to flash using a BDI2000 * Implement fix for I2C Edge Conditions problem for all boards that use the bit-banging driver (common/soft_i2c.c) * Add patches by Robert Schwebel, 31 Mar 2003: - csb226 board: bring in sync with innokom/memsetup.S - csb226 board: fix MDREFR handling - misc doc fixes / extensions - innokom board: cleanup, MDREFR fix in memsetup.S, config update - add BOOT_PROGRESS to armlinux.cmaster
wdenk
22 years ago
parent
36c05a80ec
commit
3e38691e8f
@ -1,133 +0,0 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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cpu/mpc8xx/start.o (.text) |
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common/dlmalloc.o (.text) |
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ppc/ppcstring.o (.text) |
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ppc/vsprintf.o (.text) |
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ppc/crc32.o (.text) |
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ppc/zlib.o (.text) |
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|
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. = env_offset; |
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common/environment.o(.text) |
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|
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*(.text) |
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*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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|
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
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|
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. = ALIGN(256); |
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__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
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{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
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|
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@ -1,131 +0,0 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
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ppc/vsprintf.o (.text) |
||||
ppc/crc32.o (.text) |
||||
|
||||
. = env_offset; |
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common/environment.o(.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
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|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
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_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
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_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
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{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
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|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
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{ |
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*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
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} |
||||
_end = . ; |
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PROVIDE (end = .); |
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} |
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|
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@ -0,0 +1,47 @@ |
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#
|
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# (C) Copyright 2000, 2002
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
|
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#
|
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|
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include $(TOPDIR)/config.mk |
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|
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LIB = lib$(BOARD).a
|
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|
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OBJS := wepep250.o flash.o
|
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SOBJS := memsetup.o
|
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|
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
|
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|
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clean: |
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rm -f $(SOBJS) $(OBJS)
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|
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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|
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#########################################################################
|
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|
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
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|
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-include .depend |
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|
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#########################################################################
|
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@ -0,0 +1,11 @@ |
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#
|
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# This is config used for compilation of WEP EP250 sources
|
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#
|
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# You might change location of U-Boot in memory by setting right TEXT_BASE.
|
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# This allows for example having one copy located at the end of ram and stored
|
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# in flash device and later on while developing use other location to test
|
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# the code in RAM device only.
|
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#
|
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|
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TEXT_BASE = 0xa1fe0000
|
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#TEXT_BASE = 0xa1001000
|
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@ -0,0 +1,321 @@ |
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/*
|
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* Copyright (C) 2003 ETC s.r.o. |
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* |
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* This code was inspired by Marius Groeger and Kyle Harris code |
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* available in other board ports for U-Boot |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Written by Peter Figuli <peposh@etc.sk>, 2003. |
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* |
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*/ |
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|
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#include <common.h> |
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#include "intel.h" |
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|
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|
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/*
|
||||
* This code should handle CFI FLASH memory device. This code is very |
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* minimalistic approach without many essential error handling code as well. |
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* Because U-Boot actually is missing smart handling of FLASH device, |
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* we just set flash_id to anything else to FLASH_UNKNOW, so common code |
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* can call us without any restrictions. |
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* TODO: Add CFI Query, to be able to determine FLASH device. |
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* TODO: Add error handling code |
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* NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but |
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* hopefully may work with other configurations. |
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*/ |
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|
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#if ( WEP_FLASH_BUS_WIDTH == 1 ) |
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# define FLASH_BUS vu_char |
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# if ( WEP_FLASH_INTERLEAVE == 1 ) |
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# define FLASH_CMD( x ) x |
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# else |
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# error "With 8bit bus only one chip is allowed" |
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# endif |
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|
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|
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#elif ( WEP_FLASH_BUS_WIDTH == 2 ) |
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# define FLASH_BUS vu_short |
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# if ( WEP_FLASH_INTERLEAVE == 1 ) |
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# define FLASH_CMD( x ) x |
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# elif ( WEP_FLASH_INTERLEAVE == 2 ) |
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# define FLASH_CMD( x ) (( x << 8 )| x ) |
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# else |
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# error "With 16bit bus only 1 or 2 chip(s) are allowed" |
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# endif |
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|
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|
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#elif ( WEP_FLASH_BUS_WIDTH == 4 ) |
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# define FLASH_BUS vu_long |
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# if ( WEP_FLASH_INTERLEAVE == 1 ) |
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# define FLASH_CMD( x ) x |
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# elif ( WEP_FLASH_INTERLEAVE == 2 ) |
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# define FLASH_CMD( x ) (( x << 16 )| x ) |
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# elif ( WEP_FLASH_INTERLEAVE == 4 ) |
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# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) |
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# else |
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# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" |
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# endif |
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|
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#else |
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# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" |
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#endif |
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|
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|
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
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|
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static FLASH_BUS flash_status_reg (void) |
||||
{ |
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|
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FLASH_BUS *addr = (FLASH_BUS *) 0; |
||||
|
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*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); |
||||
|
||||
return *addr; |
||||
} |
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|
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static int flash_ready (ulong timeout) |
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{ |
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int ok = 1; |
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|
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reset_timer_masked (); |
||||
while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != |
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FLASH_CMD (CFI_INTEL_SR_READY)) { |
||||
if (get_timer_masked () > timeout && timeout != 0) { |
||||
ok = 0; |
||||
break; |
||||
} |
||||
} |
||||
return ok; |
||||
} |
||||
|
||||
#if ( CFG_MAX_FLASH_BANKS != 1 ) |
||||
# error "WEP platform has only one flash bank!" |
||||
#endif |
||||
|
||||
|
||||
ulong flash_init (void) |
||||
{ |
||||
int i; |
||||
FLASH_BUS address = WEP_FLASH_BASE; |
||||
|
||||
flash_info[0].size = WEP_FLASH_BANK_SIZE; |
||||
flash_info[0].sector_count = CFG_MAX_FLASH_SECT; |
||||
flash_info[0].flash_id = INTEL_MANUFACT; |
||||
memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); |
||||
|
||||
for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { |
||||
flash_info[0].start[i] = address; |
||||
#ifdef WEP_FLASH_UNLOCK |
||||
/* Some devices are hw locked after start. */ |
||||
*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP); |
||||
*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK); |
||||
flash_ready (0); |
||||
*((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); |
||||
#endif |
||||
address += WEP_FLASH_SECT_SIZE; |
||||
} |
||||
|
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_FLASH_BASE, |
||||
CFG_FLASH_BASE + _armboot_end_data - _armboot_start, |
||||
&flash_info[0]); |
||||
|
||||
flash_protect (FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); |
||||
|
||||
return WEP_FLASH_BANK_SIZE; |
||||
} |
||||
|
||||
void flash_print_info (flash_info_t * info) |
||||
{ |
||||
int i; |
||||
|
||||
printf (" Intel vendor\n"); |
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
if (!(i % 5)) { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
printf (" %08lX%s", info->start[i], |
||||
info->protect[i] ? " (RO)" : " "); |
||||
} |
||||
printf ("\n"); |
||||
} |
||||
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last) |
||||
{ |
||||
int flag, non_protected = 0, sector; |
||||
int rc = ERR_OK; |
||||
|
||||
FLASH_BUS *address; |
||||
|
||||
for (sector = s_first; sector <= s_last; sector++) { |
||||
if (!info->protect[sector]) { |
||||
non_protected++; |
||||
} |
||||
} |
||||
|
||||
if (!non_protected) { |
||||
return ERR_PROTECTED; |
||||
} |
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout |
||||
* here. Remember that our exception vectors are |
||||
* at address 0 in the flash, and we don't want a |
||||
* (ticker) exception to happen while the flash |
||||
* chip is in programming mode. |
||||
*/ |
||||
flag = disable_interrupts (); |
||||
|
||||
|
||||
/* Start erase on unprotected sectors */ |
||||
for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { |
||||
if (info->protect[sector]) { |
||||
printf ("Protected sector %2d skipping...\n", sector); |
||||
continue; |
||||
} else { |
||||
printf ("Erasing sector %2d ... ", sector); |
||||
} |
||||
|
||||
address = (FLASH_BUS *) (info->start[sector]); |
||||
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); |
||||
*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); |
||||
if (flash_ready (CFG_FLASH_ERASE_TOUT)) { |
||||
*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); |
||||
printf ("ok.\n"); |
||||
} else { |
||||
*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); |
||||
rc = ERR_TIMOUT; |
||||
printf ("timeout! Aborting...\n"); |
||||
break; |
||||
} |
||||
*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); |
||||
} |
||||
if (ctrlc ()) |
||||
printf ("User Interrupt!\n"); |
||||
|
||||
/* allow flash to settle - wait 10 ms */ |
||||
udelay_masked (10000); |
||||
if (flag) { |
||||
enable_interrupts (); |
||||
} |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) |
||||
{ |
||||
FLASH_BUS *address = (FLASH_BUS *) dest; |
||||
int rc = ERR_OK; |
||||
int flag; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ((*address & data) != data) { |
||||
return ERR_NOT_ERASED; |
||||
} |
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout |
||||
* here. Remember that our exception vectors are |
||||
* at address 0 in the flash, and we don't want a |
||||
* (ticker) exception to happen while the flash |
||||
* chip is in programming mode. |
||||
*/ |
||||
|
||||
flag = disable_interrupts (); |
||||
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); |
||||
*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); |
||||
*address = data; |
||||
|
||||
if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { |
||||
*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); |
||||
rc = ERR_TIMOUT; |
||||
printf ("timeout! Aborting...\n"); |
||||
} |
||||
|
||||
*address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); |
||||
if (flag) { |
||||
enable_interrupts (); |
||||
} |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong read_addr, write_addr; |
||||
FLASH_BUS data; |
||||
int i, result = ERR_OK; |
||||
|
||||
|
||||
read_addr = addr & ~(sizeof (FLASH_BUS) - 1); |
||||
write_addr = read_addr; |
||||
if (read_addr != addr) { |
||||
data = 0; |
||||
for (i = 0; i < sizeof (FLASH_BUS); i++) { |
||||
if (read_addr < addr || cnt == 0) { |
||||
data |= *((uchar *) read_addr) << i * 8; |
||||
} else { |
||||
data |= (*src++) << i * 8; |
||||
cnt--; |
||||
} |
||||
read_addr++; |
||||
} |
||||
if ((result = write_data (info, write_addr, data)) != ERR_OK) { |
||||
return result; |
||||
} |
||||
write_addr += sizeof (FLASH_BUS); |
||||
} |
||||
for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { |
||||
if ((result = write_data (info, write_addr, |
||||
*((FLASH_BUS *) src))) != ERR_OK) { |
||||
return result; |
||||
} |
||||
write_addr += sizeof (FLASH_BUS); |
||||
src += sizeof (FLASH_BUS); |
||||
} |
||||
if (cnt > 0) { |
||||
read_addr = write_addr; |
||||
data = 0; |
||||
for (i = 0; i < sizeof (FLASH_BUS); i++) { |
||||
if (cnt > 0) { |
||||
data |= (*src++) << i * 8; |
||||
cnt--; |
||||
} else { |
||||
data |= *((uchar *) read_addr) << i * 8; |
||||
} |
||||
read_addr++; |
||||
} |
||||
if ((result = write_data (info, write_addr, data)) != 0) { |
||||
return result; |
||||
} |
||||
} |
||||
return ERR_OK; |
||||
} |
||||
@ -0,0 +1,100 @@ |
||||
/*
|
||||
* Copyright (C) 2002 ETC s.r.o. |
||||
* All rights reserved. |
||||
* |
||||
* Redistribution and use in source and binary forms, with or without |
||||
* modification, are permitted provided that the following conditions |
||||
* are met: |
||||
* 1. Redistributions of source code must retain the above copyright |
||||
* notice, this list of conditions and the following disclaimer. |
||||
* 2. Redistributions in binary form must reproduce the above copyright |
||||
* notice, this list of conditions and the following disclaimer in the |
||||
* documentation and/or other materials provided with the distribution. |
||||
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors |
||||
* may be used to endorse or promote products derived from this software |
||||
* without specific prior written permission. |
||||
* |
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE |
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||
* |
||||
* Written by Marcel Telka <marcel@telka.sk>, 2002. |
||||
* |
||||
* Documentation: |
||||
* [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, |
||||
* 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 |
||||
* [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, |
||||
* 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 |
||||
* |
||||
* This file is taken from OpenWinCE project hosted by SourceForge.net |
||||
* |
||||
*/ |
||||
|
||||
#ifndef FLASH_INTEL_H |
||||
#define FLASH_INTEL_H |
||||
|
||||
#include <common.h> |
||||
|
||||
/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ |
||||
|
||||
#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ |
||||
|
||||
/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ |
||||
|
||||
#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ |
||||
#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ |
||||
|
||||
/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ |
||||
|
||||
#define CFI_CHIP_INTEL_28F320J3A 0x0016 |
||||
#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" |
||||
#define CFI_CHIP_INTEL_28F640J3A 0x0017 |
||||
#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" |
||||
#define CFI_CHIP_INTEL_28F128J3A 0x0018 |
||||
#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" |
||||
|
||||
/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ |
||||
|
||||
#define CFI_CHIP_INTEL_28F640K3 0x8801 |
||||
#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" |
||||
#define CFI_CHIP_INTEL_28F128K3 0x8802 |
||||
#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" |
||||
#define CFI_CHIP_INTEL_28F256K3 0x8803 |
||||
#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" |
||||
#define CFI_CHIP_INTEL_28F640K18 0x8805 |
||||
#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" |
||||
#define CFI_CHIP_INTEL_28F128K18 0x8806 |
||||
#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" |
||||
#define CFI_CHIP_INTEL_28F256K18 0x8807 |
||||
#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" |
||||
|
||||
#endif /* FLASH_INTEL_H */ |
||||
|
||||
@ -0,0 +1,147 @@ |
||||
/* |
||||
* Copyright (C) 2001, 2002 ETC s.r.o. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License |
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version. |
||||
*
|
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*
|
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA |
||||
* 02111-1307, USA. |
||||
*
|
||||
* Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
|
||||
* Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
|
||||
* |
||||
* This file is taken from OpenWinCE project hosted by SourceForge.net |
||||
* |
||||
* Documentation: |
||||
* [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors |
||||
* Developer's Manual", February 2002, Order Number: 278522-001 |
||||
* [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P", |
||||
* Revision 1.0, February 2002 |
||||
* [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)", |
||||
* Revision 1.0, February 2002 |
||||
*
|
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
#include <asm/arch/pxa-regs.h> |
||||
|
||||
.globl memsetup
|
||||
memsetup: |
||||
|
||||
mov r10, lr |
||||
|
||||
/* setup memory - see 6.12 in [1] |
||||
* Step 1 - wait 200 us |
||||
*/ |
||||
mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */
|
||||
1: subs r0, r0, #1 |
||||
bne 1b |
||||
/* TODO: complete step 1 for Synchronous Static memory*/ |
||||
|
||||
ldr r0, =0x48000000 /* MC_BASE */ |
||||
|
||||
|
||||
|
||||
/* step 1.a - setup MSCx |
||||
*/ |
||||
ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */ |
||||
str r1, [r0, #0x8] /* MSC0_OFFSET */ |
||||
|
||||
/* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI |
||||
* see AUTO REFRESH chapter in section D. in [2] and in [3] |
||||
* DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633 |
||||
* DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633 |
||||
* TODO: complete for Synchronous Static memory |
||||
*/ |
||||
ldr r1, [r0, #4] /* MDREFR_OFFSET */ |
||||
ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */ |
||||
bic r1, r1, r2 |
||||
#if defined( WEP_SDRAM_K4S281633 ) |
||||
orr r1, r1, #48 /* MDREFR_DRI(48) */ |
||||
#elif defined( WEP_SDRAM_K4S561633 ) |
||||
orr r1, r1, #24 /* MDREFR_DRI(24) */ |
||||
#else |
||||
#error SDRAM chip is not defined |
||||
#endif |
||||
|
||||
str r1, [r0, #4] /* MDREFR_OFFSET */ |
||||
|
||||
/* Step 2 - only for Synchronous Static memory (TODO) |
||||
* |
||||
* Step 3 - same as step 4 |
||||
* |
||||
* Step 4 |
||||
* |
||||
* Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2 |
||||
*/ |
||||
orr r1, r1, #0x00010000 /* MDREFR_K1RUN */ |
||||
bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */ |
||||
str r1, [r0, #4] /* MDREFR_OFFSET */ |
||||
|
||||
/* Step 4.b - clear MDREFR:SLFRSH */ |
||||
bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */ |
||||
str r1, [r0, #4] /* MDREFR_OFFSET */ |
||||
|
||||
/* Step 4.c - set MDREFR:E1PIN */ |
||||
orr r1, r1, #0x00008000 /* MDREFR_E1PIN */ |
||||
str r1, [r0, #4] /* MDREFR_OFFSET */ |
||||
|
||||
/* Step 4.d - automatically done |
||||
* |
||||
* Steps 4.e and 4.f - configure SDRAM |
||||
*/ |
||||
#if defined( WEP_SDRAM_K4S281633 ) |
||||
ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */ |
||||
#elif defined( WEP_SDRAM_K4S561633 ) |
||||
ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */ |
||||
#else |
||||
#error SDRAM chip is not defined |
||||
#endif |
||||
str r1, [r0, #0] /* MDCNFG_OFFSET */ |
||||
|
||||
/* Step 5 - wait at least 200 us for SDRAM |
||||
* see section B. in [2] |
||||
*/ |
||||
mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */
|
||||
1: subs r2, r2, #1 |
||||
bne 1b |
||||
|
||||
/* Step 6 - after reset dcache is disabled, so automatically done |
||||
* |
||||
* Step 7 - eight refresh cycles |
||||
*/ |
||||
mov r2, #0xA0000000 |
||||
ldr r3, [r2] |
||||
ldr r3, [r2] |
||||
ldr r3, [r2] |
||||
ldr r3, [r2] |
||||
ldr r3, [r2] |
||||
ldr r3, [r2] |
||||
ldr r3, [r2] |
||||
ldr r3, [r2] |
||||
|
||||
/* Step 8 - we don't need dcache now |
||||
* |
||||
* Step 9 - enable SDRAM partition 0 |
||||
*/ |
||||
orr r1, r1, #1 /* MDCNFG_DE0 */ |
||||
str r1, [r0, #0] /* MDCNFG_OFFSET */ |
||||
|
||||
/* Step 10 - write MDMRS */ |
||||
mov r1, #0 |
||||
str r1, [r0, #0x40] /* MDMRS_OFFSET */ |
||||
|
||||
/* Step 11 - optional (TODO) */ |
||||
|
||||
mov pc,r10 |
||||
|
||||
@ -0,0 +1,55 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/xscale/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
armboot_end_data = .; |
||||
|
||||
. = ALIGN(4); |
||||
bss_start = .; |
||||
.bss : { *(.bss) } |
||||
bss_end = .; |
||||
|
||||
armboot_end = .; |
||||
} |
||||
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* Copyright (C) 2003 ETC s.r.o. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Written by Peter Figuli <peposh@etc.sk>, 2003. |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/pxa-regs.h> |
||||
|
||||
int board_init( void ){ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
gd->bd->bi_arch_number = 288;
|
||||
gd->bd->bi_boot_params = 0xa0000000; |
||||
/*
|
||||
* Setup GPIO stuff to get serial working |
||||
*/ |
||||
#if defined( CONFIG_FFUART ) |
||||
GPDR1 = 0x80; |
||||
GAFR1_L = 0x8010; |
||||
#elif defined( CONFIG_BTUART ) |
||||
GPDR1 = 0x800; |
||||
GAFR1_L = 0x900000; |
||||
#endif |
||||
PSSR = 0x20; |
||||
|
||||
/*
|
||||
* Following code is just bug workaround, remove it if not neccessary |
||||
*/ |
||||
|
||||
/* cpu/xscale/cpu.c do not set armboot_real_end that is used for
|
||||
malloc pool.*/ |
||||
if( _armboot_real_end == 0xbadc0de ){ |
||||
_armboot_real_end = _armboot_end; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int dram_init( void ){ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#if ( CONFIG_NR_DRAM_BANKS > 0 ) |
||||
gd->bd->bi_dram[0].start = WEP_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = WEP_SDRAM_1_SIZE; |
||||
#endif |
||||
#if ( CONFIG_NR_DRAM_BANKS > 1 ) |
||||
gd->bd->bi_dram[1].start = WEP_SDRAM_2; |
||||
gd->bd->bi_dram[1].size = WEP_SDRAM_2_SIZE; |
||||
#endif |
||||
#if ( CONFIG_NR_DRAM_BANKS > 2 ) |
||||
gd->bd->bi_dram[2].start = WEP_SDRAM_3; |
||||
gd->bd->bi_dram[2].size = WEP_SDRAM_3_SIZE; |
||||
#endif |
||||
#if ( CONFIG_NR_DRAM_BANKS > 3 ) |
||||
gd->bd->bi_dram[3].start = WEP_SDRAM_4; |
||||
gd->bd->bi_dram[3].size = WEP_SDRAM_4_SIZE; |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
@ -0,0 +1,44 @@ |
||||
|
||||
Flash programming on the INCA-IP board is complicated because of the |
||||
EBU swapping unit. A BDI2000 can be used for flash programming only |
||||
if the EBU swapping unit is enabled; otherwise it will not detect the |
||||
flash memory. But the EBU swapping unit is disadbled after reset, so |
||||
if you program some code to flash with the swapping unit on, it will |
||||
not be runnable with the swapping unit off. |
||||
|
||||
The consequence is that you have to write a pre-swapped image to |
||||
flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is |
||||
provided in the "tools/" directory. Use it as follows: |
||||
|
||||
bash$ ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp |
||||
|
||||
Note that the current BDI config file _disables_ the EBU swapping |
||||
unit for the flash bank 0. To enable it, (this is required for the |
||||
BDI flash commands to work) uncomment the following line in the |
||||
config file: |
||||
|
||||
;WM32 0xb8000260 0x404161ff ; Swapping unit enabled |
||||
|
||||
and comment out |
||||
|
||||
WM32 0xb8000260 0x004161ff ; Swapping unit disabled |
||||
|
||||
Alternatively, you can use "mm 0xb8000260 <value>" commands to |
||||
enable/disable the swapping unit manually. |
||||
|
||||
Just for reference, here is the complete sequence of actions we took |
||||
to install a U-Boot image into flash. |
||||
|
||||
1. ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp |
||||
|
||||
2. From BDI: |
||||
|
||||
mm 0xb8000260 0x404161ff |
||||
erase 0xb0000000 |
||||
erase 0xb0010000 |
||||
prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin |
||||
mm 0xb8000260 0x004161ff |
||||
go 0xb0000000 |
||||
|
||||
|
||||
(C) 2003 Wolfgang Denk |
||||
@ -0,0 +1,10 @@ |
||||
(C) 2003 Arun Dharankar <ADharankar@ATTBI.Com> |
||||
|
||||
Attached is an IDMA example code for MPC8260/PPCBoot. I had tried to |
||||
search around and could not find any for implementing IDMA, so |
||||
implemented one. Its not coded in the best way, but works. |
||||
|
||||
Also, I was able to test the IDMA specific code under Linux also |
||||
(with modifications). My requirement was to implement it for |
||||
CompactFlash implemented in memory mode, and it works for it under |
||||
PPCBoot and Linux. |
||||
@ -0,0 +1,53 @@ |
||||
Notes on the scheduler in sched.c: |
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
||||
|
||||
'sched.c' provides an very simplistic multi-threading scheduler. |
||||
See the example, function 'sched(...)', in the same file for its |
||||
API usage. |
||||
|
||||
Until an exhaustive testing can be done, the implementation cannot |
||||
qualify as that of production quality. It works with the example |
||||
in 'sched.c', it may or may not work in other cases. |
||||
|
||||
|
||||
Limitations: |
||||
~~~~~~~~~~~~ |
||||
|
||||
- There are NO primitives for thread synchronization (locking, |
||||
notify etc). |
||||
|
||||
- Only the GPRs and FPRs context is saved during a thread context |
||||
switch. Other registers on the PowerPC processor (60x, 7xx, 7xxx |
||||
etc) are NOT saved. |
||||
|
||||
- The scheduler is NOT transparent to the user. The user |
||||
applications must invoke thread_yield() to allow other threads to |
||||
scheduler. |
||||
|
||||
- There are NO priorities, and the scheduling policy is round-robin |
||||
based. |
||||
|
||||
- There are NO capabilities to collect thread CPU usage, scheduler |
||||
stats, thread status etc. |
||||
|
||||
- The semantics are somewhat based on those of pthreads, but NOT |
||||
the same. |
||||
|
||||
- Only seven threads are allowed. These can be easily increased by |
||||
changing "#define MAX_THREADS" depending on the available memory. |
||||
|
||||
- The stack size of each thread is 8KBytes. This can be easily |
||||
increased depending on the requirement and the available memory, |
||||
by increasing "#define STK_SIZE". |
||||
|
||||
- Only one master/parent thread is allowed, and it cannot be |
||||
stopped or deleted. Any given thread is NOT allowed to stop or |
||||
delete itself. |
||||
|
||||
- There NOT enough safety checks as are probably in the other |
||||
threads implementations. |
||||
|
||||
- There is no parent-child relationship between threads. Only one |
||||
thread may thread_join, preferably the master/parent thread. |
||||
|
||||
(C) 2003 Arun Dharankar <ADharankar@ATTBI.Com> |
||||
@ -0,0 +1,391 @@ |
||||
/* The dpalloc function used and implemented in this file was derieved
|
||||
* from PPCBoot/U-Boot file "cpu/mpc8260/commproc.c". |
||||
*/ |
||||
|
||||
/* Author: Arun Dharankar <ADharankar@ATTBI.Com>
|
||||
* This example is meant to only demonstrate how the IDMA could be used. |
||||
*/ |
||||
|
||||
/*
|
||||
* This file is based on "arch/ppc/8260_io/commproc.c" - here is it's |
||||
* copyright notice: |
||||
* |
||||
* General Purpose functions for the global management of the |
||||
* 8260 Communication Processor Module. |
||||
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net) |
||||
* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com) |
||||
* 2.3.99 Updates |
||||
* |
||||
* In addition to the individual control of the communication |
||||
* channels, there are a few functions that globally affect the |
||||
* communication processor. |
||||
* |
||||
* Buffer descriptors must be allocated from the dual ported memory |
||||
* space. The allocator for that is here. When the communication |
||||
* process is reset, we reclaim the memory available. There is |
||||
* currently no deallocator for this memory. |
||||
*/ |
||||
|
||||
|
||||
|
||||
#include <common.h> |
||||
#include <syscall.h> |
||||
|
||||
#define STANDALONE |
||||
|
||||
#ifndef STANDALONE /* Linked into/Part of PPCBoot */ |
||||
#include <command.h> |
||||
#include <watchdog.h> |
||||
#else /* Standalone app of PPCBoot */ |
||||
#include <syscall.h> |
||||
#define printf mon_printf |
||||
#define tstc mon_tstc |
||||
#define getc mon_getc |
||||
#define putc mon_putc |
||||
#define udelay mon_udelay |
||||
#define malloc mon_malloc |
||||
#define WATCHDOG_RESET() { \ |
||||
*(ushort *)(CFG_IMMR + 0x1000E) = 0x556c; \
|
||||
*(ushort *)(CFG_IMMR + 0x1000E) = 0xaa39; \
|
||||
} |
||||
#endif /* STANDALONE */ |
||||
|
||||
static int debug = 1; |
||||
|
||||
#define DEBUG(fmt, args...) { \ |
||||
if(debug != 0) { \
|
||||
printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__); \
|
||||
printf(fmt, ##args); \
|
||||
} \
|
||||
} |
||||
|
||||
#define CPM_CR_IDMA1_SBLOCK (0x14) |
||||
#define CPM_CR_IDMA2_SBLOCK (0x15) |
||||
#define CPM_CR_IDMA3_SBLOCK (0x16) |
||||
#define CPM_CR_IDMA4_SBLOCK (0x17) |
||||
#define CPM_CR_IDMA1_PAGE (0x07) |
||||
#define CPM_CR_IDMA2_PAGE (0x08) |
||||
#define CPM_CR_IDMA3_PAGE (0x09) |
||||
#define CPM_CR_IDMA4_PAGE (0x0a) |
||||
#define PROFF_IDMA1_BASE ((uint)0x87fe) |
||||
#define PROFF_IDMA2_BASE ((uint)0x88fe) |
||||
#define PROFF_IDMA3_BASE ((uint)0x89fe) |
||||
#define PROFF_IDMA4_BASE ((uint)0x8afe) |
||||
|
||||
#define CPM_CR_INIT_TRX ((ushort)0x0000) |
||||
#define CPM_CR_FLG ((ushort)0x0001) |
||||
|
||||
#define mk_cr_cmd(PG, SBC, MCN, OP) \ |
||||
((PG << 26) | (SBC << 21) | (MCN << 6) | OP) |
||||
|
||||
|
||||
#pragma pack(1) |
||||
typedef struct ibdbits { |
||||
unsigned b_valid:1; |
||||
unsigned b_resv1:1; |
||||
unsigned b_wrap:1; |
||||
unsigned b_interrupt:1; |
||||
unsigned b_last:1; |
||||
unsigned b_resv2:1; |
||||
unsigned b_cm:1; |
||||
unsigned b_resv3:2; |
||||
unsigned b_sdn:1; |
||||
unsigned b_ddn:1; |
||||
unsigned b_dgbl:1; |
||||
unsigned b_dbo:2; |
||||
unsigned b_resv4:1; |
||||
unsigned b_ddtb:1; |
||||
unsigned b_resv5:2; |
||||
unsigned b_sgbl:1; |
||||
unsigned b_sbo:2; |
||||
unsigned b_resv6:1; |
||||
unsigned b_sdtb:1; |
||||
unsigned b_resv7:9; |
||||
} ibdbits_t; |
||||
|
||||
#pragma pack(1) |
||||
typedef union ibdbitsu { |
||||
ibdbits_t b; |
||||
uint i; |
||||
} ibdbitsu_t; |
||||
|
||||
#pragma pack(1) |
||||
typedef struct idma_buf_desc { |
||||
ibdbitsu_t ibd_bits; /* Status and Control */ |
||||
uint ibd_datlen; /* Data length in buffer */ |
||||
uint ibd_sbuf; /* Source buffer addr in host mem */ |
||||
uint ibd_dbuf; /* Destination buffer addr in host mem */ |
||||
} ibd_t; |
||||
|
||||
|
||||
#pragma pack(1) |
||||
typedef struct dcmbits { |
||||
unsigned b_fb:1; |
||||
unsigned b_lp:1; |
||||
unsigned b_resv1:3; |
||||
unsigned b_tc2:1; |
||||
unsigned b_resv2:1; |
||||
unsigned b_wrap:3; |
||||
unsigned b_sinc:1; |
||||
unsigned b_dinc:1; |
||||
unsigned b_erm:1; |
||||
unsigned b_dt:1; |
||||
unsigned b_sd:2; |
||||
} dcmbits_t; |
||||
|
||||
#pragma pack(1) |
||||
typedef union dcmbitsu { |
||||
dcmbits_t b; |
||||
ushort i; |
||||
} dcmbitsu_t; |
||||
|
||||
#pragma pack(1) |
||||
typedef struct pram_idma { |
||||
ushort pi_ibase; |
||||
dcmbitsu_t pi_dcmbits; |
||||
ushort pi_ibdptr; |
||||
ushort pi_dprbuf; |
||||
ushort pi_bufinv; /* internal to CPM */ |
||||
ushort pi_ssmax; |
||||
ushort pi_dprinptr; /* internal to CPM */ |
||||
ushort pi_sts; |
||||
ushort pi_dproutptr; /* internal to CPM */ |
||||
ushort pi_seob; |
||||
ushort pi_deob; |
||||
ushort pi_dts; |
||||
ushort pi_retadd; |
||||
ushort pi_resv1; /* internal to CPM */ |
||||
uint pi_bdcnt; |
||||
uint pi_sptr; |
||||
uint pi_dptr; |
||||
uint pi_istate; |
||||
} pram_idma_t; |
||||
|
||||
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile ibd_t *bdf; |
||||
volatile pram_idma_t *piptr; |
||||
|
||||
volatile int dmadone; |
||||
volatile int *dmadonep = &dmadone; |
||||
void dmadone_handler (void *); |
||||
|
||||
int idma_init (void); |
||||
void idma_start (int, int, int, uint, uint, int); |
||||
uint dpalloc (uint, uint); |
||||
|
||||
|
||||
uint dpinit_done = 0; |
||||
|
||||
|
||||
#ifdef STANDALONE |
||||
int ctrlc (void) |
||||
{ |
||||
if (mon_tstc()) { |
||||
switch (mon_getc ()) { |
||||
case 0x03: /* ^C - Control C */ |
||||
return 1; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
void * memset(void * s,int c,size_t count) |
||||
{ |
||||
char *xs = (char *) s; |
||||
while (count--) |
||||
*xs++ = c; |
||||
return s; |
||||
} |
||||
int memcmp(const void * cs,const void * ct,size_t count) |
||||
{ |
||||
const unsigned char *su1, *su2; |
||||
int res = 0; |
||||
for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) |
||||
if ((res = *su1 - *su2) != 0) |
||||
break; |
||||
return res; |
||||
} |
||||
#endif /* STANDALONE */ |
||||
|
||||
#ifdef STANDALONE |
||||
int mem_to_mem_idma2intr (bd_t * bd, int argc, char *argv[]) |
||||
#else |
||||
int do_idma (bd_t * bd, int argc, char *argv[]) |
||||
#endif /* STANDALONE */ |
||||
{ |
||||
int i; |
||||
|
||||
dpinit_done = 0; |
||||
|
||||
idma_init (); |
||||
|
||||
DEBUG ("Installing dma handler\n"); |
||||
mon_install_hdlr (7, dmadone_handler, (void *) bdf); |
||||
|
||||
memset ((void *) 0x100000, 'a', 512); |
||||
memset ((void *) 0x200000, 'b', 512); |
||||
|
||||
for (i = 0; i < 32; i++) { |
||||
printf ("Startin IDMA, iteration=%d\n", i); |
||||
idma_start (1, 1, 512, 0x100000, 0x200000, 3); |
||||
} |
||||
|
||||
DEBUG ("Uninstalling dma handler\n"); |
||||
mon_free_hdlr (7); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void |
||||
idma_start (int sinc, int dinc, int sz, uint sbuf, uint dbuf, int ttype) |
||||
{ |
||||
/* ttype is for M-M, M-P, P-M or P-P: not used for now */ |
||||
|
||||
piptr->pi_istate = 0; /* manual says: clear it before every START_IDMA */ |
||||
piptr->pi_dcmbits.b.b_resv1 = 0; |
||||
|
||||
if (sinc == 1) |
||||
piptr->pi_dcmbits.b.b_sinc = 1; |
||||
else |
||||
piptr->pi_dcmbits.b.b_sinc = 0; |
||||
|
||||
if (dinc == 1) |
||||
piptr->pi_dcmbits.b.b_dinc = 1; |
||||
else |
||||
piptr->pi_dcmbits.b.b_dinc = 0; |
||||
|
||||
piptr->pi_dcmbits.b.b_erm = 0; |
||||
piptr->pi_dcmbits.b.b_sd = 0x00; /* M-M */ |
||||
|
||||
bdf->ibd_sbuf = sbuf; |
||||
bdf->ibd_dbuf = dbuf; |
||||
bdf->ibd_bits.b.b_cm = 0; |
||||
bdf->ibd_bits.b.b_interrupt = 1; |
||||
bdf->ibd_bits.b.b_wrap = 1; |
||||
bdf->ibd_bits.b.b_last = 1; |
||||
bdf->ibd_bits.b.b_sdn = 0; |
||||
bdf->ibd_bits.b.b_ddn = 0; |
||||
bdf->ibd_bits.b.b_dgbl = 0; |
||||
bdf->ibd_bits.b.b_ddtb = 0; |
||||
bdf->ibd_bits.b.b_sgbl = 0; |
||||
bdf->ibd_bits.b.b_sdtb = 0; |
||||
bdf->ibd_bits.b.b_dbo = 1; |
||||
bdf->ibd_bits.b.b_sbo = 1; |
||||
bdf->ibd_bits.b.b_valid = 1; |
||||
bdf->ibd_datlen = 512; |
||||
|
||||
*dmadonep = 0; |
||||
|
||||
immap->im_sdma.sdma_idmr2 = (uchar) 0xf; |
||||
|
||||
immap->im_cpm.cp_cpcr = mk_cr_cmd (CPM_CR_IDMA2_PAGE, |
||||
CPM_CR_IDMA2_SBLOCK, 0x0, |
||||
0x9) | 0x00010000; |
||||
|
||||
while (*dmadonep != 1) { |
||||
if (ctrlc ()) { |
||||
DEBUG ("\nInterrupted waiting for DMA interrupt.\n"); |
||||
goto done; |
||||
} |
||||
printf ("Waiting for DMA interrupt (dmadone=%d b_valid = %d)...\n", |
||||
dmadone, bdf->ibd_bits.b.b_valid); |
||||
udelay (1000000); |
||||
} |
||||
printf ("DMA complete notification received!\n"); |
||||
|
||||
done: |
||||
DEBUG ("memcmp(0x%08x, 0x%08x, 512) = %d\n", |
||||
sbuf, dbuf, memcmp ((void *) sbuf, (void *) dbuf, 512)); |
||||
|
||||
return; |
||||
} |
||||
|
||||
#define MAX_INT_BUFSZ 64 |
||||
#define DCM_WRAP 0 /* MUST be consistant with MAX_INT_BUFSZ */ |
||||
|
||||
int idma_init (void) |
||||
{ |
||||
uint memaddr; |
||||
|
||||
immap->im_cpm.cp_rccr &= ~0x00F3FFFF; |
||||
immap->im_cpm.cp_rccr |= 0x00A00A00; |
||||
|
||||
memaddr = dpalloc (sizeof (pram_idma_t), 64); |
||||
|
||||
*(volatile ushort *) &immap->im_dprambase[PROFF_IDMA2_BASE] = memaddr; |
||||
piptr = (volatile pram_idma_t *) ((uint) (immap) + memaddr); |
||||
|
||||
piptr->pi_resv1 = 0; /* manual says: clear it */ |
||||
piptr->pi_dcmbits.b.b_fb = 0; |
||||
piptr->pi_dcmbits.b.b_lp = 1; |
||||
piptr->pi_dcmbits.b.b_erm = 0; |
||||
piptr->pi_dcmbits.b.b_dt = 0; |
||||
|
||||
memaddr = (uint) dpalloc (sizeof (ibd_t), 64); |
||||
piptr->pi_ibase = piptr->pi_ibdptr = (volatile short) memaddr; |
||||
bdf = (volatile ibd_t *) ((uint) (immap) + memaddr); |
||||
bdf->ibd_bits.b.b_valid = 0; |
||||
|
||||
memaddr = (uint) dpalloc (64, 64); |
||||
piptr->pi_dprbuf = (volatile ushort) memaddr; |
||||
piptr->pi_dcmbits.b.b_wrap = 4; |
||||
piptr->pi_ssmax = 32; |
||||
|
||||
piptr->pi_sts = piptr->pi_ssmax; |
||||
piptr->pi_dts = piptr->pi_ssmax; |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
void dmadone_handler (void *arg) |
||||
{ |
||||
immap->im_sdma.sdma_idmr2 = (uchar) 0x0; |
||||
|
||||
*dmadonep = 1; |
||||
|
||||
return; |
||||
} |
||||
|
||||
|
||||
static uint dpbase = 0; |
||||
|
||||
uint dpalloc (uint size, uint align) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
volatile immap_t *immr = (immap_t *) CFG_IMMR; |
||||
uint retloc; |
||||
uint align_mask, off; |
||||
uint savebase; |
||||
|
||||
/* Pointer to initial global data area */ |
||||
|
||||
if (dpinit_done == 0) { |
||||
dpbase = gd->dp_alloc_base; |
||||
dpinit_done = 1; |
||||
} |
||||
|
||||
align_mask = align - 1; |
||||
savebase = dpbase; |
||||
|
||||
if ((off = (dpbase & align_mask)) != 0) |
||||
dpbase += (align - off); |
||||
|
||||
if ((off = size & align_mask) != 0) |
||||
size += align - off; |
||||
|
||||
if ((dpbase + size) >= gd->dp_alloc_top) { |
||||
dpbase = savebase; |
||||
printf ("dpalloc: ran out of dual port ram!"); |
||||
return 0; |
||||
} |
||||
|
||||
retloc = dpbase; |
||||
dpbase += size; |
||||
|
||||
memset ((void *) &immr->im_dprambase[retloc], 0, size); |
||||
|
||||
return (retloc); |
||||
} |
||||
@ -0,0 +1,188 @@ |
||||
/*
|
||||
* Copyright (C) 2003 ETC s.r.o. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Written by Peter Figuli <peposh@etc.sk>, 2003. |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#define CONFIG_PXA250 1 /* this is an PXA250 CPU */ |
||||
#define CONFIG_WEPEP250 1 /* config for wepep250 board */ |
||||
#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ |
||||
|
||||
|
||||
/*
|
||||
* Select serial console configuration |
||||
*/ |
||||
#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
|
||||
/*
|
||||
* Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if |
||||
* neccessary in include/cmd_confdefs.h file. (Un)comment for getting |
||||
* functionality or size of u-boot code. |
||||
*/ |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
& ~CFG_CMD_NET \
|
||||
& ~CFG_CMD_LOADS \
|
||||
& ~CFG_CMD_CONSOLE \
|
||||
& ~CFG_CMD_AUTOSCRIPT \
|
||||
/* | CFG_CMD_JFFS2 */ \
|
||||
) |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Boot options. Setting delay to -1 stops autostart count down. |
||||
* NOTE: Sending parameters to kernel depends on kernel version and |
||||
* 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
|
||||
* parameters at all! Do not get confused by them so. |
||||
*/ |
||||
#define CONFIG_BOOTDELAY -1 |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8" |
||||
#define CONFIG_BOOTCOMMAND "bootm 40000" |
||||
|
||||
|
||||
/*
|
||||
* General options for u-boot. Modify to save memory foot print |
||||
*/ |
||||
#define CFG_LONGHELP /* undef saves memory */ |
||||
#define CFG_PROMPT "WEP> " /* prompt string */ |
||||
#define CFG_CBSIZE 256 /* console I/O buffer */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ |
||||
#define CFG_MAXARGS 16 /* max command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ |
||||
|
||||
#define CFG_MEMTEST_START 0xa0400000 /* memtest test area */ |
||||
#define CFG_MEMTEST_END 0xa0800000 |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ |
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ |
||||
#define CFG_CPUSPEED 0x141 /* core clock - register value */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Definitions related to passing arguments to kernel. |
||||
*/ |
||||
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ |
||||
#undef CONFIG_INITRD_TAG /* do not send initrd params */ |
||||
#undef CONFIG_VFD /* do not send framebuffer setup */ |
||||
|
||||
|
||||
/*
|
||||
* Malloc pool need to host env + 128 Kb reserve for other allocations. |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) |
||||
|
||||
#define CONFIG_STACKSIZE (120<<10) /* stack size */ |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*
|
||||
* SDRAM Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ |
||||
#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */ |
||||
#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */ |
||||
#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */ |
||||
#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */ |
||||
#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */ |
||||
#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */ |
||||
#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */ |
||||
#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */ |
||||
|
||||
#define CFG_DRAM_BASE 0xa0000000 |
||||
#define CFG_DRAM_SIZE 0x02000000 |
||||
|
||||
/* Uncomment used SDRAM chip */ |
||||
#define WEP_SDRAM_K4S281633 |
||||
/*#define WEP_SDRAM_K4S561633*/ |
||||
|
||||
|
||||
/*
|
||||
* Configuration for FLASH memory |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ |
||||
#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ |
||||
#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ |
||||
#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */ |
||||
#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/ |
||||
#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */ |
||||
#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */ |
||||
#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */ |
||||
|
||||
|
||||
/* This should be defined if CFI FLASH device is present. Actually benefit
|
||||
is not so clear to me. In other words we can provide more informations |
||||
to user, but this expects more complex flash handling we do not provide
|
||||
now.*/ |
||||
#undef CFG_FLASH_CFI |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ |
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ |
||||
|
||||
#define CFG_FLASH_BASE WEP_FLASH_BASE |
||||
|
||||
/*
|
||||
* This is setting for JFFS2 support in u-boot. |
||||
* Right now there is no gain for user, but later on booting kernel might be |
||||
* possible. Consider using XIP kernel running from flash to save RAM |
||||
* footprint. |
||||
* NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. |
||||
*/ |
||||
#define CFG_JFFS2_FIRST_BANK 0 |
||||
#define CFG_JFFS2_FIRST_SECTOR 5 |
||||
#define CFG_JFFS2_NUM_BANKS 1 |
||||
|
||||
/*
|
||||
* Environment setup. Definitions of monitor location and size with |
||||
* definition of environment setup ends up in 2 possibilities. |
||||
* 1. Embeded environment - in u-boot code is space for environment |
||||
* 2. Environment is read from predefined sector of flash |
||||
* Right now we support 2. possiblity, but expecting no env placed |
||||
* on mentioned address right now. This also needs to provide whole |
||||
* sector for it - for us 256Kb is really waste of memory. U-boot uses |
||||
* default env. and until kernel parameters could be sent to kernel |
||||
* env. has no sense to us. |
||||
*/ |
||||
|
||||
#define CFG_MONITOR_BASE PHYS_FLASH_1 |
||||
#define CFG_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR 0x20000 /* absolute address for now */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
|
||||
#undef CONFIG_ENV_OVERWRITE /* env is not writable now */ |
||||
|
||||
/*
|
||||
* Well this has to be defined, but on the other hand it is used differently |
||||
* one may expect. For instance loadb command do not cares :-) |
||||
* So advice is - do not relay on this... |
||||
*/ |
||||
#define CFG_LOAD_ADDR 0x40000 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
|
||||
@ -0,0 +1,38 @@ |
||||
#include <stdio.h> |
||||
#include <stdlib.h> |
||||
#include <string.h> |
||||
#include <unistd.h> |
||||
|
||||
#ifndef BUFSIZ |
||||
# define BUFSIZ 4096 |
||||
#endif |
||||
|
||||
#undef BUFSIZ |
||||
# define BUFSIZ 64 |
||||
int main (void) |
||||
{ |
||||
short ibuff[BUFSIZ], obuff[BUFSIZ]; |
||||
int rc, i, len; |
||||
|
||||
while ((rc = read (0, ibuff, sizeof (ibuff))) > 0) { |
||||
memset (obuff, 0, sizeof (obuff)); |
||||
for (i = 0; i < (rc + 1) / 2; i++) { |
||||
obuff[i] = ibuff[i ^ 1]; |
||||
} |
||||
|
||||
len = (rc + 1) & ~1; |
||||
|
||||
if (write (1, obuff, len) != len) { |
||||
perror ("read error"); |
||||
return (EXIT_FAILURE); |
||||
} |
||||
|
||||
memset (ibuff, 0, sizeof (ibuff)); |
||||
} |
||||
|
||||
if (rc < 0) { |
||||
perror ("read error"); |
||||
return (EXIT_FAILURE); |
||||
} |
||||
return (EXIT_SUCCESS); |
||||
} |
||||
Loading…
Reference in new issue