Wolfgang Denk
15 years ago
commit
3e3989619f
@ -0,0 +1,90 @@ |
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/*
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* CF IDE addon card code |
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* |
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* Enter bugs at http://blackfin.uclinux.org/
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* |
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* Copyright (c) 2005-2009 Analog Devices Inc. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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#include <common.h> |
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#include <config.h> |
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#include <asm/blackfin.h> |
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#include "bf533-stamp.h" |
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void cf_outb(unsigned char val, volatile unsigned char *addr) |
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{ |
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/* "ETHERNET" means the expansion memory banks */ |
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swap_to(ETHERNET); |
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*addr = val; |
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SSYNC(); |
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swap_to(FLASH); |
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} |
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unsigned char cf_inb(volatile unsigned char *addr) |
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{ |
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unsigned char c; |
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swap_to(ETHERNET); |
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c = *addr; |
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SSYNC(); |
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swap_to(FLASH); |
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return c; |
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} |
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void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words) |
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{ |
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int i; |
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swap_to(ETHERNET); |
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for (i = 0; i < words; i++) { |
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*(sect_buf + i) = *addr; |
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SSYNC(); |
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} |
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swap_to(FLASH); |
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} |
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void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) |
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{ |
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int i; |
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swap_to(ETHERNET); |
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for (i = 0; i < words; i++) { |
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*addr = *(sect_buf + i); |
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SSYNC(); |
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} |
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swap_to(FLASH); |
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} |
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void cf_ide_init(void) |
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{ |
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int i, cf_stat; |
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/* Check whether CF card is inserted */ |
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bfin_write_FIO_EDGE(FIO_EDGE_CF_BITS); |
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bfin_write_FIO_POLAR(FIO_POLAR_CF_BITS); |
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for (i = 0; i < 0x300; i++) |
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asm volatile("nop;"); |
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cf_stat = bfin_read_FIO_FLAG_S() & CF_STAT_BITS; |
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bfin_write_FIO_EDGE(FIO_EDGE_BITS); |
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bfin_write_FIO_POLAR(FIO_POLAR_BITS); |
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if (!cf_stat) { |
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for (i = 0; i < 0x3000; i++) |
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asm volatile("nop;"); |
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ide_init(); |
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} |
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} |
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@ -0,0 +1,56 @@ |
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2007 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2009 CJSC "NII STT", Russia, Smolensk
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,51 @@ |
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/*
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* File: board/bf561-acvilon/bf561-acvilon.c |
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* Based on: board/bf561-ezkit/bf561-ezkit.c |
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* Author: |
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* |
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* Created: 2009-06-23 |
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* Description: Acvilon System On Module board file |
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* |
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* Modified: |
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* Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
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* Copyright (c) 2005-2008 Analog Devices Inc. |
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* |
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* (C) Copyright 2000-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Bugs: |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, see the file COPYING, or write |
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* to the Free Software Foundation, Inc., |
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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printf("Board: CJSC \"NII STT\"-=Acvilon Platform=- [U-Boot]\n"); |
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printf(" Support: http://www.niistt.ru/\n"); |
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return 0; |
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} |
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#ifdef CONFIG_SMC911X |
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int board_eth_init(bd_t *bis) |
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{ |
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return smc911x_initialize(0, CONFIG_SMC911X_BASE); |
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} |
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#endif |
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@ -0,0 +1,34 @@ |
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# This is not actually used for Blackfin boards so do not change it
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#TEXT_BASE = do-not-use-me
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CFLAGS_lib_generic += -O2
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CFLAGS_lzma += -O2
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# Set some default LDR flags based on boot mode.
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LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
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LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
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@ -0,0 +1,54 @@ |
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
|
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS-y := $(BOARD).o
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|
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SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS-y))
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|
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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|
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clean: |
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rm -f $(SOBJS) $(OBJS)
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|
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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|
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,33 @@ |
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#
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# Copyright (c) 2005-2008 Analog Device Inc.
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#
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
|
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# project.
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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|
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# This is not actually used for Blackfin boards so do not change it
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#TEXT_BASE = do-not-use-me
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CFLAGS_lib_generic += -O2
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CFLAGS_lzma += -O2
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|
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# Set some default LDR flags based on boot mode.
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LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
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@ -0,0 +1,78 @@ |
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/*
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* U-boot - main board file |
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* |
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* Copyright (c) 2008-2009 Analog Devices Inc. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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#include <common.h> |
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#include <config.h> |
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#include <net.h> |
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#include <netdev.h> |
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#include <asm/blackfin.h> |
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#include <asm/net.h> |
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#include <asm/mach-common/bits/otp.h> |
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#include <asm/sdh.h> |
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int checkboard(void) |
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{ |
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printf("Board: Bluetechnix TCM-BF518 board\n"); |
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printf(" Support: http://www.bluetechnix.com/\n"); |
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printf(" http://blackfin.uclinux.org/\n"); |
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return 0; |
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} |
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|
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#if defined(CONFIG_BFIN_MAC) |
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static void board_init_enetaddr(uchar *mac_addr) |
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{ |
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bool valid_mac = false; |
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#if 0 |
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/* the MAC is stored in OTP memory page 0xDF */ |
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uint32_t ret; |
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uint64_t otp_mac; |
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ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac); |
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if (!(ret & OTP_MASTER_ERROR)) { |
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uchar *otp_mac_p = (uchar *)&otp_mac; |
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for (ret = 0; ret < 6; ++ret) |
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mac_addr[ret] = otp_mac_p[5 - ret]; |
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if (is_valid_ether_addr(mac_addr)) |
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valid_mac = true; |
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} |
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#endif |
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if (!valid_mac) { |
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puts("Warning: Generating 'random' MAC address\n"); |
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bfin_gen_rand_mac(mac_addr); |
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} |
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eth_setenv_enetaddr("ethaddr", mac_addr); |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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return bfin_EMAC_initialize(bis); |
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} |
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#endif |
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|
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int misc_init_r(void) |
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{ |
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#ifdef CONFIG_BFIN_MAC |
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uchar enetaddr[6]; |
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if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
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board_init_enetaddr(enetaddr); |
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#endif |
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|
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return 0; |
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} |
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|
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#ifdef CONFIG_BFIN_SDH |
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int board_mmc_init(bd_t *bis) |
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{ |
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return bfin_mmc_init(bis); |
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} |
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#endif |
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@ -1,59 +0,0 @@ |
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/*
|
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* Copyright (C) 2008 Analog Device Inc. |
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* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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#ifndef __BLACKFIN_SDH_H__ |
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#define __BLACKFIN_SDH_H__ |
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|
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#define MMC_RSP_PRESENT (1 << 0) |
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#define MMC_RSP_136 (1 << 1) /* 136 bit response */ |
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#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ |
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#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ |
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#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ |
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|
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#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */ |
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#define MMC_CMD_AC (0 << 5) |
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#define MMC_CMD_ADTC (1 << 5) |
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#define MMC_CMD_BC (2 << 5) |
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#define MMC_CMD_BCR (3 << 5) |
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|
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#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */ |
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#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */ |
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#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */ |
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#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */ |
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|
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/*
|
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* These are the native response types, and correspond to valid bit |
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* patterns of the above flags. One additional valid pattern |
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* is all zeros, which means we don't expect a response. |
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*/ |
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#define MMC_RSP_NONE (0) |
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#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
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#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) |
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#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) |
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#define MMC_RSP_R3 (MMC_RSP_PRESENT) |
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#define MMC_RSP_R4 (MMC_RSP_PRESENT) |
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#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
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#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
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#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) |
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#define ILLEGAL_COMMAND (1 << 22) |
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#define APP_CMD (1 << 5) |
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|
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#endif |
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File diff suppressed because it is too large
Load Diff
@ -1 +1,2 @@ |
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#include "mem_map.h" |
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#include "ports.h" |
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|
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@ -0,0 +1,21 @@ |
||||
/*
|
||||
* Common Blackfin memory map |
||||
* |
||||
* Copyright 2004-2009 Analog Devices Inc. |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#ifndef __BF52X_MEM_MAP_H__ |
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#define __BF52X_MEM_MAP_H__ |
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|
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#define L1_DATA_A_SRAM (0xFF800000) |
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#define L1_DATA_A_SRAM_SIZE (0x4000) |
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#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) |
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#define L1_DATA_B_SRAM (0xFF900000) |
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#define L1_DATA_B_SRAM_SIZE (0x4000) |
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#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) |
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#define L1_INST_SRAM (0xFFA00000) |
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#define L1_INST_SRAM_SIZE (0xC000) |
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#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) |
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|
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#endif |
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@ -1 +1,2 @@ |
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#include "mem_map.h" |
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#include "ports.h" |
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|
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@ -0,0 +1,21 @@ |
||||
/*
|
||||
* Common Blackfin memory map |
||||
* |
||||
* Copyright 2004-2009 Analog Devices Inc. |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#ifndef __BF54X_MEM_MAP_H__ |
||||
#define __BF54X_MEM_MAP_H__ |
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|
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#define L1_DATA_A_SRAM (0xFF800000) |
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#define L1_DATA_A_SRAM_SIZE (0x4000) |
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#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) |
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#define L1_DATA_B_SRAM (0xFF900000) |
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#define L1_DATA_B_SRAM_SIZE (0x4000) |
||||
#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) |
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#define L1_INST_SRAM (0xFFA00000) |
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#define L1_INST_SRAM_SIZE (0xC000) |
||||
#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) |
||||
|
||||
#endif |
||||
@ -0,0 +1,26 @@ |
||||
/*
|
||||
* Common Blackfin memory map |
||||
* |
||||
* Copyright 2004-2009 Analog Devices Inc. |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#ifndef __BFIN_MEM_MAP_H__ |
||||
#define __BFIN_MEM_MAP_H__ |
||||
|
||||
/* Every Blackfin so far has MMRs like this */ |
||||
#ifndef COREMMR_BASE |
||||
# define COREMMR_BASE 0xFFE00000 |
||||
#endif |
||||
#ifndef SYSMMR_BASE |
||||
# define SYSMMR_BASE 0xFFC00000 |
||||
#endif |
||||
|
||||
/* Every Blackfin so far has on-chip Scratch Pad SRAM like this */ |
||||
#ifndef L1_SRAM_SCRATCH |
||||
# define L1_SRAM_SCRATCH 0xFFB00000 |
||||
# define L1_SRAM_SCRATCH_SIZE 0x1000 |
||||
# define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) |
||||
#endif |
||||
|
||||
#endif |
||||
@ -1 +0,0 @@ |
||||
#include <asm-avr32/arch-at32ap700x/mmc.h> |
||||
@ -0,0 +1,17 @@ |
||||
/*
|
||||
* sdh.h, export bfin_mmc_init |
||||
* |
||||
* Copyright (c) 2009 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#ifndef __ASM_SDH_H__ |
||||
#define __ASM_SDH_H__ |
||||
|
||||
#include <mmc.h> |
||||
#include <asm/u-boot.h> |
||||
|
||||
int bfin_mmc_init(bd_t *bis); |
||||
|
||||
#endif |
||||
@ -0,0 +1,178 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF561 Acvilon System On Module |
||||
* For more information please go to http://www.niistt.ru/
|
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BF561_ACVILON_H__ |
||||
#define __CONFIG_BF561_ACVILON_H__ |
||||
|
||||
#include <asm/config-pre.h> |
||||
|
||||
|
||||
/*
|
||||
* Processor Settings |
||||
*/ |
||||
#define CONFIG_BFIN_CPU bf561-0.5 |
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
||||
|
||||
|
||||
/*
|
||||
* Clock Settings |
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||
*/ |
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 12000000 |
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||
/* 1 = CLKIN / 2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||
/* 1 = bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||
/* Values can range from 0-63 (where 0 means 64) */ |
||||
#define CONFIG_VCO_MULT 50 |
||||
/* CCLK_DIV controls the core clock divider */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* SCLK_DIV controls the system clock divider */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 5 |
||||
|
||||
|
||||
/*
|
||||
* Memory Settings |
||||
*/ |
||||
#define CONFIG_MEM_ADD_WDTH 10 |
||||
#define CONFIG_MEM_SIZE 128 |
||||
|
||||
#define CONFIG_EBIU_SDRRC_VAL 0x300 |
||||
#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189 |
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL 0x4e |
||||
#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2 |
||||
#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554 |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) |
||||
|
||||
|
||||
/*
|
||||
* RTC Settings |
||||
*/ |
||||
#define CONFIG_RTC_DS1337 |
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ |
||||
#define CONFIG_SYS_I2C_DTT_ADDR 0x49 |
||||
/*#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30 |
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3*/ |
||||
|
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
#define ADI_CMDS_NETWORK 1 |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DTT |
||||
|
||||
#if defined(CONFIG_CMD_NET) |
||||
|
||||
#define CONFIG_SMC911X 1 |
||||
#define CONFIG_SMC911X_32_BIT |
||||
/* #define CONFIG_SMC911X_16_BIT */ |
||||
#define CONFIG_SMC911X_BASE 0x28000000 |
||||
|
||||
#endif /* (CONFIG_CMD_NET) */ |
||||
|
||||
#define CONFIG_HOSTNAME bf561-acvilon |
||||
|
||||
/* Uncomment next line to use fixed MAC address */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||
|
||||
|
||||
/*
|
||||
* Flash Settings |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
|
||||
/*
|
||||
* I2C Settings |
||||
*/ |
||||
#define CONFIG_HARD_I2C |
||||
/* Use 300kHz speed by default */ |
||||
#define CONFIG_SYS_I2C_SPEED 0x00 |
||||
#define CONFIG_PCA9564_I2C |
||||
#define CONFIG_PCA9564_BASE 0x2c000000 |
||||
|
||||
|
||||
/*
|
||||
* SPI Settings |
||||
*/ |
||||
#define CONFIG_BFIN_SPI |
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000 |
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000 |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_ATMEL |
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
/* #define CONFIG_CMD_SAVEENV */ |
||||
#define CONFIG_ENV_SECT_SIZE (1056 * 8) |
||||
#define CONFIG_ENV_OFFSET ((16 + 256) * 1056) |
||||
#define CONFIG_ENV_SIZE (8 * 1056) |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
||||
|
||||
|
||||
/*
|
||||
* NAND Settings |
||||
* We're using NAND_PLAT driver to make things simplier |
||||
*/ |
||||
#define CONFIG_NAND_PLAT |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_SYS_NAND_BASE 0x24000000 |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
|
||||
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) |
||||
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3)) |
||||
#define BFIN_NAND_READY PF10 |
||||
#define BFIN_NAND_WRITE(addr, cmd) \ |
||||
do { \
|
||||
bfin_write8(addr, cmd); \
|
||||
SSYNC(); \
|
||||
} while (0) |
||||
|
||||
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) |
||||
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) |
||||
#define NAND_PLAT_DEV_READY(chip) (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY) |
||||
#define NAND_PLAT_INIT() \ |
||||
do { \
|
||||
bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \
|
||||
bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \
|
||||
} while (0) |
||||
|
||||
|
||||
/*
|
||||
* Misc Settings |
||||
*/ |
||||
#define CONFIG_UART_CONSOLE 0 |
||||
#define CONFIG_BAUDRATE 57600 |
||||
#define CONFIG_SYS_PROMPT "Acvilon> " |
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup |
||||
*/ |
||||
#include <configs/bfin_adi_common.h> |
||||
|
||||
#endif /* __CONFIG_BF561_ACVILON_H__ */ |
||||
@ -0,0 +1,129 @@ |
||||
/*
|
||||
* U-boot - Configuration file for Bluetechnix TCM-BF518 board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_TCM_BF518_H__ |
||||
#define __CONFIG_TCM_BF518_H__ |
||||
|
||||
#include <asm/config-pre.h> |
||||
|
||||
|
||||
/*
|
||||
* Processor Settings |
||||
*/ |
||||
#define CONFIG_BFIN_CPU bf518-0.0 |
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
||||
|
||||
|
||||
/*
|
||||
* Clock Settings |
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||
*/ |
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 25000000 |
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||
/* 1 = CLKIN / 2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||
/* 1 = bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||
/* Values can range from 0-63 (where 0 means 64) */ |
||||
#define CONFIG_VCO_MULT 16 |
||||
/* CCLK_DIV controls the core clock divider */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* SCLK_DIV controls the system clock divider */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 4 |
||||
|
||||
|
||||
/*
|
||||
* Memory Settings |
||||
*/ |
||||
/* This board has a 32meg MT48H16M16 */ |
||||
#define CONFIG_MEM_ADD_WDTH 9 |
||||
#define CONFIG_MEM_SIZE 32 |
||||
|
||||
#define CONFIG_EBIU_SDRRC_VAL 0x3f8 |
||||
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd |
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) |
||||
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) |
||||
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (384 * 1024) |
||||
|
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) |
||||
#define ADI_CMDS_NETWORK 1 |
||||
#define CONFIG_BFIN_MAC |
||||
#define CONFIG_NETCONSOLE 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
#define CONFIG_HOSTNAME tcm-bf518 |
||||
/* Uncomment next line to use fixed MAC address */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||
|
||||
|
||||
/*
|
||||
* Flash Settings |
||||
*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000 |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 19 |
||||
|
||||
|
||||
/*
|
||||
* SPI Settings |
||||
*/ |
||||
#define CONFIG_BFIN_SPI |
||||
#define CONFIG_ENV_SPI_MAX_HZ 30000000 |
||||
#define CONFIG_SF_DEFAULT_SPEED 30000000 |
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x8000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x8000 |
||||
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
||||
|
||||
|
||||
/*
|
||||
* I2C Settings |
||||
*/ |
||||
#define CONFIG_BFIN_TWI_I2C 1 |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0 |
||||
|
||||
|
||||
/*
|
||||
* Misc Settings |
||||
*/ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_RTC_BFIN |
||||
#define CONFIG_UART_CONSOLE 0 |
||||
#define CONFIG_BOOTCOMMAND "run flashboot" |
||||
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" |
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup |
||||
*/ |
||||
#include <configs/bfin_adi_common.h> |
||||
|
||||
#endif |
||||
@ -0,0 +1,117 @@ |
||||
/* |
||||
* arch/blackfin/lib/ins.S - ins{bwl} using hardware loops |
||||
* |
||||
* Copyright 2004-2008 Analog Devices Inc. |
||||
* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
|
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <asm/blackfin.h> |
||||
|
||||
.align 2
|
||||
|
||||
#ifdef CONFIG_IPIPE |
||||
# define DO_CLI \ |
||||
[--sp] = rets; \
|
||||
[--sp] = (P5:0); \
|
||||
sp += -12; \
|
||||
call ___ipipe_disable_root_irqs_hw; \
|
||||
sp += 12; \
|
||||
(P5:0) = [sp++];
|
||||
# define CLI_INNER_NOP |
||||
#else |
||||
# define DO_CLI cli R3;
|
||||
# define CLI_INNER_NOP nop; nop; nop;
|
||||
#endif |
||||
|
||||
#ifdef CONFIG_IPIPE |
||||
# define DO_STI \ |
||||
sp += -12; \
|
||||
call ___ipipe_enable_root_irqs_hw; \
|
||||
sp += 12; \
|
||||
2: rets = [sp++];
|
||||
#else |
||||
# define DO_STI 2: sti R3;
|
||||
#endif |
||||
|
||||
#ifdef CONFIG_BFIN_INS_LOWOVERHEAD |
||||
# define CLI_OUTER DO_CLI;
|
||||
# define STI_OUTER DO_STI;
|
||||
# define CLI_INNER 1: |
||||
# if ANOMALY_05000416 |
||||
# define STI_INNER nop; 2: nop;
|
||||
# else |
||||
# define STI_INNER 2: |
||||
# endif |
||||
#else |
||||
# define CLI_OUTER |
||||
# define STI_OUTER |
||||
# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
|
||||
# define STI_INNER DO_STI;
|
||||
#endif |
||||
|
||||
/* |
||||
* Reads on the Blackfin are speculative. In Blackfin terms, this means they |
||||
* can be interrupted at any time (even after they have been issued on to the |
||||
* external bus), and re-issued after the interrupt occurs. |
||||
* |
||||
* If a FIFO is sitting on the end of the read, it will see two reads, |
||||
* when the core only sees one. The FIFO receives the read which is cancelled, |
||||
* and not delivered to the core. |
||||
* |
||||
* To solve this, interrupts are turned off before reads occur to I/O space. |
||||
* There are 3 versions of all these functions |
||||
* - turns interrupts off every read (higher overhead, but lower latency) |
||||
* - turns interrupts off every loop (low overhead, but longer latency) |
||||
* - DMA version, which do not suffer from this issue. DMA versions have |
||||
* different name (prefixed by dma_ ), and are located in |
||||
* ../kernel/bfin_dma_5xx.c |
||||
* Using the dma related functions are recommended for transfering large |
||||
* buffers in/out of FIFOs. |
||||
*/ |
||||
|
||||
#define COMMON_INS(func, ops) \ |
||||
ENTRY(_ins##func) \ |
||||
P0 = R0; /* P0 = port */ \
|
||||
CLI_OUTER; /* 3 instructions before first read access */ \
|
||||
P1 = R1; /* P1 = address */ \
|
||||
P2 = R2; /* P2 = count */ \
|
||||
SSYNC; \
|
||||
\ |
||||
LSETUP(1f, 2f) LC0 = P2; \
|
||||
CLI_INNER; \
|
||||
ops; \
|
||||
STI_INNER; \
|
||||
\ |
||||
STI_OUTER; \
|
||||
RTS; \
|
||||
ENDPROC(_ins##func) |
||||
|
||||
COMMON_INS(l, \ |
||||
R0 = [P0]; \
|
||||
[P1++] = R0; \
|
||||
) |
||||
|
||||
COMMON_INS(w, \ |
||||
R0 = W[P0]; \
|
||||
W[P1++] = R0; \
|
||||
) |
||||
|
||||
COMMON_INS(w_8, \ |
||||
R0 = W[P0]; \
|
||||
B[P1++] = R0; \
|
||||
R0 = R0 >> 8; \
|
||||
B[P1++] = R0; \
|
||||
) |
||||
|
||||
COMMON_INS(b, \ |
||||
R0 = B[P0]; \
|
||||
B[P1++] = R0; \
|
||||
) |
||||
|
||||
COMMON_INS(l_16, \ |
||||
R0 = [P0]; \
|
||||
W[P1++] = R0; \
|
||||
R0 = R0 >> 16; \
|
||||
W[P1++] = R0; \
|
||||
) |
||||
@ -0,0 +1,60 @@ |
||||
/* |
||||
* Implementation of outs{bwl} for BlackFin processors using zero overhead loops. |
||||
* |
||||
* Copyright 2005-2009 Analog Devices Inc. |
||||
* 2005 BuyWays BV |
||||
* Bas Vermeulen <bas@buyways.nl>
|
||||
* |
||||
* Licensed under the GPL-2. |
||||
*/ |
||||
|
||||
#include <asm/linkage.h> |
||||
|
||||
.align 2
|
||||
|
||||
ENTRY(_outsl) |
||||
P0 = R0; /* P0 = port */
|
||||
P1 = R1; /* P1 = address */
|
||||
P2 = R2; /* P2 = count */
|
||||
|
||||
LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
|
||||
.Llong_loop_s: R0 = [P1++];
|
||||
.Llong_loop_e: [P0] = R0;
|
||||
RTS;
|
||||
ENDPROC(_outsl) |
||||
|
||||
ENTRY(_outsw) |
||||
P0 = R0; /* P0 = port */
|
||||
P1 = R1; /* P1 = address */
|
||||
P2 = R2; /* P2 = count */
|
||||
|
||||
LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
|
||||
.Lword_loop_s: R0 = W[P1++];
|
||||
.Lword_loop_e: W[P0] = R0;
|
||||
RTS;
|
||||
ENDPROC(_outsw) |
||||
|
||||
ENTRY(_outsb) |
||||
P0 = R0; /* P0 = port */
|
||||
P1 = R1; /* P1 = address */
|
||||
P2 = R2; /* P2 = count */
|
||||
|
||||
LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
|
||||
.Lbyte_loop_s: R0 = B[P1++];
|
||||
.Lbyte_loop_e: B[P0] = R0;
|
||||
RTS;
|
||||
ENDPROC(_outsb) |
||||
|
||||
ENTRY(_outsw_8) |
||||
P0 = R0; /* P0 = port */
|
||||
P1 = R1; /* P1 = address */
|
||||
P2 = R2; /* P2 = count */
|
||||
|
||||
LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
|
||||
.Lword8_loop_s: R1 = B[P1++];
|
||||
R0 = B[P1++];
|
||||
R0 = R0 << 8;
|
||||
R0 = R0 + R1;
|
||||
.Lword8_loop_e: W[P0] = R0;
|
||||
RTS;
|
||||
ENDPROC(_outsw_8) |
||||
Loading…
Reference in new issue