This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>master
Simon Glass
9 years ago
committed by
Tom Rini
parent
a6f7f78744
commit
3eb8f58d75
@ -1,15 +0,0 @@ |
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if TARGET_IMA3_MX53 |
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config SYS_BOARD |
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default "ima3-mx53" |
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config SYS_VENDOR |
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default "esg" |
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config SYS_SOC |
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default "mx5" |
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config SYS_CONFIG_NAME |
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default "ima3-mx53" |
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endif |
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@ -1,6 +0,0 @@ |
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IMA3-MX53 BOARD |
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#M: - |
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S: Maintained |
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F: board/esg/ima3-mx53/ |
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F: include/configs/ima3-mx53.h |
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F: configs/ima3-mx53_defconfig |
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@ -1,9 +0,0 @@ |
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#
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# Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
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#
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# Based on ti/evm/Makefile
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := ima3-mx53.o
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@ -1,206 +0,0 @@ |
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/*
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* (C) Copyright 2012, Stefano Babic <sbabic@denx.de> |
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* |
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* (C) Copyright 2010 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/imx-regs.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/crm_regs.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/iomux-mx53.h> |
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#include <asm/errno.h> |
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#include <netdev.h> |
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#include <mmc.h> |
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#include <fsl_esdhc.h> |
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#include <asm/gpio.h> |
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/* NOR flash configuration */ |
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#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2)) |
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#define IMA3_MX53_CS0GCR2 0 |
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#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15)) |
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#define IMA3_MX53_CS0RCR2 0 |
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#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15)) |
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#define IMA3_MX53_CS0WCR2 0 |
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DECLARE_GLOBAL_DATA_PTR; |
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static void weim_nor_settings(void) |
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{ |
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struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; |
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writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1); |
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writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2); |
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writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1); |
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writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2); |
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writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1); |
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writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2); |
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writel(0x0, &weim_regs->wcr); |
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set_chipselect_size(CS0_128); |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, |
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PHYS_SDRAM_1_SIZE); |
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return 0; |
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} |
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) |
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static void setup_iomux_uart(void) |
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{ |
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static const iomux_v3_cfg_t uart_pads[] = { |
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT13__UART4_RXD_MUX, UART_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT12__UART4_TXD_MUX, UART_PAD_CTRL), |
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}; |
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); |
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} |
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static void setup_iomux_fec(void) |
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{ |
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static const iomux_v3_cfg_t fec_pads[] = { |
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NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE), |
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NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), |
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NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH), |
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NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH), |
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), |
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), |
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NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), |
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NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK, |
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PAD_CTL_HYS | PAD_CTL_PKE), |
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}; |
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
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} |
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#ifdef CONFIG_FSL_ESDHC |
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struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR }; |
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int board_mmc_getcd(struct mmc *mmc) |
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{ |
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int ret; |
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ret = !gpio_get_value(IMX_GPIO_NR(1, 1)); |
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return ret; |
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} |
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#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ |
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PAD_CTL_PUS_100K_UP) |
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#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ |
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PAD_CTL_DSE_HIGH) |
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#define SD_CD_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | PAD_CTL_PKE) |
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int board_mmc_init(bd_t *bis) |
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{ |
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static const iomux_v3_cfg_t sd1_pads[] = { |
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NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, SD_CD_PAD_CTRL), |
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}; |
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imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads)); |
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gpio_direction_input(IMX_GPIO_NR(1, 1)); |
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esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
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return fsl_esdhc_initialize(bis, &esdhc_cfg); |
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} |
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#endif |
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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP) |
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static void setup_iomux_spi(void) |
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{ |
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static const iomux_v3_cfg_t spi_pads[] = { |
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL), |
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL), |
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/* SSEL 0 */ |
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__GPIO5_29, SPI_PAD_CTRL), |
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}; |
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imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads)); |
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gpio_direction_output(IMX_GPIO_NR(5, 29), 1); |
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} |
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int board_early_init_f(void) |
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{ |
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/* configure I/O pads */ |
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setup_iomux_uart(); |
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setup_iomux_fec(); |
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weim_nor_settings(); |
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/* configure spi */ |
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setup_iomux_spi(); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
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mxc_set_sata_internal_clock(); |
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return 0; |
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} |
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#if defined(CONFIG_RESET_PHY_R) |
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#include <miiphy.h> |
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void reset_phy(void) |
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{ |
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unsigned short reg; |
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/* reset the phy */ |
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miiphy_reset("FEC", CONFIG_PHY_ADDR); |
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/* set hard link to 100Mbit, full-duplex */ |
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miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®); |
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reg &= ~BMCR_ANENABLE; |
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reg |= (BMCR_SPEED100 | BMCR_FULLDPLX); |
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miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg); |
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miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®); |
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reg |= (1 << 5); |
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miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg); |
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} |
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#endif |
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int checkboard(void) |
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{ |
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puts("Board: IMA3_MX53\n"); |
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return 0; |
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} |
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@ -1,104 +0,0 @@ |
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/* |
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* (C) Copyright 2012 |
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* Stefano Babic DENX Software Engineering sbabic@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Refer doc/README.imximage for more details about how-to configure |
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* and create imximage boot image |
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* |
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* The syntax is taken as close as possible with the kwbimage |
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*/ |
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/* image version */ |
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IMAGE_VERSION 2 |
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/* |
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* Boot Device : one of |
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* spi, sd (the board has no nand neither onenand) |
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*/ |
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BOOT_FROM nor |
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/* |
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* Device Configuration Data (DCD) |
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* |
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* Each entry must have the format: |
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* Addr-type Address Value |
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* |
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* where: |
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* Addr-type register length (1,2 or 4 bytes) |
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* Address absolute address of the register |
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* value value to be stored in the register |
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*/ |
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/* IOMUX for RAM only */ |
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DATA 4 0x53fa8554 0x300020 |
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DATA 4 0x53fa8560 0x300020 |
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DATA 4 0x53fa8594 0x300020 |
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DATA 4 0x53fa8584 0x300020 |
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DATA 4 0x53fa8558 0x300040 |
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DATA 4 0x53fa8568 0x300040 |
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DATA 4 0x53fa8590 0x300040 |
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DATA 4 0x53fa857c 0x300040 |
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DATA 4 0x53fa8564 0x300040 |
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DATA 4 0x53fa8580 0x300040 |
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DATA 4 0x53fa8570 0x300220 |
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DATA 4 0x53fa8578 0x300220 |
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DATA 4 0x53fa872c 0x300000 |
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DATA 4 0x53fa8728 0x300000 |
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DATA 4 0x53fa871c 0x300000 |
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DATA 4 0x53fa8718 0x300000 |
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DATA 4 0x53fa8574 0x300020 |
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DATA 4 0x53fa8588 0x300020 |
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DATA 4 0x53fa855c 0x0 |
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DATA 4 0x53fa858c 0x0 |
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DATA 4 0x53fa856c 0x300040 |
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DATA 4 0x53fa86f0 0x300000 |
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DATA 4 0x53fa8720 0x300000 |
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DATA 4 0x53fa86fc 0x0 |
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DATA 4 0x53fa86f4 0x0 |
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DATA 4 0x53fa8714 0x0 |
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DATA 4 0x53fa8724 0x4000000 |
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/* DDR RAM */ |
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DATA 4 0x63fd9088 0x40404040 |
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DATA 4 0x63fd9090 0x40404040 |
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DATA 4 0x63fd907C 0x01420143 |
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DATA 4 0x63fd9080 0x01450146 |
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DATA 4 0x63fd9018 0x00111740 |
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DATA 4 0x63fd9000 0x84190000 |
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/* esdcfgX */ |
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DATA 4 0x63fd900C 0x9f5152e3 |
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DATA 4 0x63fd9010 0xb68e8a63 |
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DATA 4 0x63fd9014 0x01ff00db |
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/* Read/Write command delay */ |
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DATA 4 0x63fd902c 0x000026d2 |
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/* Out of reset delays */ |
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DATA 4 0x63fd9030 0x00ff0e21 |
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/* ESDCTL ODT timing control */ |
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DATA 4 0x63fd9008 0x12273030 |
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/* ESDCTL power down control */ |
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DATA 4 0x63fd9004 0x0002002d |
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/* Set registers in DDR memory chips */ |
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DATA 4 0x63fd901c 0x00008032 |
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DATA 4 0x63fd901c 0x00008033 |
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DATA 4 0x63fd901c 0x00028031 |
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DATA 4 0x63fd901c 0x052080b0 |
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DATA 4 0x63fd901c 0x04008040 |
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/* ESDCTL refresh control */ |
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DATA 4 0x63fd9020 0x00005800 |
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/* PHY ZQ HW control */ |
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DATA 4 0x63fd9040 0x05380003 |
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/* PHY ODT control */ |
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DATA 4 0x63fd9058 0x00022222 |
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/* start DDR3 */ |
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DATA 4 0x63fd901c 0x00000000 |
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@ -1,6 +0,0 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_IMA3_MX53=y |
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg" |
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# CONFIG_CMD_SETEXPR is not set |
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CONFIG_SPI_FLASH=y |
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CONFIG_SYS_PROMPT="IMA3 MX53 U-Boot > " |
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@ -1,238 +0,0 @@ |
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/*
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* (C) Copyright 2012, Stefano Babic <sbabic@denx.de> |
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* |
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* Copyright (C) 2010 Freescale Semiconductor, Inc. |
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* |
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* Configuration settings for the MX53-EVK Freescale board. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/* SOC type must be included before imx-regs.h */ |
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#define CONFIG_MX53 |
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#include <asm/arch/imx-regs.h> |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_DISPLAY_BOARDINFO |
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_INITRD_TAG |
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#define CONFIG_OF_LIBFDT |
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/* Size of malloc() pool */ |
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) |
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#define CONFIG_BOARD_EARLY_INIT_F |
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/* Enable GPIOs */ |
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#define CONFIG_MXC_GPIO |
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/* UART */ |
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#define CONFIG_MXC_UART |
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#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR |
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/* MMC */ |
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#define CONFIG_FSL_ESDHC |
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
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#define CONFIG_SYS_FSL_ESDHC_NUM 1 |
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#define CONFIG_MMC |
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#define CONFIG_GENERIC_MMC |
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#define CONFIG_DOS_PARTITION |
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/* Ethernet on FEC */ |
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#define CONFIG_MII |
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#define CONFIG_FEC_MXC |
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#define IMX_FEC_BASE FEC_BASE_ADDR |
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#define CONFIG_FEC_MXC_PHYADDR 0x01 |
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#define CONFIG_PHY_ADDR CONFIG_FEC_MXC_PHYADDR |
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#define CONFIG_RESET_PHY_R |
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#define CONFIG_FEC_MXC_NO_ANEG |
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#define CONFIG_ETHPRIME "FEC0" |
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/* SPI */ |
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#define CONFIG_HARD_SPI |
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#define CONFIG_MXC_SPI |
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#define CONFIG_DEFAULT_SPI_BUS 1 |
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#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 |
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/* SPI FLASH - not used for environment */ |
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#define CONFIG_SPI_FLASH_STMICRO |
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
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#define CONFIG_SF_DEFAULT_SPEED 25000000 |
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/* allow to overwrite serial and ethaddr */ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_CONS_INDEX 1 |
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#define CONFIG_BAUDRATE 115200 |
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/* Command definition */ |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_MII |
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#define CONFIG_CMD_MMC |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_CMD_MTDPARTS |
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#define CONFIG_CMD_SPI |
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#define CONFIG_CMD_SF |
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#define CONFIG_CMD_GPIO |
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#define CONFIG_BOOTDELAY 3 |
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#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ |
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#define CONFIG_SYS_TEXT_BASE 0xf0001400 /* uboot in nor flash */ |
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#define CONFIG_ARP_TIMEOUT 200UL |
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/* Miscellaneous configurable options */ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
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#define CONFIG_AUTO_COMPLETE |
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
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/* Print Buffer Size */ |
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
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#define CONFIG_SYS_MEMTEST_START 0x70000000 |
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#define CONFIG_SYS_MEMTEST_END 0x10000 |
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
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#define CONFIG_CMDLINE_EDITING |
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/* Physical Memory Map */ |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR |
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#define PHYS_SDRAM_1_SIZE (1024 * 1024 * 1024) |
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|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) |
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) |
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
||||
#define MTDIDS_DEFAULT "nor0=f0000000.flash" |
||||
|
||||
/* FLASH and environment organization */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xF0000000 |
||||
#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ |
||||
#define CONFIG_FLASH_CFI_MTD /* with MTD support */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 |
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
||||
|
||||
#define CONFIG_ENV_SIZE (8 * 1024) |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
||||
CONFIG_SYS_MONITOR_LEN) |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ |
||||
CONFIG_ENV_SECT_SIZE) |
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
||||
|
||||
/*
|
||||
* Default environment and default scripts |
||||
* to update uboot and load kernel |
||||
*/ |
||||
|
||||
#define HOSTNAME ima3-mx53 |
||||
|
||||
#define CONFIG_HOSTNAME ima3-mx53 |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram0 rw\0" \
|
||||
"addip_sta=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
|
||||
"addip=if test -n ${ipdyn};then run addip_dyn;" \
|
||||
"else run addip_sta;fi\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=${console},${baudrate}\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
|
||||
"console=ttymxc3\0" \
|
||||
"loadaddr=70800000\0" \
|
||||
"kernel_addr_r=70800000\0" \
|
||||
"ramdisk_addr_r=71000000\0" \
|
||||
"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
|
||||
"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
|
||||
"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
|
||||
"mmcargs=setenv bootargs root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"mmcroot=/dev/mmcblk0p3 rw\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs addip addtty addmtd addmisc mmcload;" \
|
||||
"bootm\0" \
|
||||
"mmcload=fatload mmc ${mmcdev}:${mmcpart} " \
|
||||
"${loadaddr} ${uimage}\0" \
|
||||
"mmcrootfstype=ext3 rootwait\0" \
|
||||
"flash_self=run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
|
||||
"run nfsargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r}\0" \
|
||||
"net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};" \
|
||||
"tftp ${kernel_addr_r} ${bootfile}\0" \
|
||||
"net_self=if run net_self_load;then " \
|
||||
"run ramargs addip addtty addmtd addmisc;" \
|
||||
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
|
||||
"else echo Images not loades;fi\0" \
|
||||
"satargs=setenv bootargs root=/dev/sda1\0" \
|
||||
"satafile=boot/uImage\0" \
|
||||
"ssdboot=echo Booting from ssd ...; " \
|
||||
"run satargs addip addtty addmtd addmisc;" \
|
||||
"sata init;ext2load sata 0:1 ${kernel_addr_r} " \
|
||||
"${satafile};bootm\0" \
|
||||
"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.imx\0" \
|
||||
"uimage=uImage\0" \
|
||||
"load=tftp ${loadaddr} ${u-boot}\0" \
|
||||
"uboot_addr=0xf0001000\0" \
|
||||
"update=protect off 0xf0000000 +60000;" \
|
||||
"erase ${uboot_addr} +60000;" \
|
||||
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
|
||||
"upd=if run load;then echo Updating u-boot;if run update;" \
|
||||
"then echo U-Boot updated;" \
|
||||
"else echo Error updating u-boot !;" \
|
||||
"echo Board without bootloader !!;" \
|
||||
"fi;" \
|
||||
"else echo U-Boot not downloaded..exiting;fi\0" \
|
||||
"bootcmd=run net_nfs\0" |
||||
|
||||
|
||||
#define CONFIG_CMD_SATA |
||||
#ifdef CONFIG_CMD_SATA |
||||
#define CONFIG_DWC_AHSATA |
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1 |
||||
#define CONFIG_DWC_AHSATA_PORT_ID 0 |
||||
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR |
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_LIBATA |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue