Aubrey.Li
18 years ago
parent
eb92f61355
commit
3f0606ad0b
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005-2007 Analog Device Inc.
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o spi.o
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$(LIB): .depend $(OBJS) u-boot.lds |
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$(AR) cr $@ $(OBJS)
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u-boot.lds: u-boot.lds.S |
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$(CPP) $(CPPFLAGS) -P -Ubfin $^ > $@.tmp
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mv -f $@.tmp $@
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -0,0 +1,472 @@ |
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/****************************************************************************
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* SPI flash driver for M25P64 |
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****************************************************************************/ |
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#include <common.h> |
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#include <linux/ctype.h> |
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#if defined(CONFIG_SPI) |
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/*Application definitions */ |
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#define NUM_SECTORS 128 /* number of sectors */ |
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#define SECTOR_SIZE 0x10000 |
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#define NOP_NUM 1000 |
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#define COMMON_SPI_SETTINGS (SPE|MSTR|CPHA|CPOL) /*Settings to the SPI_CTL */ |
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#define TIMOD01 (0x01) /*stes the SPI to work with core instructions */ |
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/*Flash commands */ |
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#define SPI_WREN (0x06) /*Set Write Enable Latch */ |
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#define SPI_WRDI (0x04) /*Reset Write Enable Latch */ |
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#define SPI_RDSR (0x05) /*Read Status Register */ |
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#define SPI_WRSR (0x01) /*Write Status Register */ |
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#define SPI_READ (0x03) /*Read data from memory */ |
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#define SPI_PP (0x02) /*Program Data into memory */ |
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#define SPI_SE (0xD8) /*Erase one sector in memory */ |
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#define SPI_BE (0xC7) /*Erase all memory */ |
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#define WIP (0x1) /*Check the write in progress bit of the SPI status register */ |
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#define WEL (0x2) /*Check the write enable bit of the SPI status register */ |
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#define TIMEOUT 350000000 |
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typedef enum { |
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NO_ERR, |
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POLL_TIMEOUT, |
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INVALID_SECTOR, |
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INVALID_BLOCK, |
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} ERROR_CODE; |
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void spi_init_f(void); |
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void spi_init_r(void); |
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ssize_t spi_read(uchar *, int, uchar *, int); |
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ssize_t spi_write(uchar *, int, uchar *, int); |
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char ReadStatusRegister(void); |
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void Wait_For_SPIF(void); |
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void SetupSPI(const int spi_setting); |
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void SPI_OFF(void); |
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void SendSingleCommand(const int iCommand); |
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ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector); |
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ERROR_CODE EraseBlock(int nBlock); |
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ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData); |
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ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData); |
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ERROR_CODE Wait_For_Status(char Statusbit); |
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ERROR_CODE Wait_For_WEL(void); |
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/* -------------------
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* Variables |
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* ------------------- */ |
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/* **************************************************************************
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* |
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* Function: spi_init_f |
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* |
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* Description: Init SPI-Controller (ROM part) |
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* |
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* return: --- |
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* |
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* *********************************************************************** */ |
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void spi_init_f(void) |
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{ |
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} |
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/* **************************************************************************
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* |
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* Function: spi_init_r |
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* |
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* Description: Init SPI-Controller (RAM part) - |
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* The malloc engine is ready and we can move our buffers to |
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* normal RAM |
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* |
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* return: --- |
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* |
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* *********************************************************************** */ |
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void spi_init_r(void) |
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{ |
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return; |
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} |
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/****************************************************************************
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* Function: spi_write |
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**************************************************************************** */ |
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ssize_t spi_write(uchar * addr, int alen, uchar * buffer, int len) |
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{ |
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unsigned long offset; |
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int start_block, end_block; |
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int start_byte, end_byte; |
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ERROR_CODE result = NO_ERR; |
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uchar temp[SECTOR_SIZE]; |
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int i, num; |
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offset = addr[0] << 16 | addr[1] << 8 | addr[2]; |
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/* Get the start block number */ |
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result = GetSectorNumber(offset, &start_block); |
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if (result == INVALID_SECTOR) { |
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printf("Invalid sector! "); |
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return 0; |
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} |
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/* Get the end block number */ |
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result = GetSectorNumber(offset + len - 1, &end_block); |
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if (result == INVALID_SECTOR) { |
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printf("Invalid sector! "); |
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return 0; |
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} |
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for (num = start_block; num <= end_block; num++) { |
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ReadData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp); |
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start_byte = num * SECTOR_SIZE; |
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end_byte = (num + 1) * SECTOR_SIZE - 1; |
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if (start_byte < offset) |
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start_byte = offset; |
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if (end_byte > (offset + len)) |
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end_byte = (offset + len - 1); |
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for (i = start_byte; i <= end_byte; i++) |
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temp[i - num * SECTOR_SIZE] = buffer[i - offset]; |
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EraseBlock(num); |
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result = WriteData(num * SECTOR_SIZE, SECTOR_SIZE, (int *)temp); |
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if (result != NO_ERR) |
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return 0; |
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printf("."); |
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} |
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return len; |
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} |
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/****************************************************************************
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* Function: spi_read |
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**************************************************************************** */ |
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ssize_t spi_read(uchar * addr, int alen, uchar * buffer, int len) |
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{ |
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unsigned long offset; |
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offset = addr[0] << 16 | addr[1] << 8 | addr[2]; |
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ReadData(offset, len, (int *)buffer); |
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return len; |
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} |
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void SendSingleCommand(const int iCommand) |
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{ |
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unsigned short dummy; |
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/*turns on the SPI in single write mode */ |
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SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); |
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/*sends the actual command to the SPI TX register */ |
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*pSPI_TDBR = iCommand; |
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__builtin_bfin_ssync(); |
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/*The SPI status register will be polled to check the SPIF bit */ |
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Wait_For_SPIF(); |
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dummy = *pSPI_RDBR; |
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/*The SPI will be turned off */ |
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SPI_OFF(); |
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} |
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void SetupSPI(const int spi_setting) |
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{ |
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if (icache_status() || dcache_status()) |
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udelay(CONFIG_CCLK_HZ / 50000000); |
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/*sets up the PF2 to be the slave select of the SPI */ |
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*pSPI_FLG = 0xFB04; |
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*pSPI_BAUD = CONFIG_SPI_BAUD; |
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*pSPI_CTL = spi_setting; |
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__builtin_bfin_ssync(); |
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} |
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void SPI_OFF(void) |
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{ |
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*pSPI_CTL = 0x0400; /* disable SPI */ |
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*pSPI_FLG = 0; |
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*pSPI_BAUD = 0; |
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__builtin_bfin_ssync(); |
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udelay(CONFIG_CCLK_HZ / 50000000); |
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} |
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void Wait_For_SPIF(void) |
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{ |
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unsigned short dummyread; |
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while ((*pSPI_STAT & TXS)) ; |
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while (!(*pSPI_STAT & SPIF)) ; |
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while (!(*pSPI_STAT & RXS)) ; |
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dummyread = *pSPI_RDBR; /* Read dummy to empty the receive register */ |
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} |
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ERROR_CODE Wait_For_WEL(void) |
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{ |
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int i; |
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char status_register = 0; |
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ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */ |
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for (i = 0; i < TIMEOUT; i++) { |
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status_register = ReadStatusRegister(); |
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if ((status_register & WEL)) { |
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ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */ |
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break; |
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} |
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ErrorCode = POLL_TIMEOUT; /* Time out error */ |
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}; |
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return ErrorCode; |
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} |
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ERROR_CODE Wait_For_Status(char Statusbit) |
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{ |
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int i; |
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char status_register = 0xFF; |
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ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */ |
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for (i = 0; i < TIMEOUT; i++) { |
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status_register = ReadStatusRegister(); |
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if (!(status_register & Statusbit)) { |
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ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */ |
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break; |
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} |
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ErrorCode = POLL_TIMEOUT; /* Time out error */ |
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}; |
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return ErrorCode; |
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} |
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char ReadStatusRegister(void) |
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{ |
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char status_register = 0; |
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SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turn on the SPI */ |
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*pSPI_TDBR = SPI_RDSR; /* send instruction to read status register */ |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /*wait until the instruction has been sent */ |
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*pSPI_TDBR = 0; /*send dummy to receive the status register */ |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /*wait until the data has been sent */ |
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status_register = *pSPI_RDBR; /*read the status register */ |
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SPI_OFF(); /* Turn off the SPI */ |
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return status_register; |
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} |
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ERROR_CODE GetSectorNumber(unsigned long ulOffset, int *pnSector) |
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{ |
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int nSector = 0; |
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ERROR_CODE ErrorCode = NO_ERR; |
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if (ulOffset > (NUM_SECTORS * 0x10000 - 1)) { |
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ErrorCode = INVALID_SECTOR; |
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return ErrorCode; |
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} |
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nSector = (int)ulOffset / 0x10000; |
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*pnSector = nSector; |
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/* ok */ |
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return ErrorCode; |
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} |
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ERROR_CODE EraseBlock(int nBlock) |
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{ |
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unsigned long ulSectorOff = 0x0, ShiftValue; |
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ERROR_CODE ErrorCode = NO_ERR; |
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/* if the block is invalid just return */ |
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if ((nBlock < 0) || (nBlock > NUM_SECTORS)) { |
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ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */ |
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return ErrorCode; |
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} |
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/* figure out the offset of the block in flash */ |
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if ((nBlock >= 0) && (nBlock < NUM_SECTORS)) { |
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ulSectorOff = (nBlock * SECTOR_SIZE); |
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} else { |
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ErrorCode = INVALID_BLOCK; /* tells us if there was an error erasing flash */ |
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return ErrorCode; |
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} |
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/* A write enable instruction must previously have been executed */ |
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SendSingleCommand(SPI_WREN); |
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/*The status register will be polled to check the write enable latch "WREN" */ |
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ErrorCode = Wait_For_WEL(); |
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if (POLL_TIMEOUT == ErrorCode) { |
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printf("SPI Erase block error\n"); |
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return ErrorCode; |
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} else |
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/*Turn on the SPI to send single commands */ |
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SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); |
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/* Send the erase block command to the flash followed by the 24 address */ |
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/* to point to the start of a sector. */ |
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*pSPI_TDBR = SPI_SE; |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); |
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ShiftValue = (ulSectorOff >> 16); /* Send the highest byte of the 24 bit address at first */ |
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*pSPI_TDBR = ShiftValue; |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /* Wait until the instruction has been sent */ |
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ShiftValue = (ulSectorOff >> 8); /* Send the middle byte of the 24 bit address at second */ |
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*pSPI_TDBR = ShiftValue; |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /* Wait until the instruction has been sent */ |
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*pSPI_TDBR = ulSectorOff; /* Send the lowest byte of the 24 bit address finally */ |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /* Wait until the instruction has been sent */ |
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/*Turns off the SPI */ |
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SPI_OFF(); |
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/* Poll the status register to check the Write in Progress bit */ |
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/* Sector erase takes time */ |
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ErrorCode = Wait_For_Status(WIP); |
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/* block erase should be complete */ |
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return ErrorCode; |
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} |
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/*****************************************************************************
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* ERROR_CODE ReadData() |
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* |
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* Read a value from flash for verify purpose |
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* |
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* Inputs: unsigned long ulStart - holds the SPI start address |
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* int pnData - pointer to store value read from flash |
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* long lCount - number of elements to read |
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***************************************************************************** */ |
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ERROR_CODE ReadData(unsigned long ulStart, long lCount, int *pnData) |
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{ |
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unsigned long ShiftValue; |
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char *cnData; |
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int i; |
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cnData = (char *)pnData; /* Pointer cast to be able to increment byte wise */ |
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/* Start SPI interface */ |
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SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); |
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*pSPI_TDBR = SPI_READ; /* Send the read command to SPI device */ |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /* Wait until the instruction has been sent */ |
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ShiftValue = (ulStart >> 16); /* Send the highest byte of the 24 bit address at first */ |
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*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */ |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /* Wait until the instruction has been sent */ |
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ShiftValue = (ulStart >> 8); /* Send the middle byte of the 24 bit address at second */ |
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*pSPI_TDBR = ShiftValue; /* Send the byte to the SPI device */ |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /* Wait until the instruction has been sent */ |
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*pSPI_TDBR = ulStart; /* Send the lowest byte of the 24 bit address finally */ |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /* Wait until the instruction has been sent */ |
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/* After the SPI device address has been placed on the MOSI pin the data can be */ |
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/* received on the MISO pin. */ |
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for (i = 0; i < lCount; i++) { |
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*pSPI_TDBR = 0; /*send dummy */ |
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__builtin_bfin_ssync(); |
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while (!(*pSPI_STAT & RXS)) ; |
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*cnData++ = *pSPI_RDBR; /*read */ |
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if ((i >= SECTOR_SIZE) && (i % SECTOR_SIZE == 0)) |
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printf("."); |
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} |
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SPI_OFF(); /* Turn off the SPI */ |
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return NO_ERR; |
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} |
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ERROR_CODE WriteFlash(unsigned long ulStartAddr, long lTransferCount, |
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int *iDataSource, long *lWriteCount) |
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{ |
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unsigned long ulWAddr; |
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long lWTransferCount = 0; |
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int i; |
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char iData; |
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char *temp = (char *)iDataSource; |
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ERROR_CODE ErrorCode = NO_ERR; /* tells us if there was an error erasing flash */ |
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/* First, a Write Enable Command must be sent to the SPI. */ |
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SendSingleCommand(SPI_WREN); |
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/* Second, the SPI Status Register will be tested whether the */ |
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/* Write Enable Bit has been set. */ |
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ErrorCode = Wait_For_WEL(); |
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if (POLL_TIMEOUT == ErrorCode) { |
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printf("SPI Write Time Out\n"); |
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return ErrorCode; |
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} else |
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/* Third, the 24 bit address will be shifted out the SPI MOSI bytewise. */ |
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SetupSPI((COMMON_SPI_SETTINGS | TIMOD01)); /* Turns the SPI on */ |
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*pSPI_TDBR = SPI_PP; |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /*wait until the instruction has been sent */ |
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ulWAddr = (ulStartAddr >> 16); |
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*pSPI_TDBR = ulWAddr; |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /*wait until the instruction has been sent */ |
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ulWAddr = (ulStartAddr >> 8); |
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*pSPI_TDBR = ulWAddr; |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /*wait until the instruction has been sent */ |
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ulWAddr = ulStartAddr; |
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*pSPI_TDBR = ulWAddr; |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /*wait until the instruction has been sent */ |
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/* Fourth, maximum number of 256 bytes will be taken from the Buffer */ |
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/* and sent to the SPI device. */ |
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for (i = 0; (i < lTransferCount) && (i < 256); i++, lWTransferCount++) { |
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iData = *temp; |
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*pSPI_TDBR = iData; |
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__builtin_bfin_ssync(); |
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Wait_For_SPIF(); /*wait until the instruction has been sent */ |
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temp++; |
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} |
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SPI_OFF(); /* Turns the SPI off */ |
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/* Sixth, the SPI Write in Progress Bit must be toggled to ensure the */ |
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/* programming is done before start of next transfer. */ |
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ErrorCode = Wait_For_Status(WIP); |
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if (POLL_TIMEOUT == ErrorCode) { |
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printf("SPI Program Time out!\n"); |
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return ErrorCode; |
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} else |
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*lWriteCount = lWTransferCount; |
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return ErrorCode; |
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} |
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ERROR_CODE WriteData(unsigned long ulStart, long lCount, int *pnData) |
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{ |
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unsigned long ulWStart = ulStart; |
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long lWCount = lCount, lWriteCount; |
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long *pnWriteCount = &lWriteCount; |
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ERROR_CODE ErrorCode = NO_ERR; |
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while (lWCount != 0) { |
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ErrorCode = WriteFlash(ulWStart, lWCount, pnData, pnWriteCount); |
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/* After each function call of WriteFlash the counter must be adjusted */ |
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lWCount -= *pnWriteCount; |
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/* Also, both address pointers must be recalculated. */ |
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ulWStart += *pnWriteCount; |
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pnData += *pnWriteCount / 4; |
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} |
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/* return the appropriate error code */ |
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return ErrorCode; |
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} |
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#endif /* CONFIG_SPI */ |
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@ -1,71 +0,0 @@ |
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#
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# U-boot - Makefile
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#
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# Copyright (c) 2005 blackfin.uclinux.org
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o stamp.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -1,193 +0,0 @@ |
||||
/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. |
||||
* |
||||
* Blackfin BF533/2.6 support : LG Soft India |
||||
*/ |
||||
|
||||
|
||||
/* Include an exception handler to invoke the CPLB manager |
||||
*/ |
||||
|
||||
#include <asm-blackfin/linkage.h> |
||||
#include <asm/cplb.h> |
||||
#include <asm/entry.h> |
||||
|
||||
|
||||
.text |
||||
|
||||
.globl _cplb_hdr;
|
||||
.type _cplb_hdr, STT_FUNC;
|
||||
.extern _cplb_mgr;
|
||||
.type _cplb_mgr, STT_FUNC;
|
||||
.extern __unknown_exception_occurred;
|
||||
.type __unknown_exception_occurred, STT_FUNC;
|
||||
.extern __cplb_miss_all_locked;
|
||||
.type __cplb_miss_all_locked, STT_FUNC;
|
||||
.extern __cplb_miss_without_replacement;
|
||||
.type __cplb_miss_without_replacement, STT_FUNC;
|
||||
.extern __cplb_protection_violation;
|
||||
.type __cplb_protection_violation, STT_FUNC;
|
||||
.extern panic_pv;
|
||||
|
||||
.align 2;
|
||||
|
||||
ENTRY(_cplb_hdr) |
||||
SSYNC;
|
||||
[--SP] = ( R7:0, P5:0 );
|
||||
[--SP] = ASTAT;
|
||||
[--SP] = SEQSTAT;
|
||||
[--SP] = I0;
|
||||
[--SP] = I1;
|
||||
[--SP] = I2;
|
||||
[--SP] = I3;
|
||||
[--SP] = LT0;
|
||||
[--SP] = LB0;
|
||||
[--SP] = LC0;
|
||||
[--SP] = LT1;
|
||||
[--SP] = LB1;
|
||||
[--SP] = LC1;
|
||||
R2 = SEQSTAT;
|
||||
|
||||
/*Mask the contents of SEQSTAT and leave only EXCAUSE in R2*/ |
||||
R2 <<= 26;
|
||||
R2 >>= 26;
|
||||
|
||||
R1 = 0x23; /* Data access CPLB protection violation */
|
||||
CC = R2 == R1;
|
||||
IF !CC JUMP not_data_write;
|
||||
R0 = 2; /* is a write to data space*/
|
||||
JUMP is_icplb_miss;
|
||||
|
||||
not_data_write: |
||||
R1 = 0x2C; /* CPLB miss on an instruction fetch */
|
||||
CC = R2 == R1;
|
||||
R0 = 0; /* is_data_miss == False*/
|
||||
IF CC JUMP is_icplb_miss;
|
||||
|
||||
R1 = 0x26;
|
||||
CC = R2 == R1;
|
||||
IF !CC JUMP unknown;
|
||||
|
||||
R0 = 1; /* is_data_miss == True*/
|
||||
|
||||
is_icplb_miss: |
||||
|
||||
#if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE)) |
||||
#if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE)) |
||||
R1 = CPLB_ENABLE_ICACHE;
|
||||
#endif |
||||
#if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE)) |
||||
R1 = CPLB_ENABLE_DCACHE;
|
||||
#endif |
||||
#if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE)) |
||||
R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
|
||||
#endif |
||||
#else |
||||
R1 = 0;
|
||||
#endif |
||||
|
||||
[--SP] = RETS;
|
||||
CALL _cplb_mgr;
|
||||
RETS = [SP++];
|
||||
CC = R0 == 0;
|
||||
IF !CC JUMP not_replaced;
|
||||
LC1 = [SP++];
|
||||
LB1 = [SP++];
|
||||
LT1 = [SP++];
|
||||
LC0 = [SP++];
|
||||
LB0 = [SP++];
|
||||
LT0 = [SP++];
|
||||
I3 = [SP++];
|
||||
I2 = [SP++];
|
||||
I1 = [SP++];
|
||||
I0 = [SP++];
|
||||
SEQSTAT = [SP++];
|
||||
ASTAT = [SP++];
|
||||
( R7:0, P5:0 ) = [SP++];
|
||||
RTS;
|
||||
|
||||
unknown: |
||||
[--SP] = RETS;
|
||||
CALL __unknown_exception_occurred;
|
||||
RETS = [SP++];
|
||||
JUMP unknown;
|
||||
not_replaced: |
||||
CC = R0 == CPLB_NO_UNLOCKED;
|
||||
IF !CC JUMP next_check;
|
||||
[--SP] = RETS;
|
||||
CALL __cplb_miss_all_locked;
|
||||
RETS = [SP++];
|
||||
next_check: |
||||
CC = R0 == CPLB_NO_ADDR_MATCH;
|
||||
IF !CC JUMP next_check2;
|
||||
[--SP] = RETS;
|
||||
CALL __cplb_miss_without_replacement;
|
||||
RETS = [SP++];
|
||||
JUMP not_replaced;
|
||||
next_check2: |
||||
CC = R0 == CPLB_PROT_VIOL;
|
||||
IF !CC JUMP strange_return_from_cplb_mgr;
|
||||
[--SP] = RETS;
|
||||
CALL __cplb_protection_violation;
|
||||
RETS = [SP++];
|
||||
JUMP not_replaced;
|
||||
strange_return_from_cplb_mgr: |
||||
IDLE;
|
||||
CSYNC;
|
||||
JUMP strange_return_from_cplb_mgr;
|
||||
|
||||
/************************************ |
||||
* Diagnostic exception handlers |
||||
*/ |
||||
|
||||
__cplb_miss_all_locked: |
||||
sp += -12;
|
||||
R0 = CPLB_NO_UNLOCKED;
|
||||
call panic_bfin;
|
||||
SP += 12;
|
||||
RTS;
|
||||
|
||||
__cplb_miss_without_replacement: |
||||
sp += -12;
|
||||
R0 = CPLB_NO_ADDR_MATCH;
|
||||
call panic_bfin;
|
||||
SP += 12;
|
||||
RTS;
|
||||
|
||||
__cplb_protection_violation: |
||||
sp += -12;
|
||||
R0 = CPLB_PROT_VIOL;
|
||||
call panic_bfin;
|
||||
SP += 12;
|
||||
RTS;
|
||||
|
||||
__unknown_exception_occurred: |
||||
|
||||
/* This function is invoked by the default exception |
||||
* handler, if it does not recognise the kind of |
||||
* exception that has occurred. In other words, the |
||||
* default handler only handles some of the system's |
||||
* exception types, and it does not expect any others |
||||
* to occur. If your application is going to be using |
||||
* other kinds of exceptions, you must replace the |
||||
* default handler with your own, that handles all the |
||||
* exceptions you will use. |
||||
* |
||||
* Since there's nothing we can do, we just loop here |
||||
* at what we hope is a suitably informative label. |
||||
*/ |
||||
|
||||
IDLE;
|
||||
do_not_know_what_to_do: |
||||
CSYNC;
|
||||
JUMP __unknown_exception_occurred;
|
||||
|
||||
RTS;
|
||||
.__unknown_exception_occurred.end: |
||||
.global __unknown_exception_occurred;
|
||||
.type __unknown_exception_occurred, STT_FUNC;
|
||||
|
||||
panic_bfin: |
||||
RTS;
|
||||
@ -1,601 +0,0 @@ |
||||
/*This file is subject to the terms and conditions of the GNU General Public |
||||
* License. |
||||
* |
||||
* Blackfin BF533/2.6 support : LG Soft India |
||||
* Modification: Dec 07 2004 |
||||
* 1. Correction in icheck_lock. Valid lock entries were |
||||
* geting victimized, for instruction cplb replacement. |
||||
* 2. Setup loop's are modified as now toolchain support's P Indexed |
||||
* addressing |
||||
* :LG Soft India |
||||
* |
||||
*/ |
||||
|
||||
/* Usage: int _cplb_mgr(is_data_miss,int enable_cache) |
||||
* is_data_miss==2 => Mark as Dirty, write to the clean data page |
||||
* is_data_miss==1 => Replace a data CPLB. |
||||
* is_data_miss==0 => Replace an instruction CPLB. |
||||
* |
||||
* Returns: |
||||
* CPLB_RELOADED => Successfully updated CPLB table. |
||||
* CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates |
||||
* that the CPLBs in the configuration tablei are badly |
||||
* configured, as this should never occur. |
||||
* CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception, |
||||
* is not covered by any of the CPLBs in the configuration |
||||
* table. The application isi presumably misbehaving. |
||||
* CPLB_PROT_VIOL => The address being accessed, that triggered thei exception, |
||||
* was not a first-write to a clean Write Back Data page, |
||||
* and so presumably is a genuine violation of the page's |
||||
* protection attributes. The application is misbehaving. |
||||
*/ |
||||
#define ASSEMBLY |
||||
|
||||
#include <asm-blackfin/linkage.h> |
||||
#include <asm-blackfin/blackfin.h> |
||||
#include <asm-blackfin/cplbtab.h> |
||||
#include <asm-blackfin/cplb.h> |
||||
|
||||
.text |
||||
|
||||
.align 2;
|
||||
ENTRY(_cplb_mgr) |
||||
|
||||
[--SP]=( R7:0,P5:0 );
|
||||
|
||||
CC = R0 == 2;
|
||||
IF CC JUMP dcplb_write;
|
||||
|
||||
CC = R0 == 0;
|
||||
IF !CC JUMP dcplb_miss_compare;
|
||||
|
||||
/* ICPLB Miss Exception. We need to choose one of the |
||||
* currently-installed CPLBs, and replace it with one |
||||
* from the configuration table. |
||||
*/ |
||||
|
||||
P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
|
||||
P4.H = (ICPLB_FAULT_ADDR >> 16);
|
||||
|
||||
P1 = 16;
|
||||
P5.L = page_size_table;
|
||||
P5.H = page_size_table;
|
||||
|
||||
P0.L = (ICPLB_DATA0 & 0xFFFF);
|
||||
P0.H = (ICPLB_DATA0 >> 16);
|
||||
R4 = [P4]; /* Get faulting address*/
|
||||
R6 = 64; /* Advance past the fault address, which*/
|
||||
R6 = R6 + R4; /* we'll use if we find a match*/
|
||||
R3 = ((16 << 8) | 2); /* Extract mask, bits 16 and 17.*/
|
||||
|
||||
R5 = 0;
|
||||
isearch: |
||||
|
||||
R1 = [P0-0x100]; /* Address for this CPLB */
|
||||
|
||||
R0 = [P0++]; /* Info for this CPLB*/
|
||||
CC = BITTST(R0,0); /* Is the CPLB valid?*/
|
||||
IF !CC JUMP nomatch; /* Skip it, if not.*/
|
||||
CC = R4 < R1(IU); /* If fault address less than page start*/
|
||||
IF CC JUMP nomatch; /* then skip this one.*/
|
||||
R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
|
||||
P1 = R2;
|
||||
P1 = P5 + (P1<<2); /* index into page-size table*/
|
||||
R2 = [P1]; /* Get the page size*/
|
||||
R1 = R1 + R2; /* and add to page start, to get page end*/
|
||||
CC = R4 < R1(IU); /* and see whether fault addr is in page.*/
|
||||
IF !CC R4 = R6; /* If so, advance the address and finish loop.*/
|
||||
IF !CC JUMP isearch_done;
|
||||
nomatch: |
||||
/* Go around again*/ |
||||
R5 += 1;
|
||||
CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
|
||||
IF !CC JUMP isearch;
|
||||
|
||||
isearch_done: |
||||
I0 = R4; /* Fault address we'll search for*/
|
||||
|
||||
/* set up pointers */ |
||||
P0.L = (ICPLB_DATA0 & 0xFFFF);
|
||||
P0.H = (ICPLB_DATA0 >> 16);
|
||||
|
||||
/* The replacement procedure for ICPLBs */ |
||||
|
||||
P4.L = (IMEM_CONTROL & 0xFFFF);
|
||||
P4.H = (IMEM_CONTROL >> 16);
|
||||
|
||||
/* disable cplbs */ |
||||
R5 = [P4]; /* Control Register*/
|
||||
BITCLR(R5,ENICPLB_P);
|
||||
CLI R1;
|
||||
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
|
||||
.align 8;
|
||||
[P4] = R5;
|
||||
SSYNC;
|
||||
STI R1;
|
||||
|
||||
R1 = -1; /* end point comparison */
|
||||
R3 = 16; /* counter */
|
||||
|
||||
/* Search through CPLBs for first non-locked entry */ |
||||
/* Overwrite it by moving everyone else up by 1 */ |
||||
icheck_lock: |
||||
R0 = [P0++];
|
||||
R3 = R3 + R1;
|
||||
CC = R3 == R1;
|
||||
IF CC JUMP all_locked;
|
||||
CC = BITTST(R0, 0); /* an invalid entry is good */
|
||||
IF !CC JUMP ifound_victim;
|
||||
CC = BITTST(R0,1); /* but a locked entry isn't */
|
||||
IF CC JUMP icheck_lock;
|
||||
|
||||
ifound_victim: |
||||
#ifdef CONFIG_CPLB_INFO |
||||
R7 = [P0 - 0x104];
|
||||
P2.L = ipdt_table;
|
||||
P2.H = ipdt_table;
|
||||
P3.L = ipdt_swapcount_table;
|
||||
P3.H = ipdt_swapcount_table;
|
||||
P3 += -4;
|
||||
icount: |
||||
R2 = [P2]; /* address from config table */
|
||||
P2 += 8;
|
||||
P3 += 8;
|
||||
CC = R2==-1;
|
||||
IF CC JUMP icount_done;
|
||||
CC = R7==R2;
|
||||
IF !CC JUMP icount;
|
||||
R7 = [P3];
|
||||
R7 += 1;
|
||||
[P3] = R7;
|
||||
CSYNC;
|
||||
icount_done: |
||||
#endif |
||||
LC0=R3;
|
||||
LSETUP(is_move,ie_move) LC0;
|
||||
is_move: |
||||
R0 = [P0];
|
||||
[P0 - 4] = R0;
|
||||
R0 = [P0 - 0x100];
|
||||
[P0-0x104] = R0;
|
||||
ie_move:P0+=4;
|
||||
|
||||
/* We've made space in the ICPLB table, so that ICPLB15 |
||||
* is now free to be overwritten. Next, we have to determine |
||||
* which CPLB we need to install, from the configuration |
||||
* table. This is a matter of getting the start-of-page |
||||
* addresses and page-lengths from the config table, and |
||||
* determining whether the fault address falls within that |
||||
* range. |
||||
*/ |
||||
|
||||
P2.L = ipdt_table;
|
||||
P2.H = ipdt_table;
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
P3.L = ipdt_swapcount_table;
|
||||
P3.H = ipdt_swapcount_table;
|
||||
P3 += -8;
|
||||
#endif |
||||
P0.L = page_size_table;
|
||||
P0.H = page_size_table;
|
||||
|
||||
/* Retrieve our fault address (which may have been advanced |
||||
* because the faulting instruction crossed a page boundary). |
||||
*/ |
||||
|
||||
R0 = I0;
|
||||
|
||||
/* An extraction pattern, to get the page-size bits from |
||||
* the CPLB data entry. Bits 16-17, so two bits at posn 16. |
||||
*/ |
||||
|
||||
R1 = ((16<<8)|2);
|
||||
inext: R4 = [P2++]; /* address from config table */
|
||||
R2 = [P2++]; /* data from config table */
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
P3 += 8;
|
||||
#endif |
||||
|
||||
CC = R4 == -1; /* End of config table*/
|
||||
IF CC JUMP no_page_in_table;
|
||||
|
||||
/* See if failed address > start address */ |
||||
CC = R4 <= R0(IU);
|
||||
IF !CC JUMP inext;
|
||||
|
||||
/* extract page size (17:16)*/ |
||||
R3 = EXTRACT(R2, R1.L) (Z);
|
||||
|
||||
/* add page size to addr to get range */ |
||||
|
||||
P5 = R3;
|
||||
P5 = P0 + (P5 << 2); /* scaled, for int access*/
|
||||
R3 = [P5];
|
||||
R3 = R3 + R4;
|
||||
|
||||
/* See if failed address < (start address + page size) */ |
||||
CC = R0 < R3(IU);
|
||||
IF !CC JUMP inext;
|
||||
|
||||
/* We've found a CPLB in the config table that covers |
||||
* the faulting address, so install this CPLB into the |
||||
* last entry of the table. |
||||
*/ |
||||
|
||||
P1.L = (ICPLB_DATA15 & 0xFFFF); /*ICPLB_DATA15*/
|
||||
P1.H = (ICPLB_DATA15 >> 16);
|
||||
[P1] = R2;
|
||||
[P1-0x100] = R4;
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
R3 = [P3];
|
||||
R3 += 1;
|
||||
[P3] = R3;
|
||||
#endif |
||||
|
||||
/* P4 points to IMEM_CONTROL, and R5 contains its old |
||||
* value, after we disabled ICPLBS. Re-enable them. |
||||
*/ |
||||
|
||||
BITSET(R5,ENICPLB_P);
|
||||
CLI R2;
|
||||
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
|
||||
.align 8;
|
||||
[P4] = R5;
|
||||
SSYNC;
|
||||
STI R2;
|
||||
|
||||
( R7:0,P5:0 ) = [SP++];
|
||||
R0 = CPLB_RELOADED;
|
||||
RTS;
|
||||
|
||||
/* FAILED CASES*/ |
||||
no_page_in_table: |
||||
( R7:0,P5:0 ) = [SP++];
|
||||
R0 = CPLB_NO_ADDR_MATCH;
|
||||
RTS;
|
||||
all_locked: |
||||
( R7:0,P5:0 ) = [SP++];
|
||||
R0 = CPLB_NO_UNLOCKED;
|
||||
RTS;
|
||||
prot_violation: |
||||
( R7:0,P5:0 ) = [SP++];
|
||||
R0 = CPLB_PROT_VIOL;
|
||||
RTS;
|
||||
|
||||
dcplb_write: |
||||
|
||||
/* if a DCPLB is marked as write-back (CPLB_WT==0), and |
||||
* it is clean (CPLB_DIRTY==0), then a write to the |
||||
* CPLB's page triggers a protection violation. We have to |
||||
* mark the CPLB as dirty, to indicate that there are |
||||
* pending writes associated with the CPLB. |
||||
*/ |
||||
|
||||
P4.L = (DCPLB_STATUS & 0xFFFF);
|
||||
P4.H = (DCPLB_STATUS >> 16);
|
||||
P3.L = (DCPLB_DATA0 & 0xFFFF);
|
||||
P3.H = (DCPLB_DATA0 >> 16);
|
||||
R5 = [P4];
|
||||
|
||||
/* A protection violation can be caused by more than just writes |
||||
* to a clean WB page, so we have to ensure that: |
||||
* - It's a write |
||||
* - to a clean WB page |
||||
* - and is allowed in the mode the access occurred. |
||||
*/ |
||||
|
||||
CC = BITTST(R5, 16); /* ensure it was a write*/
|
||||
IF !CC JUMP prot_violation;
|
||||
|
||||
/* to check the rest, we have to retrieve the DCPLB.*/ |
||||
|
||||
/* The low half of DCPLB_STATUS is a bit mask*/ |
||||
|
||||
R2 = R5.L (Z); /* indicating which CPLB triggered the event.*/
|
||||
R3 = 30; /* so we can use this to determine the offset*/
|
||||
R2.L = SIGNBITS R2;
|
||||
R2 = R2.L (Z); /* into the DCPLB table.*/
|
||||
R3 = R3 - R2;
|
||||
P4 = R3;
|
||||
P3 = P3 + (P4<<2);
|
||||
R3 = [P3]; /* Retrieve the CPLB*/
|
||||
|
||||
/* Now we can check whether it's a clean WB page*/ |
||||
|
||||
CC = BITTST(R3, 14); /* 0==WB, 1==WT*/
|
||||
IF CC JUMP prot_violation;
|
||||
CC = BITTST(R3, 7); /* 0 == clean, 1 == dirty*/
|
||||
IF CC JUMP prot_violation;
|
||||
|
||||
/* Check whether the write is allowed in the mode that was active.*/ |
||||
|
||||
R2 = 1<<3; /* checking write in user mode*/
|
||||
CC = BITTST(R5, 17); /* 0==was user, 1==was super*/
|
||||
R5 = CC;
|
||||
R2 <<= R5; /* if was super, check write in super mode*/
|
||||
R2 = R3 & R2;
|
||||
CC = R2 == 0;
|
||||
IF CC JUMP prot_violation;
|
||||
|
||||
/* It's a genuine write-to-clean-page.*/ |
||||
|
||||
BITSET(R3, 7); /* mark as dirty*/
|
||||
[P3] = R3; /* and write back.*/
|
||||
CSYNC;
|
||||
( R7:0,P5:0 ) = [SP++];
|
||||
R0 = CPLB_RELOADED;
|
||||
RTS;
|
||||
|
||||
dcplb_miss_compare: |
||||
|
||||
/* Data CPLB Miss event. We need to choose a CPLB to |
||||
* evict, and then locate a new CPLB to install from the |
||||
* config table, that covers the faulting address. |
||||
*/ |
||||
|
||||
P1.L = (DCPLB_DATA15 & 0xFFFF);
|
||||
P1.H = (DCPLB_DATA15 >> 16);
|
||||
|
||||
P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
|
||||
P4.H = (DCPLB_FAULT_ADDR >> 16);
|
||||
R4 = [P4];
|
||||
I0 = R4;
|
||||
|
||||
/* The replacement procedure for DCPLBs*/ |
||||
|
||||
R6 = R1; /* Save for later*/
|
||||
|
||||
/* Turn off CPLBs while we work.*/ |
||||
P4.L = (DMEM_CONTROL & 0xFFFF);
|
||||
P4.H = (DMEM_CONTROL >> 16);
|
||||
R5 = [P4];
|
||||
BITCLR(R5,ENDCPLB_P);
|
||||
CLI R0;
|
||||
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
|
||||
.align 8;
|
||||
[P4] = R5;
|
||||
SSYNC;
|
||||
STI R0;
|
||||
|
||||
/* Start looking for a CPLB to evict. Our order of preference |
||||
* is: invalid CPLBs, clean CPLBs, dirty CPLBs. Locked CPLBs |
||||
* are no good. |
||||
*/ |
||||
|
||||
I1.L = (DCPLB_DATA0 & 0xFFFF);
|
||||
I1.H = (DCPLB_DATA0 >> 16);
|
||||
P1 = 3;
|
||||
P2 = 16;
|
||||
I2.L = dcplb_preference;
|
||||
I2.H = dcplb_preference;
|
||||
LSETUP(sdsearch1, edsearch1) LC0 = P1;
|
||||
sdsearch1: |
||||
R0 = [I2++]; /* Get the bits we're interested in*/
|
||||
P0 = I1; /* Go back to start of table*/
|
||||
LSETUP (sdsearch2, edsearch2) LC1 = P2;
|
||||
sdsearch2: |
||||
R1 = [P0++]; /* Fetch each installed CPLB in turn*/
|
||||
R2 = R1 & R0; /* and test for interesting bits.*/
|
||||
CC = R2 == 0; /* If none are set, it'll do.*/
|
||||
IF !CC JUMP skip_stack_check;
|
||||
|
||||
R2 = [P0 - 0x104]; /* R2 - PageStart */
|
||||
P3.L = page_size_table; /* retrive end address */
|
||||
P3.H = page_size_table; /* retrive end address */
|
||||
R3 = 0x2; /* 0th - position, 2 bits -length */
|
||||
nop; /*Anamoly 05000209*/
|
||||
R7 = EXTRACT(R1,R3.l);
|
||||
R7 = R7 << 2; /* Page size index offset */
|
||||
P5 = R7;
|
||||
P3 = P3 + P5;
|
||||
R7 = [P3]; /* page size in 1K bytes */
|
||||
|
||||
R7 = R7 << 0xA; /* in bytes * 1024*/
|
||||
R7 = R2 + R7; /* R7 - PageEnd */
|
||||
R4 = SP; /* Test SP is in range */
|
||||
|
||||
CC = R7 < R4; /* if PageEnd < SP */
|
||||
IF CC JUMP dfound_victim;
|
||||
R3 = 0x284; /* stack length from start of trap till the point */
|
||||
/* 20 stack locations for future modifications */ |
||||
R4 = R4 + R3;
|
||||
CC = R4 < R2; /* if SP + stacklen < PageStart */
|
||||
IF CC JUMP dfound_victim;
|
||||
skip_stack_check: |
||||
|
||||
edsearch2: NOP;
|
||||
edsearch1: NOP;
|
||||
|
||||
/* If we got here, we didn't find a DCPLB we considered |
||||
* replacable, which means all of them were locked. |
||||
*/ |
||||
|
||||
JUMP all_locked;
|
||||
dfound_victim: |
||||
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
R1 = [P0 - 0x104];
|
||||
P2.L = dpdt_table;
|
||||
P2.H = dpdt_table;
|
||||
P3.L = dpdt_swapcount_table;
|
||||
P3.H = dpdt_swapcount_table;
|
||||
P3 += -4;
|
||||
dicount: |
||||
R2 = [P2];
|
||||
P2 += 8;
|
||||
P3 += 8;
|
||||
CC = R2==-1;
|
||||
IF CC JUMP dicount_done;
|
||||
CC = R1==R2;
|
||||
IF !CC JUMP dicount;
|
||||
R1 = [P3];
|
||||
R1 += 1;
|
||||
[P3] = R1;
|
||||
CSYNC;
|
||||
dicount_done: |
||||
#endif |
||||
|
||||
/* Clean down the hardware loops*/ |
||||
R2 = 0;
|
||||
LC1 = R2;
|
||||
LC0 = R2;
|
||||
|
||||
/* There's a suitable victim in [P0-4] (because we've |
||||
* advanced already). If it's a valid dirty write-back |
||||
* CPLB, we need to flush the pending writes first. |
||||
*/ |
||||
|
||||
CC = BITTST(R1, 0); /* Is it valid?*/
|
||||
IF !CC JUMP Ddoverwrite;/* nope.*/
|
||||
CC = BITTST(R1, 7); /* Is it dirty?*/
|
||||
IF !CC JUMP Ddoverwrite (BP); /* Nope.*/
|
||||
CC = BITTST(R1, 14); /* Is it Write-Through?*/
|
||||
IF CC JUMP Ddoverwrite; /* Yep*/
|
||||
|
||||
/* This is a dirty page, so we need to flush all writes |
||||
* that are pending on the page. |
||||
*/ |
||||
|
||||
/* Retrieve the page start address*/ |
||||
R0 = [P0 - 0x104];
|
||||
[--sp] = rets;
|
||||
CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/
|
||||
rets = [sp++];
|
||||
Ddoverwrite: |
||||
|
||||
/* [P0-4] is a suitable victim CPLB, so we want to |
||||
* overwrite it by moving all the following CPLBs |
||||
* one space closer to the start. |
||||
*/ |
||||
|
||||
R1.L = ((DCPLB_DATA15+4) & 0xFFFF); /*DCPLB_DATA15+4*/
|
||||
R1.H = ((DCPLB_DATA15+4) >> 16);
|
||||
R0 = P0;
|
||||
|
||||
/* If the victim happens to be in DCPLB15, |
||||
* we don't need to move anything. |
||||
*/ |
||||
|
||||
CC = R1 == R0;
|
||||
IF CC JUMP de_moved;
|
||||
R1 = R1 - R0;
|
||||
R1 >>= 2;
|
||||
P1 = R1;
|
||||
LSETUP(ds_move, de_move) LC0=P1;
|
||||
ds_move: |
||||
R0 = [P0++]; /* move data */
|
||||
[P0 - 8] = R0;
|
||||
R0 = [P0-0x104] /* move address */ |
||||
de_move: [P0-0x108] = R0;
|
||||
|
||||
/* We've now made space in DCPLB15 for the new CPLB to be |
||||
* installed. The next stage is to locate a CPLB in the |
||||
* config table that covers the faulting address. |
||||
*/ |
||||
|
||||
de_moved:NOP;
|
||||
R0 = I0; /* Our faulting address */
|
||||
|
||||
P2.L = dpdt_table;
|
||||
P2.H = dpdt_table;
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
P3.L = dpdt_swapcount_table;
|
||||
P3.H = dpdt_swapcount_table;
|
||||
P3 += -8;
|
||||
#endif |
||||
|
||||
P1.L = page_size_table;
|
||||
P1.H = page_size_table;
|
||||
|
||||
/* An extraction pattern, to retrieve bits 17:16.*/ |
||||
|
||||
R1 = (16<<8)|2;
|
||||
dnext: R4 = [P2++]; /* address */
|
||||
R2 = [P2++]; /* data */
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
P3 += 8;
|
||||
#endif |
||||
|
||||
CC = R4 == -1;
|
||||
IF CC JUMP no_page_in_table;
|
||||
|
||||
/* See if failed address > start address */ |
||||
CC = R4 <= R0(IU);
|
||||
IF !CC JUMP dnext;
|
||||
|
||||
/* extract page size (17:16)*/ |
||||
R3 = EXTRACT(R2, R1.L) (Z);
|
||||
|
||||
/* add page size to addr to get range */ |
||||
|
||||
P5 = R3;
|
||||
P5 = P1 + (P5 << 2);
|
||||
R3 = [P5];
|
||||
R3 = R3 + R4;
|
||||
|
||||
/* See if failed address < (start address + page size) */ |
||||
CC = R0 < R3(IU);
|
||||
IF !CC JUMP dnext;
|
||||
|
||||
/* We've found the CPLB that should be installed, so |
||||
* write it into CPLB15, masking off any caching bits |
||||
* if necessary. |
||||
*/ |
||||
|
||||
P1.L = (DCPLB_DATA15 & 0xFFFF);
|
||||
P1.H = (DCPLB_DATA15 >> 16);
|
||||
|
||||
/* If the DCPLB has cache bits set, but caching hasn't |
||||
* been enabled, then we want to mask off the cache-in-L1 |
||||
* bit before installing. Moreover, if caching is off, we |
||||
* also want to ensure that the DCPLB has WT mode set, rather |
||||
* than WB, since WB pages still trigger first-write exceptions |
||||
* even when not caching is off, and the page isn't marked as |
||||
* cachable. Finally, we could mark the page as clean, not dirty, |
||||
* but we choose to leave that decision to the user; if the user
|
||||
* chooses to have a CPLB pre-defined as dirty, then they always |
||||
* pay the cost of flushing during eviction, but don't pay the |
||||
* cost of first-write exceptions to mark the page as dirty. |
||||
*/ |
||||
|
||||
#ifdef CONFIG_BLKFIN_WT |
||||
BITSET(R6, 14); /* Set WT*/
|
||||
#endif |
||||
|
||||
[P1] = R2;
|
||||
[P1-0x100] = R4;
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
R3 = [P3];
|
||||
R3 += 1;
|
||||
[P3] = R3;
|
||||
#endif |
||||
|
||||
/* We've installed the CPLB, so re-enable CPLBs. P4 |
||||
* points to DMEM_CONTROL, and R5 is the value we |
||||
* last wrote to it, when we were disabling CPLBs. |
||||
*/ |
||||
|
||||
BITSET(R5,ENDCPLB_P);
|
||||
CLI R2;
|
||||
.align 8;
|
||||
[P4] = R5;
|
||||
SSYNC;
|
||||
STI R2;
|
||||
|
||||
( R7:0,P5:0 ) = [SP++];
|
||||
R0 = CPLB_RELOADED;
|
||||
RTS;
|
||||
|
||||
.data |
||||
.align 4;
|
||||
page_size_table: |
||||
.byte4 0x00000400; /* 1K */
|
||||
.byte4 0x00001000; /* 4K */
|
||||
.byte4 0x00100000; /* 1M */
|
||||
.byte4 0x00400000; /* 4M */
|
||||
|
||||
.align 4;
|
||||
dcplb_preference: |
||||
.byte4 0x00000001; /* valid bit */
|
||||
.byte4 0x00000082; /* dirty+lock bits */
|
||||
.byte4 0x00000002; /* lock bit */
|
||||
@ -0,0 +1,180 @@ |
||||
#define ASSEMBLY |
||||
|
||||
#include <linux/config.h> |
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/mem_init.h> |
||||
.global init_sdram;
|
||||
|
||||
#if (CONFIG_CCLK_DIV == 1) |
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 |
||||
#endif |
||||
#if (CONFIG_CCLK_DIV == 2) |
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 |
||||
#endif |
||||
#if (CONFIG_CCLK_DIV == 4) |
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 |
||||
#endif |
||||
#if (CONFIG_CCLK_DIV == 8) |
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 |
||||
#endif |
||||
#ifndef CONFIG_CCLK_ACT_DIV |
||||
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly |
||||
#endif |
||||
|
||||
init_sdram: |
||||
[--SP] = ASTAT;
|
||||
[--SP] = RETS;
|
||||
[--SP] = (R7:0);
|
||||
[--SP] = (P5:0);
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||
p0.h = hi(SPI_BAUD);
|
||||
p0.l = lo(SPI_BAUD);
|
||||
r0.l = CONFIG_SPI_BAUD;
|
||||
w[p0] = r0.l;
|
||||
SSYNC;
|
||||
#endif |
||||
|
||||
/* |
||||
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable |
||||
*/ |
||||
p0.h = hi(PLL_LOCKCNT);
|
||||
p0.l = lo(PLL_LOCKCNT);
|
||||
r0 = 0x300(Z);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* Put SDRAM in self-refresh, incase anything is running |
||||
*/ |
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITSET (R0, 24);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/* |
||||
* Set PLL_CTL with the value that we calculate in R0 |
||||
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors |
||||
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK |
||||
* - [7] = output delay (add 200ps of delay to mem signals) |
||||
* - [6] = input delay (add 200ps of input delay to mem signals) |
||||
* - [5] = PDWN : 1=All Clocks off |
||||
* - [3] = STOPCK : 1=Core Clock off |
||||
* - [1] = PLL_OFF : 1=Disable Power to PLL |
||||
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL |
||||
* all other bits set to zero |
||||
*/ |
||||
|
||||
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||
r0 = r0 << 9; /* Shift it over, */
|
||||
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||
r0 = r1 | r0;
|
||||
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
|
||||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
p0.l = lo(PLL_CTL); /* Load the address */
|
||||
cli r2; /* Disable interrupts */
|
||||
ssync;
|
||||
w[p0] = r0.l; /* Set the value */
|
||||
idle; /* Wait for the PLL to stablize */
|
||||
sti r2; /* Enable interrupts */
|
||||
|
||||
check_again: |
||||
p0.h = hi(PLL_STAT);
|
||||
p0.l = lo(PLL_STAT);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0,5);
|
||||
if ! CC jump check_again;
|
||||
|
||||
/* Configure SCLK & CCLK Dividers */ |
||||
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||
p0.h = hi(PLL_DIV);
|
||||
p0.l = lo(PLL_DIV);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* We now are running at speed, time to set the Async mem bank wait states |
||||
* This will speed up execution, since we are normally running from FLASH. |
||||
*/ |
||||
|
||||
p2.h = (EBIU_AMBCTL1 >> 16);
|
||||
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
|
||||
r0.h = (AMBCTL1VAL >> 16);
|
||||
r0.l = (AMBCTL1VAL & 0xFFFF);
|
||||
[p2] = r0;
|
||||
ssync;
|
||||
|
||||
p2.h = (EBIU_AMBCTL0 >> 16);
|
||||
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
|
||||
r0.h = (AMBCTL0VAL >> 16);
|
||||
r0.l = (AMBCTL0VAL & 0xFFFF);
|
||||
[p2] = r0;
|
||||
ssync;
|
||||
|
||||
p2.h = (EBIU_AMGCTL >> 16);
|
||||
p2.l = (EBIU_AMGCTL & 0xffff);
|
||||
r0 = AMGCTLVAL;
|
||||
w[p2] = r0;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* Now, Initialize the SDRAM, |
||||
* start with the SDRAM Refresh Rate Control Register |
||||
*/ |
||||
p0.l = lo(EBIU_SDRRC);
|
||||
p0.h = hi(EBIU_SDRRC);
|
||||
r0 = mem_SDRRC;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* SDRAM Memory Bank Control Register - bank specific parameters |
||||
*/ |
||||
p0.l = (EBIU_SDBCTL & 0xFFFF);
|
||||
p0.h = (EBIU_SDBCTL >> 16);
|
||||
r0 = mem_SDBCTL;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* SDRAM Global Control Register - global programmable parameters |
||||
* Disable self-refresh |
||||
*/ |
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITCLR (R0, 24);
|
||||
|
||||
/* |
||||
* Check if SDRAM is already powered up, if it is, enable self-refresh |
||||
*/ |
||||
p0.h = hi(EBIU_SDSTAT);
|
||||
p0.l = lo(EBIU_SDSTAT);
|
||||
r2.l = w[p0];
|
||||
cc = bittst(r2,3);
|
||||
if !cc jump skip;
|
||||
NOP;
|
||||
BITSET (R0, 23);
|
||||
skip: |
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/* Write in the new value in the register */ |
||||
R0.L = lo(mem_SDGCTL);
|
||||
R0.H = hi(mem_SDGCTL);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
nop;
|
||||
|
||||
(P5:0) = [SP++];
|
||||
(R7:0) = [SP++];
|
||||
RETS = [SP++];
|
||||
ASTAT = [SP++];
|
||||
RTS;
|
||||
|
||||
@ -0,0 +1,181 @@ |
||||
#define ASSEMBLY |
||||
|
||||
#include <linux/config.h> |
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/mem_init.h> |
||||
.global init_sdram;
|
||||
|
||||
#if (CONFIG_CCLK_DIV == 1) |
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV1 |
||||
#endif |
||||
#if (CONFIG_CCLK_DIV == 2) |
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV2 |
||||
#endif |
||||
#if (CONFIG_CCLK_DIV == 4) |
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV4 |
||||
#endif |
||||
#if (CONFIG_CCLK_DIV == 8) |
||||
#define CONFIG_CCLK_ACT_DIV CCLK_DIV8 |
||||
#endif |
||||
#ifndef CONFIG_CCLK_ACT_DIV |
||||
#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly |
||||
#endif |
||||
|
||||
init_sdram: |
||||
[--SP] = ASTAT;
|
||||
[--SP] = RETS;
|
||||
[--SP] = (R7:0);
|
||||
[--SP] = (P5:0);
|
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
|
||||
p0.h = hi(SPI_BAUD);
|
||||
p0.l = lo(SPI_BAUD);
|
||||
r0.l = CONFIG_SPI_BAUD_INITBLOCK;
|
||||
w[p0] = r0.l;
|
||||
SSYNC;
|
||||
#endif |
||||
|
||||
/* |
||||
* PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable |
||||
*/ |
||||
p0.h = hi(PLL_LOCKCNT);
|
||||
p0.l = lo(PLL_LOCKCNT);
|
||||
r0 = 0x300(Z);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* Put SDRAM in self-refresh, incase anything is running |
||||
*/ |
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITSET (R0, 24);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/* |
||||
* Set PLL_CTL with the value that we calculate in R0 |
||||
* - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors |
||||
* - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK |
||||
* - [7] = output delay (add 200ps of delay to mem signals) |
||||
* - [6] = input delay (add 200ps of input delay to mem signals) |
||||
* - [5] = PDWN : 1=All Clocks off |
||||
* - [3] = STOPCK : 1=Core Clock off |
||||
* - [1] = PLL_OFF : 1=Disable Power to PLL |
||||
* - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL |
||||
* all other bits set to zero |
||||
*/ |
||||
|
||||
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
|
||||
r0 = r0 << 9; /* Shift it over, */
|
||||
r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
|
||||
r0 = r1 | r0;
|
||||
r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
|
||||
r1 = r1 << 8; /* Shift it over */
|
||||
r0 = r1 | r0; /* add them all together */
|
||||
|
||||
p0.h = hi(PLL_CTL);
|
||||
p0.l = lo(PLL_CTL); /* Load the address */
|
||||
cli r2; /* Disable interrupts */
|
||||
ssync;
|
||||
w[p0] = r0.l; /* Set the value */
|
||||
idle; /* Wait for the PLL to stablize */
|
||||
sti r2; /* Enable interrupts */
|
||||
|
||||
check_again: |
||||
p0.h = hi(PLL_STAT);
|
||||
p0.l = lo(PLL_STAT);
|
||||
R0 = W[P0](Z);
|
||||
CC = BITTST(R0,5);
|
||||
if ! CC jump check_again;
|
||||
|
||||
/* Configure SCLK & CCLK Dividers */ |
||||
r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
|
||||
p0.h = hi(PLL_DIV);
|
||||
p0.l = lo(PLL_DIV);
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* We now are running at speed, time to set the Async mem bank wait states |
||||
* This will speed up execution, since we are normally running from FLASH. |
||||
*/ |
||||
|
||||
p2.h = (EBIU_AMBCTL1 >> 16);
|
||||
p2.l = (EBIU_AMBCTL1 & 0xFFFF);
|
||||
r0.h = (AMBCTL1VAL >> 16);
|
||||
r0.l = (AMBCTL1VAL & 0xFFFF);
|
||||
[p2] = r0;
|
||||
ssync;
|
||||
|
||||
p2.h = (EBIU_AMBCTL0 >> 16);
|
||||
p2.l = (EBIU_AMBCTL0 & 0xFFFF);
|
||||
r0.h = (AMBCTL0VAL >> 16);
|
||||
r0.l = (AMBCTL0VAL & 0xFFFF);
|
||||
[p2] = r0;
|
||||
ssync;
|
||||
|
||||
p2.h = (EBIU_AMGCTL >> 16);
|
||||
p2.l = (EBIU_AMGCTL & 0xffff);
|
||||
r0 = AMGCTLVAL;
|
||||
w[p2] = r0;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* Now, Initialize the SDRAM, |
||||
* start with the SDRAM Refresh Rate Control Register |
||||
*/ |
||||
p0.l = lo(EBIU_SDRRC);
|
||||
p0.h = hi(EBIU_SDRRC);
|
||||
r0 = mem_SDRRC;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* SDRAM Memory Bank Control Register - bank specific parameters |
||||
*/ |
||||
p0.l = (EBIU_SDBCTL & 0xFFFF);
|
||||
p0.h = (EBIU_SDBCTL >> 16);
|
||||
r0 = mem_SDBCTL;
|
||||
w[p0] = r0.l;
|
||||
ssync;
|
||||
|
||||
/* |
||||
* SDRAM Global Control Register - global programmable parameters |
||||
* Disable self-refresh |
||||
*/ |
||||
P2.H = hi(EBIU_SDGCTL);
|
||||
P2.L = lo(EBIU_SDGCTL);
|
||||
R0 = [P2];
|
||||
BITCLR (R0, 24);
|
||||
|
||||
/* |
||||
* Check if SDRAM is already powered up, if it is, enable self-refresh |
||||
*/ |
||||
p0.h = hi(EBIU_SDSTAT);
|
||||
p0.l = lo(EBIU_SDSTAT);
|
||||
r2.l = w[p0];
|
||||
cc = bittst(r2,3);
|
||||
if !cc jump skip;
|
||||
NOP;
|
||||
BITSET (R0, 23);
|
||||
skip: |
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
|
||||
/* Write in the new value in the register */ |
||||
R0.L = lo(mem_SDGCTL);
|
||||
R0.H = hi(mem_SDGCTL);
|
||||
[P2] = R0;
|
||||
SSYNC;
|
||||
nop;
|
||||
|
||||
|
||||
(P5:0) = [SP++];
|
||||
(R7:0) = [SP++];
|
||||
RETS = [SP++];
|
||||
ASTAT = [SP++];
|
||||
RTS;
|
||||
|
||||
@ -0,0 +1,194 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it |
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, wd@denx.de |
||||
* (C) Copyright 2006 |
||||
* Aubrey Li, aubrey.li@analog.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <stdarg.h> |
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#include <i2c.h> |
||||
#include <linux/types.h> |
||||
#include <devices.h> |
||||
|
||||
#ifdef CONFIG_VIDEO |
||||
#define NTSC_FRAME_ADDR 0x06000000 |
||||
#include "video.h" |
||||
|
||||
/* NTSC OUTPUT SIZE 720 * 240 */ |
||||
#define VERTICAL 2 |
||||
#define HORIZONTAL 4 |
||||
|
||||
int is_vblank_line(const int line) |
||||
{ |
||||
/*
|
||||
* This array contains a single bit for each line in |
||||
* an NTSC frame.
|
||||
*/ |
||||
if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528)) |
||||
return true; |
||||
|
||||
return false; |
||||
} |
||||
|
||||
int NTSC_framebuffer_init(char *base_address) |
||||
{ |
||||
const int NTSC_frames = 1; |
||||
const int NTSC_lines = 525; |
||||
char *dest = base_address; |
||||
int frame_num, line_num; |
||||
|
||||
for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) { |
||||
for (line_num = 1; line_num <= NTSC_lines; ++line_num) { |
||||
unsigned int code; |
||||
int offset = 0; |
||||
int i; |
||||
|
||||
if (is_vblank_line(line_num)) |
||||
offset++; |
||||
|
||||
if (line_num > 266 || line_num < 3) |
||||
offset += 2; |
||||
|
||||
/* Output EAV code */ |
||||
code = SystemCodeMap[offset].EAV; |
||||
write_dest_byte((char)(code >> 24) & 0xff); |
||||
write_dest_byte((char)(code >> 16) & 0xff); |
||||
write_dest_byte((char)(code >> 8) & 0xff); |
||||
write_dest_byte((char)(code) & 0xff); |
||||
|
||||
/* Output horizontal blanking */ |
||||
for (i = 0; i < 67 * 2; ++i) { |
||||
write_dest_byte(0x80); |
||||
write_dest_byte(0x10); |
||||
} |
||||
|
||||
/* Output SAV */ |
||||
code = SystemCodeMap[offset].SAV; |
||||
write_dest_byte((char)(code >> 24) & 0xff); |
||||
write_dest_byte((char)(code >> 16) & 0xff); |
||||
write_dest_byte((char)(code >> 8) & 0xff); |
||||
write_dest_byte((char)(code) & 0xff); |
||||
|
||||
/* Output empty horizontal data */ |
||||
for (i = 0; i < 360 * 2; ++i) { |
||||
write_dest_byte(0x80); |
||||
write_dest_byte(0x10); |
||||
} |
||||
} |
||||
} |
||||
|
||||
return dest - base_address; |
||||
} |
||||
|
||||
void fill_frame(char *Frame, int Value) |
||||
{ |
||||
int *OddPtr32; |
||||
int OddLine; |
||||
int *EvenPtr32; |
||||
int EvenLine; |
||||
int i; |
||||
int *data; |
||||
int m, n; |
||||
|
||||
/* fill odd and even frames */ |
||||
for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) { |
||||
OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276); |
||||
EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276); |
||||
for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) { |
||||
*OddPtr32 = Value; |
||||
*EvenPtr32 = Value; |
||||
} |
||||
} |
||||
|
||||
for (m = 0; m < VERTICAL; m++) { |
||||
data = (int *)u_boot_logo.data; |
||||
for (OddLine = (22 + m), EvenLine = (285 + m); |
||||
OddLine < (u_boot_logo.height * VERTICAL) + (22 + m); |
||||
OddLine += VERTICAL, EvenLine += VERTICAL) { |
||||
OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276); |
||||
EvenPtr32 = |
||||
(int *)((Frame + ((EvenLine) * 1716)) + 276); |
||||
for (i = 0; i < u_boot_logo.width / 2; i++) { |
||||
/* enlarge one pixel to m x n */ |
||||
for (n = 0; n < HORIZONTAL; n++) { |
||||
*OddPtr32++ = *data; |
||||
*EvenPtr32++ = *data; |
||||
} |
||||
data++; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
void video_putc(const char c) |
||||
{ |
||||
} |
||||
|
||||
void video_puts(const char *s) |
||||
{ |
||||
} |
||||
|
||||
static int video_init(void) |
||||
{ |
||||
char *NTSCFrame; |
||||
NTSCFrame = (char *)NTSC_FRAME_ADDR; |
||||
NTSC_framebuffer_init(NTSCFrame); |
||||
fill_frame(NTSCFrame, BLUE); |
||||
|
||||
*pPPI_CONTROL = 0x0082; |
||||
*pPPI_FRAME = 0x020D; |
||||
|
||||
*pDMA0_START_ADDR = NTSCFrame; |
||||
*pDMA0_X_COUNT = 0x035A; |
||||
*pDMA0_X_MODIFY = 0x0002; |
||||
*pDMA0_Y_COUNT = 0x020D; |
||||
*pDMA0_Y_MODIFY = 0x0002; |
||||
*pDMA0_CONFIG = 0x1015; |
||||
*pPPI_CONTROL = 0x0083; |
||||
return 0; |
||||
} |
||||
|
||||
int drv_video_init(void) |
||||
{ |
||||
int error, devices = 1; |
||||
|
||||
device_t videodev; |
||||
|
||||
video_init(); /* Video initialization */ |
||||
|
||||
memset(&videodev, 0, sizeof(videodev)); |
||||
|
||||
strcpy(videodev.name, "video"); |
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ |
||||
videodev.flags = DEV_FLAGS_OUTPUT; /* Output only */ |
||||
videodev.putc = video_putc; /* 'putc' function */ |
||||
videodev.puts = video_puts; /* 'puts' function */ |
||||
|
||||
error = device_register(&videodev); |
||||
|
||||
return (error == 0) ? devices : error; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,25 @@ |
||||
#include <video_logo.h> |
||||
#define write_dest_byte(val) {*dest++=val;} |
||||
#define BLACK (0x01800180) /* black pixel pattern */ |
||||
#define BLUE (0x296E29F0) /* blue pixel pattern */ |
||||
#define RED (0x51F0515A) /* red pixel pattern */ |
||||
#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */ |
||||
#define GREEN (0x91229136) /* green pixel pattern */ |
||||
#define CYAN (0xAA10AAA6) /* cyan pixel pattern */ |
||||
#define YELLOW (0xD292D210) /* yellow pixel pattern */ |
||||
#define WHITE (0xFE80FE80) /* white pixel pattern */ |
||||
|
||||
#define true 1 |
||||
#define false 0 |
||||
|
||||
typedef struct { |
||||
unsigned int SAV; |
||||
unsigned int EAV; |
||||
} SystemCodeType; |
||||
|
||||
const SystemCodeType SystemCodeMap[4] = { |
||||
{0xFF000080, 0xFF00009D}, |
||||
{0xFF0000AB, 0xFF0000B6}, |
||||
{0xFF0000C7, 0xFF0000DA}, |
||||
{0xFF0000EC, 0xFF0000F1} |
||||
}; |
||||
@ -0,0 +1,172 @@ |
||||
/*
|
||||
* File: include/asm-blackfin/arch-bf533/anomaly.h |
||||
* Based on: |
||||
* Author: |
||||
* |
||||
* Created: |
||||
* Description: |
||||
* |
||||
* Rev: |
||||
* |
||||
* Modified: |
||||
* |
||||
* |
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2, or (at your option) |
||||
* any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; see the file COPYING. |
||||
* If not, write to the Free Software Foundation, |
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
||||
*/ |
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List |
||||
* - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List |
||||
* - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List |
||||
*/ |
||||
|
||||
#ifndef _MACH_ANOMALY_H_ |
||||
#define _MACH_ANOMALY_H_ |
||||
|
||||
/* We do not support 0.1 or 0.2 silicon - sorry */ |
||||
#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2)) |
||||
#error Kernel will not work on BF533 Version 0.1 or 0.2 |
||||
#endif |
||||
|
||||
/* Issues that are common to 0.5, 0.4, and 0.3 silicon */ |
||||
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) |
||||
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in |
||||
slot1 and store of a P register in slot 2 is not |
||||
supported */ |
||||
#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on |
||||
every corresponding match */ |
||||
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive |
||||
Channel DMA stops */ |
||||
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR |
||||
registers. */ |
||||
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out |
||||
upper bits*/ |
||||
#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */ |
||||
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame |
||||
syncs */ |
||||
#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not |
||||
functional */ |
||||
#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable |
||||
state */ |
||||
#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */ |
||||
#define ANOMALY_05000272 /* Certain data cache write through modes fail for |
||||
VDDint <=0.9V */ |
||||
#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */ |
||||
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after |
||||
an edge is detected may clear interrupt */ |
||||
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause |
||||
DMA system instability */ |
||||
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is |
||||
not restored */ |
||||
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic |
||||
control */ |
||||
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when |
||||
killed in a particular stage*/ |
||||
#endif |
||||
|
||||
/* These issues only occur on 0.3 or 0.4 BF533 */ |
||||
#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3)) |
||||
#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not |
||||
updated at the same time. */ |
||||
#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data |
||||
Cache Fill can be corrupted after or during |
||||
Instruction DMA if certain core stalls exist */ |
||||
#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General |
||||
Purpose TX or RX modes */ |
||||
#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by |
||||
preceding memory read */ |
||||
#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during |
||||
inactive channels in certain conditions */ |
||||
#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag |
||||
situation */ |
||||
#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */ |
||||
#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */ |
||||
#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect |
||||
data*/ |
||||
#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate |
||||
Differences in certain Conditions */ |
||||
#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */ |
||||
#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to |
||||
hardware reset */ |
||||
#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or |
||||
IDLE around a Change of Control causes |
||||
unpredictable results */ |
||||
#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the |
||||
shadow of a conditional branch */ |
||||
#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware |
||||
errors */ |
||||
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ |
||||
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event |
||||
interrupt not functional */ |
||||
#define ANOMALY_05000257 /* An interrupt or exception during short Hardware |
||||
loops may cause the instruction fetch unit to |
||||
malfunction */ |
||||
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of |
||||
the ICPLB Data registers differ */ |
||||
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */ |
||||
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */ |
||||
#define ANOMALY_05000262 /* Stores to data cache may be lost */ |
||||
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */ |
||||
#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE |
||||
instruction will cause an infinite stall in the |
||||
second to last instruction in a hardware loop */ |
||||
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on |
||||
SPORT external receive and transmit clocks. */ |
||||
#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the |
||||
internal voltage regulator (VDDint) to increase. */ |
||||
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the |
||||
internal voltage regulator (VDDint) to decrease */ |
||||
#endif |
||||
|
||||
/* These issues are only on 0.4 silicon */ |
||||
#if (defined(CONFIG_BF_REV_0_4)) |
||||
#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */ |
||||
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel |
||||
(TDM) */ |
||||
#endif |
||||
|
||||
/* These issues are only on 0.3 silicon */ |
||||
#if defined(CONFIG_BF_REV_0_3) |
||||
#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with |
||||
External Frame Syncs */ |
||||
#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative |
||||
Instruction or Data Fetches, or by Fetches at the |
||||
boundary of reserved memory space */ |
||||
#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs |
||||
when polarity setting is changed */ |
||||
#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data |
||||
corruption */ |
||||
#define ANOMALY_05000199 /* DMA current address shows wrong value during carry |
||||
fix */ |
||||
#define ANOMALY_05000201 /* Receive frame sync not ignored during active |
||||
frames in sport MCM */ |
||||
#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA |
||||
stopping */ |
||||
#if defined(CONFIG_BF533) |
||||
#define ANOMALY_05000204 /* Incorrect data read with write-through cache and |
||||
allocate cache lines on reads only mode */ |
||||
#endif /* CONFIG_BF533 */ |
||||
#define ANOMALY_05000207 /* Recovery from "brown-out" condition */ |
||||
#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain |
||||
instructions */ |
||||
#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame |
||||
Sync Transmit Mode */ |
||||
#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */ |
||||
#endif |
||||
|
||||
#endif /* _MACH_ANOMALY_H_ */ |
||||
@ -0,0 +1,482 @@ |
||||
/*This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. |
||||
* |
||||
* Blackfin BF533/2.6 support : LG Soft India |
||||
* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd |
||||
* Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's |
||||
* shouldn't be victimized. cplbmgr.S search logic is corrected |
||||
* to findout the appropriate victim. |
||||
* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC |
||||
* : LG Soft India |
||||
*/ |
||||
#include <config.h> |
||||
|
||||
#ifndef __ARCH_BFINNOMMU_CPLBTAB_H |
||||
#define __ARCH_BFINNOMMU_CPLBTAB_H |
||||
|
||||
/*************************************************************************
|
||||
* ICPLB TABLE |
||||
*************************************************************************/ |
||||
|
||||
.data |
||||
/* This table is configurable */ |
||||
.align 4; |
||||
|
||||
/* Data Attibutes*/ |
||||
|
||||
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) |
||||
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) |
||||
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) |
||||
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) |
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ |
||||
|
||||
#define ANOMALY_05000158 0x200 |
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ |
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) |
||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) |
||||
|
||||
#else /*Write Through */ |
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) |
||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) |
||||
#endif |
||||
|
||||
.align 4; |
||||
.global _ipdt_table _ipdt_table:.byte4 0x00000000; |
||||
.byte4(SDRAM_IKERNEL); /*SDRAM_Page0 */ |
||||
.byte4 0x00400000; |
||||
.byte4(SDRAM_IKERNEL); /*SDRAM_Page1 */ |
||||
.byte4 0x00800000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page2 */ |
||||
.byte4 0x00C00000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page3 */ |
||||
.byte4 0x01000000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page4 */ |
||||
.byte4 0x01400000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page5 */ |
||||
.byte4 0x01800000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page6 */ |
||||
.byte4 0x01C00000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page7 */ |
||||
#ifndef CONFIG_EZKIT /*STAMP Memory regions */ |
||||
.byte4 0x02000000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page8 */ |
||||
.byte4 0x02400000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page9 */ |
||||
.byte4 0x02800000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page10 */ |
||||
.byte4 0x02C00000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page11 */ |
||||
.byte4 0x03000000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page12 */ |
||||
.byte4 0x03400000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page13 */ |
||||
.byte4 0x03800000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page14 */ |
||||
.byte4 0x03C00000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page15 */ |
||||
#endif |
||||
.byte4 0x20000000; |
||||
.byte4(SDRAM_EBIU); /* Async Memory Bank 2 (Secnd) */ |
||||
|
||||
#ifdef CONFIG_STAMP |
||||
.byte4 0x04000000; |
||||
.byte4(SDRAM_IGENERIC); |
||||
.byte4 0x04400000; |
||||
.byte4(SDRAM_IGENERIC); |
||||
.byte4 0x04800000; |
||||
.byte4(SDRAM_IGENERIC); |
||||
.byte4 0x04C00000; |
||||
.byte4(SDRAM_IGENERIC); |
||||
.byte4 0x05000000; |
||||
.byte4(SDRAM_IGENERIC); |
||||
.byte4 0x05400000; |
||||
.byte4(SDRAM_IGENERIC); |
||||
.byte4 0x05800000; |
||||
.byte4(SDRAM_IGENERIC); |
||||
.byte4 0x05C00000; |
||||
.byte4(SDRAM_IGENERIC); |
||||
.byte4 0x06000000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page25 */ |
||||
.byte4 0x06400000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page26 */ |
||||
.byte4 0x06800000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page27 */ |
||||
.byte4 0x06C00000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page28 */ |
||||
.byte4 0x07000000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page29 */ |
||||
.byte4 0x07400000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page30 */ |
||||
.byte4 0x07800000; |
||||
.byte4(SDRAM_IGENERIC); /*SDRAM_Page31 */ |
||||
.byte4 0x07C00000; |
||||
.byte4(SDRAM_IKERNEL); /*SDRAM_Page32 */ |
||||
#endif |
||||
.byte4 0xffffffff; /* end of section - termination */ |
||||
|
||||
/**********************************************************************
|
||||
* PAGE DESCRIPTOR TABLE |
||||
* |
||||
**********************************************************************/ |
||||
|
||||
/* Till here we are discussing about the static memory management model.
|
||||
* However, the operating envoronments commonly define more CPLB |
||||
* descriptors to cover the entire addressable memory than will fit into |
||||
* the available on-chip 16 CPLB MMRs. When this happens, the below table |
||||
* will be used which will hold all the potentially required CPLB descriptors |
||||
* |
||||
* This is how Page descriptor Table is implemented in uClinux/Blackfin. |
||||
*/ |
||||
.global _dpdt_table _dpdt_table:.byte4 0x00000000; |
||||
.byte4(SDRAM_DKERNEL); /*SDRAM_Page0 */ |
||||
.byte4 0x00400000; |
||||
.byte4(SDRAM_DKERNEL); /*SDRAM_Page1 */ |
||||
.byte4 0x00800000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page2 */ |
||||
.byte4 0x00C00000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page3 */ |
||||
.byte4 0x01000000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page4 */ |
||||
.byte4 0x01400000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page5 */ |
||||
.byte4 0x01800000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page6 */ |
||||
.byte4 0x01C00000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page7 */ |
||||
|
||||
#ifndef CONFIG_EZKIT |
||||
.byte4 0x02000000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page8 */ |
||||
.byte4 0x02400000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page9 */ |
||||
.byte4 0x02800000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page10 */ |
||||
.byte4 0x02C00000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page11 */ |
||||
.byte4 0x03000000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page12 */ |
||||
.byte4 0x03400000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page13 */ |
||||
.byte4 0x03800000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page14 */ |
||||
.byte4 0x03C00000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page15 */ |
||||
#endif |
||||
|
||||
#ifdef CONFIG_STAMP |
||||
.byte4 0x04000000; |
||||
.byte4(SDRAM_DGENERIC); |
||||
.byte4 0x04400000; |
||||
.byte4(SDRAM_DGENERIC); |
||||
.byte4 0x04800000; |
||||
.byte4(SDRAM_DGENERIC); |
||||
.byte4 0x04C00000; |
||||
.byte4(SDRAM_DGENERIC); |
||||
.byte4 0x05000000; |
||||
.byte4(SDRAM_DGENERIC); |
||||
.byte4 0x05400000; |
||||
.byte4(SDRAM_DGENERIC); |
||||
.byte4 0x05800000; |
||||
.byte4(SDRAM_DGENERIC); |
||||
.byte4 0x05C00000; |
||||
.byte4(SDRAM_DGENERIC); |
||||
.byte4 0x06000000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page25 */ |
||||
.byte4 0x06400000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page26 */ |
||||
.byte4 0x06800000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page27 */ |
||||
.byte4 0x06C00000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page28 */ |
||||
.byte4 0x07000000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page29 */ |
||||
.byte4 0x07400000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page30 */ |
||||
.byte4 0x07800000; |
||||
.byte4(SDRAM_DGENERIC); /*SDRAM_Page31 */ |
||||
.byte4 0x07C00000; |
||||
.byte4(SDRAM_DKERNEL); /*SDRAM_Page32 */ |
||||
#endif |
||||
|
||||
.byte4 0x20000000; |
||||
.byte4(SDRAM_EBIU); /* Async Memory Bank 0 (Prim A) */ |
||||
|
||||
#if (BFIN_CPU == ADSP_BF533) |
||||
.byte4 0xFF800000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF801000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF802000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF803000; |
||||
.byte4(L1_DMEMORY); |
||||
#endif |
||||
.byte4 0xFF804000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF805000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF806000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF807000; |
||||
.byte4(L1_DMEMORY); |
||||
#if (BFIN_CPU == ADSP_BF533) |
||||
.byte4 0xFF900000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF901000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF902000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF903000; |
||||
.byte4(L1_DMEMORY); |
||||
#endif |
||||
#if ((BFIN_CPU == ADSP_BF532) || (BFIN_CPU == ADSP_BF533)) |
||||
.byte4 0xFF904000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF905000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF906000; |
||||
.byte4(L1_DMEMORY); |
||||
.byte4 0xFF907000; |
||||
.byte4(L1_DMEMORY); |
||||
#endif |
||||
.byte4 0xFFB00000; |
||||
.byte4(L1_DMEMORY); |
||||
|
||||
.byte4 0xffffffff; /*end of section - termination */ |
||||
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
.global _ipdt_swapcount_table; /* swapin count first, then swapout count */ |
||||
_ipdt_swapcount_table: |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 10 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 20 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 30 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 40 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 50 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 60 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 70 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 80 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 90 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 100 */ |
||||
|
||||
.global _dpdt_swapcount_table; /* swapin count first, then swapout count */ |
||||
_dpdt_swapcount_table: |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 10 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 20 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 30 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 40 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 50 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 60 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 70 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 80 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 80 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 100 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 110 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 120 */ |
||||
#endif |
||||
|
||||
#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ |
||||
@ -0,0 +1,46 @@ |
||||
/*
|
||||
* U-boot - bf533_rtc.h |
||||
* |
||||
* Copyright (c) 2005 blackfin.uclinux.org |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _BF533_RTC_H_ |
||||
#define _BF533_RTC_H_ |
||||
|
||||
void rtc_init(void); |
||||
void wait_for_complete(void); |
||||
void rtc_reset(void); |
||||
|
||||
#define MIN_TO_SECS(_x_) (60 * _x_) |
||||
#define HRS_TO_SECS(_x_) (60 * 60 * _x_) |
||||
#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_) |
||||
|
||||
#define NUM_SECS_IN_DAY (24 * 3600) |
||||
#define NUM_SECS_IN_HOUR (3600) |
||||
#define NUM_SECS_IN_MIN (60) |
||||
|
||||
/* Shift values for RTC_STAT register */ |
||||
#define DAY_BITS_OFF 17 |
||||
#define HOUR_BITS_OFF 12 |
||||
#define MIN_BITS_OFF 6 |
||||
#define SEC_BITS_OFF 0 |
||||
|
||||
#endif |
||||
@ -0,0 +1,40 @@ |
||||
/************************************************************************
|
||||
* |
||||
* cdefBF53x.h |
||||
* |
||||
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. |
||||
* |
||||
************************************************************************/ |
||||
|
||||
#ifndef _CDEFBF53x_H |
||||
#define _CDEFBF53x_H |
||||
|
||||
#if defined(__ADSPBF531__) |
||||
#include <asm/arch-bf533/cdefBF531.h> |
||||
#elif defined(__ADSPBF532__) |
||||
#include <asm/arch-bf533/cdefBF532.h> |
||||
#elif defined(__ADSPBF533__) |
||||
#include <asm/arch-bf533/cdefBF533.h> |
||||
#include <asm/arch-bf533/defBF533_extn.h> |
||||
#include <asm/arch-bf533/bf533_serial.h> |
||||
#elif defined(__ADSPBF537__) |
||||
#include <asm/arch-bf537/cdefBF537.h> |
||||
#include <asm/arch-bf537/defBF537_extn.h> |
||||
#include <asm/arch-bf537/bf537_serial.h> |
||||
#elif defined(__ADSPBF561__) |
||||
#include <asm/arch-bf561/cdefBF561.h> |
||||
#include <asm/arch-bf561/defBF561_extn.h> |
||||
#include <asm/arch-bf561/bf561_serial.h> |
||||
#elif defined(__ADSPBF535__) |
||||
#include <asm/cpu/cdefBF5d35.h> |
||||
#elif defined(__AD6532__) |
||||
#include <asm/cpu/cdefAD6532.h> |
||||
#else |
||||
#if defined(__ADSPLPBLACKFIN__) |
||||
#include <asm/arch-bf533/cdefBF532.h> |
||||
#else |
||||
#include <asm/arch-bf533/cdefBF535.h> |
||||
#endif |
||||
#endif |
||||
|
||||
#endif /* _CDEFBF53x_H */ |
||||
@ -1,572 +0,0 @@ |
||||
/*This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. |
||||
* |
||||
* Blackfin BF533/2.6 support : LG Soft India |
||||
* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd |
||||
* Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's |
||||
* shouldn't be victimized. cplbmgr.S search logic is corrected |
||||
* to findout the appropriate victim. |
||||
* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC |
||||
* : LG Soft India |
||||
*/ |
||||
#include <config.h> |
||||
|
||||
#ifndef __ARCH_BFINNOMMU_CPLBTAB_H |
||||
#define __ARCH_BFINNOMMU_CPLBTAB_H |
||||
|
||||
/*************************************************************************
|
||||
* ICPLB TABLE |
||||
*************************************************************************/ |
||||
|
||||
.data |
||||
|
||||
/* This table is configurable */ |
||||
|
||||
.align 4; |
||||
|
||||
/* Data Attibutes*/ |
||||
|
||||
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) |
||||
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) |
||||
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) |
||||
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) |
||||
|
||||
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ |
||||
|
||||
#define ANOMALY_05000158 0x200 |
||||
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ |
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) |
||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) |
||||
|
||||
#else /*Write Through*/ |
||||
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) |
||||
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) |
||||
#define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) |
||||
#endif |
||||
|
||||
.global icplb_table |
||||
icplb_table: |
||||
.byte4 0xFFA00000; |
||||
.byte4 (L1_IMEMORY); |
||||
.byte4 0x00000000; |
||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ |
||||
.byte4 0x00400000; |
||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ |
||||
.byte4 0x07C00000; |
||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/ |
||||
.byte4 0x00800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ |
||||
.byte4 0x00C00000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ |
||||
.byte4 0x01000000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ |
||||
.byte4 0x01400000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ |
||||
.byte4 0x01800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ |
||||
.byte4 0x01C00000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ |
||||
#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ |
||||
.byte4 0x02000000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ |
||||
.byte4 0x02400000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ |
||||
.byte4 0x02800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ |
||||
.byte4 0x02C00000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ |
||||
.byte4 0x03000000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ |
||||
.byte4 0x03400000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ |
||||
#endif |
||||
.byte4 0xffffffff; /* end of section - termination*/ |
||||
|
||||
.align 4; |
||||
.global ipdt_table |
||||
ipdt_table: |
||||
#ifdef CONFIG_CPLB_INFO |
||||
.byte4 0x00000000; |
||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/ |
||||
.byte4 0x00400000; |
||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/ |
||||
#endif |
||||
.byte4 0x00800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/ |
||||
.byte4 0x00C00000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/ |
||||
.byte4 0x01000000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/ |
||||
.byte4 0x01400000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/ |
||||
.byte4 0x01800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/ |
||||
.byte4 0x01C00000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/ |
||||
#ifndef CONFIG_EZKIT /*STAMP Memory regions*/ |
||||
.byte4 0x02000000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/ |
||||
.byte4 0x02400000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/ |
||||
.byte4 0x02800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/ |
||||
.byte4 0x02C00000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/ |
||||
.byte4 0x03000000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/ |
||||
.byte4 0x03400000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/ |
||||
.byte4 0x03800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/ |
||||
.byte4 0x03C00000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/ |
||||
#endif |
||||
.byte4 0x20200000; |
||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ |
||||
.byte4 0x20100000; |
||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ |
||||
.byte4 0x20000000; |
||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ |
||||
.byte4 0x20300000; /*Fix for Network*/ |
||||
.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ |
||||
|
||||
#ifdef CONFIG_STAMP |
||||
.byte4 0x04000000; |
||||
.byte4 (SDRAM_IGENERIC); |
||||
.byte4 0x04400000; |
||||
.byte4 (SDRAM_IGENERIC); |
||||
.byte4 0x04800000; |
||||
.byte4 (SDRAM_IGENERIC); |
||||
.byte4 0x04C00000; |
||||
.byte4 (SDRAM_IGENERIC); |
||||
.byte4 0x05000000; |
||||
.byte4 (SDRAM_IGENERIC); |
||||
.byte4 0x05400000; |
||||
.byte4 (SDRAM_IGENERIC); |
||||
.byte4 0x05800000; |
||||
.byte4 (SDRAM_IGENERIC); |
||||
.byte4 0x05C00000; |
||||
.byte4 (SDRAM_IGENERIC); |
||||
.byte4 0x06000000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/ |
||||
.byte4 0x06400000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/ |
||||
.byte4 0x06800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/ |
||||
.byte4 0x06C00000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/ |
||||
.byte4 0x07000000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/ |
||||
.byte4 0x07400000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/ |
||||
.byte4 0x07800000; |
||||
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/ |
||||
#ifdef CONFIG_CPLB_INFO |
||||
.byte4 0x07C00000; |
||||
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/ |
||||
#endif |
||||
#endif |
||||
.byte4 0xffffffff; /* end of section - termination*/ |
||||
|
||||
/*********************************************************************
|
||||
* DCPLB TABLE |
||||
********************************************************************/ |
||||
|
||||
.global dcplb_table |
||||
dcplb_table: |
||||
.byte4 0x00000000; |
||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ |
||||
.byte4 0x00400000; |
||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ |
||||
.byte4 0x07C00000; |
||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/ |
||||
.byte4 0x00800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ |
||||
.byte4 0x00C00000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ |
||||
.byte4 0x01000000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ |
||||
.byte4 0x01400000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ |
||||
.byte4 0x01800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ |
||||
.byte4 0x01C00000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ |
||||
#ifndef CONFIG_EZKIT |
||||
.byte4 0x02000000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ |
||||
.byte4 0x02400000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ |
||||
.byte4 0x02800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ |
||||
.byte4 0x02C00000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ |
||||
.byte4 0x03000000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ |
||||
.byte4 0x03400000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ |
||||
.byte4 0x03800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ |
||||
#endif |
||||
.byte4 0xffffffff; /*end of section - termination*/ |
||||
|
||||
/**********************************************************************
|
||||
* PAGE DESCRIPTOR TABLE |
||||
* |
||||
**********************************************************************/ |
||||
|
||||
/* Till here we are discussing about the static memory management model.
|
||||
* However, the operating envoronments commonly define more CPLB |
||||
* descriptors to cover the entire addressable memory than will fit into |
||||
* the available on-chip 16 CPLB MMRs. When this happens, the below table |
||||
* will be used which will hold all the potentially required CPLB descriptors |
||||
* |
||||
* This is how Page descriptor Table is implemented in uClinux/Blackfin. |
||||
*/ |
||||
.global dpdt_table |
||||
dpdt_table: |
||||
#ifdef CONFIG_CPLB_INFO |
||||
.byte4 0x00000000; |
||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/ |
||||
.byte4 0x00400000; |
||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/ |
||||
#endif |
||||
.byte4 0x00800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/ |
||||
.byte4 0x00C00000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/ |
||||
.byte4 0x01000000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/ |
||||
.byte4 0x01400000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/ |
||||
.byte4 0x01800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/ |
||||
.byte4 0x01C00000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/ |
||||
|
||||
#ifndef CONFIG_EZKIT |
||||
.byte4 0x02000000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/ |
||||
.byte4 0x02400000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/ |
||||
.byte4 0x02800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/ |
||||
.byte4 0x02C00000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/ |
||||
.byte4 0x03000000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/ |
||||
.byte4 0x03400000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/ |
||||
.byte4 0x03800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/ |
||||
.byte4 0x03C00000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/ |
||||
#endif |
||||
.byte4 0x20200000; |
||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/ |
||||
.byte4 0x20100000; |
||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/ |
||||
.byte4 0x20000000; |
||||
.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/ |
||||
.byte4 0x20300000; /*Fix for Network*/ |
||||
.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/ |
||||
|
||||
#ifdef CONFIG_STAMP |
||||
.byte4 0x04000000; |
||||
.byte4 (SDRAM_DGENERIC); |
||||
.byte4 0x04400000; |
||||
.byte4 (SDRAM_DGENERIC); |
||||
.byte4 0x04800000; |
||||
.byte4 (SDRAM_DGENERIC); |
||||
.byte4 0x04C00000; |
||||
.byte4 (SDRAM_DGENERIC); |
||||
.byte4 0x05000000; |
||||
.byte4 (SDRAM_DGENERIC); |
||||
.byte4 0x05400000; |
||||
.byte4 (SDRAM_DGENERIC); |
||||
.byte4 0x05800000; |
||||
.byte4 (SDRAM_DGENERIC); |
||||
.byte4 0x05C00000; |
||||
.byte4 (SDRAM_DGENERIC); |
||||
.byte4 0x06000000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/ |
||||
.byte4 0x06400000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/ |
||||
.byte4 0x06800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/ |
||||
.byte4 0x06C00000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/ |
||||
.byte4 0x07000000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/ |
||||
.byte4 0x07400000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/ |
||||
.byte4 0x07800000; |
||||
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/ |
||||
#ifdef CONFIG_CPLB_INFO |
||||
.byte4 0x07C00000; |
||||
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/ |
||||
#endif |
||||
#endif |
||||
|
||||
.byte4 0xFF900000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF901000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF902000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF903000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF904000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF905000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF906000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF907000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF800000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF801000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF802000; |
||||
.byte4 (L1_DMEMORY); |
||||
.byte4 0xFF803000; |
||||
.byte4 (L1_DMEMORY); |
||||
|
||||
.byte4 0xffffffff; /*end of section - termination*/ |
||||
|
||||
#ifdef CONFIG_CPLB_INFO |
||||
.global ipdt_swapcount_table; /* swapin count first, then swapout count*/ |
||||
ipdt_swapcount_table: |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 10 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 20 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 30 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 40 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 50 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 60 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 70 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 80 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 90 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 100 */ |
||||
|
||||
.global dpdt_swapcount_table; /* swapin count first, then swapout count*/ |
||||
dpdt_swapcount_table: |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 10 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 20 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 30 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 40 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 50 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 60 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 70 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 80 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 80 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 100 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 110 */ |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; |
||||
.byte4 0x00000000; /* 120 */ |
||||
|
||||
#endif |
||||
|
||||
#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/ |
||||
@ -1,32 +0,0 @@ |
||||
/************************************************************************
|
||||
* |
||||
* cdefBF53x.h |
||||
* |
||||
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved. |
||||
* |
||||
************************************************************************/ |
||||
|
||||
#ifndef _CDEFBF53x_H |
||||
#define _CDEFBF53x_H |
||||
|
||||
#if defined(__ADSPBF531__) |
||||
#include <asm/cpu/cdefBF531.h> |
||||
#elif defined(__ADSPBF532__) |
||||
#include <asm/cpu/cdefBF532.h> |
||||
#elif defined(__ADSPBF533__) |
||||
#include <asm/cpu/cdefBF533.h> |
||||
#elif defined(__ADSPBF561__) |
||||
#include <asm/cpu/cdefBF561.h> |
||||
#elif defined(__ADSPBF535__) |
||||
#include <asm/cpu/cdefBF535.h> |
||||
#elif defined(__AD6532__) |
||||
#include <sam/cpu/cdefAD6532.h> |
||||
#else |
||||
#if defined(__ADSPLPBLACKFIN__) |
||||
#include <asm/cpu/cdefBF532.h> |
||||
#else |
||||
#include <asm/cpu/cdefBF535.h> |
||||
#endif |
||||
#endif |
||||
|
||||
#endif /* _CDEFBF53x_H */ |
||||
@ -0,0 +1,228 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF533 EZKIT board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_EZKIT533_H__ |
||||
#define __CONFIG_EZKIT533_H__ |
||||
|
||||
#define CONFIG_BAUDRATE 57600 |
||||
#define CONFIG_STAMP 1 |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ |
||||
|
||||
#define CFG_LONGHELP 1 |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
#define CONFIG_LOADADDR 0x01000000 /* default load address */ |
||||
#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux" |
||||
//#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
|
||||
|
||||
#define CONFIG_DRIVER_SMC91111 1 |
||||
#define CONFIG_SMC91111_BASE 0x20310300 |
||||
|
||||
#if 0 |
||||
#define CONFIG_MII |
||||
#define CFG_DISCOVER_PHY |
||||
#endif |
||||
|
||||
#define CONFIG_RTC_BFIN 1 |
||||
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ |
||||
|
||||
/*
|
||||
* Boot Mode Set |
||||
* Blackfin can support several boot modes |
||||
*/ |
||||
#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ |
||||
#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ |
||||
#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ |
||||
/* Define the boot mode */ |
||||
#define BFIN_BOOT_MODE BF533_BYPASS_BOOT |
||||
//#define BFIN_BOOT_MODE BF533_SPI_BOOT
|
||||
|
||||
#define CONFIG_PANIC_HANG 1 |
||||
|
||||
#define ADSP_BF531 0x31 |
||||
#define ADSP_BF532 0x32 |
||||
#define ADSP_BF533 0x33 |
||||
#define BFIN_CPU ADSP_BF533 |
||||
|
||||
/* This sets the default state of the cache on U-Boot's boot */ |
||||
#define CONFIG_ICACHE_ON |
||||
#define CONFIG_DCACHE_ON |
||||
|
||||
/* Define where the uboot will be loaded by on-chip boot rom */ |
||||
#define APP_ENTRY 0x00001000 |
||||
|
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 27000000 |
||||
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ |
||||
/* 1=CLKIN/2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ |
||||
/* 1=bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ |
||||
/* Values can range from 1-64 */ |
||||
#define CONFIG_VCO_MULT 22 |
||||
/* CONFIG_CCLK_DIV controls what the core clock divider is */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 5 |
||||
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ |
||||
/* Values can range from 2-65535 */ |
||||
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ |
||||
#define CONFIG_SPI_BAUD 2 |
||||
#define CONFIG_SPI_BAUD_INITBLOCK 4 |
||||
|
||||
#if ( CONFIG_CLKIN_HALF == 0 ) |
||||
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) |
||||
#else |
||||
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) |
||||
#endif |
||||
|
||||
#if (CONFIG_PLL_BYPASS == 0) |
||||
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) |
||||
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) |
||||
#else |
||||
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ |
||||
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ |
||||
#endif |
||||
|
||||
#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ |
||||
#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ |
||||
#define CONFIG_MEM_MT48LC16M16A2TG_75 1 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 |
||||
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_DATE) |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600" |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */ |
||||
#define CFG_LOAD_ADDR 0x01000000 /* default load address */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) |
||||
#define CFG_FLASH_BASE 0x20000000 |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) |
||||
#define CFG_GBL_DATA_SIZE 0x4000 |
||||
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) |
||||
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) |
||||
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
#define CFG_FLASH0_BASE 0x20000000 |
||||
#define CFG_FLASH1_BASE 0x20200000 |
||||
#define CFG_FLASH2_BASE 0x20280000 |
||||
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR 0x20020000 |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
|
||||
/* JFFS Partition offset set */ |
||||
#define CFG_JFFS2_FIRST_BANK 0 |
||||
#define CFG_JFFS2_NUM_BANKS 1 |
||||
/* 512k reserved for u-boot */ |
||||
#define CFG_JFFS2_FIRST_SECTOR 11 |
||||
|
||||
|
||||
/*
|
||||
* Stack sizes |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
|
||||
#define POLL_MODE 1 |
||||
#define FLASH_TOT_SECT 40 |
||||
#define FLASH_SIZE 0x220000 |
||||
#define CFG_FLASH_SIZE 0x220000 |
||||
|
||||
/*
|
||||
* Initialize PSD4256 registers for using I2C |
||||
*/ |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* I2C settings |
||||
* By default PF1 is used as SDA and PF0 as SCL on the Stamp board |
||||
*/ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PF_SCL PF0 |
||||
#define PF_SDA PF1 |
||||
|
||||
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") |
||||
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") |
||||
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") |
||||
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") |
||||
#define I2C_SDA(bit) if(bit) { \ |
||||
*pFIO_FLAG_S = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} |
||||
#define I2C_SCL(bit) if(bit) { \ |
||||
*pFIO_FLAG_S = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CFG_I2C_SPEED 50000 |
||||
#define CFG_I2C_SLAVE 0xFE |
||||
|
||||
#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ |
||||
|
||||
/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ |
||||
/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
||||
#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ |
||||
~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) |
||||
#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ |
||||
B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) |
||||
*/ |
||||
#define AMGCTLVAL 0xFF |
||||
#define AMBCTL0VAL 0x7BB07BB0 |
||||
#define AMBCTL1VAL 0xFFC27BB0 |
||||
|
||||
#define CONFIG_VDSP 1 |
||||
|
||||
#ifdef CONFIG_VDSP |
||||
#define ET_EXEC_VDSP 0x8 |
||||
#define SHT_STRTAB_VDSP 0x1 |
||||
#define ELFSHDRSIZE_VDSP 0x2C |
||||
#define VDSP_ENTRY_ADDR 0xFFA00000 |
||||
#endif |
||||
|
||||
#endif |
||||
@ -0,0 +1,475 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF533 STAMP board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_STAMP_H__ |
||||
#define __CONFIG_STAMP_H__ |
||||
|
||||
#define CONFIG_STAMP 1 |
||||
#define CONFIG_RTC_BFIN 1 |
||||
#define CONFIG_BF533 1 |
||||
/*
|
||||
* Boot Mode Set |
||||
* Blackfin can support several boot modes |
||||
*/ |
||||
#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ |
||||
#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ |
||||
#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ |
||||
/* Define the boot mode */ |
||||
#define BFIN_BOOT_MODE BF533_BYPASS_BOOT |
||||
//#define BFIN_BOOT_MODE BF533_SPI_BOOT
|
||||
|
||||
#define CONFIG_PANIC_HANG 1 |
||||
|
||||
#define ADSP_BF531 0x31 |
||||
#define ADSP_BF532 0x32 |
||||
#define ADSP_BF533 0x33 |
||||
#define BFIN_CPU ADSP_BF533 |
||||
|
||||
/* This sets the default state of the cache on U-Boot's boot */ |
||||
#define CONFIG_ICACHE_ON |
||||
#define CONFIG_DCACHE_ON |
||||
|
||||
/* Define where the uboot will be loaded by on-chip boot rom */ |
||||
#define APP_ENTRY 0x00001000 |
||||
|
||||
/*
|
||||
* Stringize definitions - needed for environmental settings |
||||
*/ |
||||
#define STRINGIZE2(x) #x |
||||
#define STRINGIZE(x) STRINGIZE2(x) |
||||
|
||||
/*
|
||||
* Board settings |
||||
* |
||||
*/ |
||||
#define CONFIG_DRIVER_SMC91111 1 |
||||
#define CONFIG_SMC91111_BASE 0x20300300 |
||||
|
||||
/* FLASH/ETHERNET uses the same address range */ |
||||
#define SHARED_RESOURCES 1 |
||||
|
||||
/* Is I2C bit-banged? */ |
||||
#define CONFIG_SOFT_I2C 1 |
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PF_SCL PF3 |
||||
#define PF_SDA PF2 |
||||
|
||||
/*
|
||||
* Video splash screen support |
||||
*/ |
||||
#define CONFIG_VIDEO 0 |
||||
|
||||
#define CONFIG_VDSP 1 |
||||
|
||||
/*
|
||||
* Clock settings |
||||
* |
||||
*/ |
||||
|
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 11059200 |
||||
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ |
||||
/* 1=CLKIN/2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ |
||||
/* 1=bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ |
||||
/* Values can range from 1-64 */ |
||||
#define CONFIG_VCO_MULT 36 |
||||
/* CONFIG_CCLK_DIV controls what the core clock divider is */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 5 |
||||
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ |
||||
/* Values can range from 2-65535 */ |
||||
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ |
||||
#define CONFIG_SPI_BAUD 2 |
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) |
||||
#define CONFIG_SPI_BAUD_INITBLOCK 4 |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Network settings |
||||
* |
||||
*/ |
||||
|
||||
#if (CONFIG_DRIVER_SMC91111) |
||||
#if 0 |
||||
#define CONFIG_MII |
||||
#endif |
||||
|
||||
/* network support */ |
||||
#define CONFIG_IPADDR 192.168.0.15 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_GATEWAYIP 192.168.0.1 |
||||
#define CONFIG_SERVERIP 192.168.0.2 |
||||
#define CONFIG_HOSTNAME STAMP |
||||
#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs |
||||
|
||||
/* To remove hardcoding and enable MAC storage in EEPROM */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ |
||||
#endif /* CONFIG_DRIVER_SMC91111 */ |
||||
|
||||
/*
|
||||
* Flash settings |
||||
* |
||||
*/ |
||||
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
#define CFG_FLASH_CFI_AMD_RESET |
||||
|
||||
#define CFG_FLASH_BASE 0x20000000 |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR 0x20004000 |
||||
#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) |
||||
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) |
||||
#define CFG_ENV_IS_IN_EEPROM 1 |
||||
#define CFG_ENV_OFFSET 0x4000 |
||||
#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */ |
||||
#endif |
||||
|
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
#define ENV_IS_EMBEDDED |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ |
||||
#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* JFFS Partition offset set */ |
||||
#define CFG_JFFS2_FIRST_BANK 0 |
||||
#define CFG_JFFS2_NUM_BANKS 1 |
||||
/* 512k reserved for u-boot */ |
||||
#define CFG_JFFS2_FIRST_SECTOR 11 |
||||
|
||||
/*
|
||||
* following timeouts shall be used once the |
||||
* Flash real protection is enabled |
||||
*/ |
||||
#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ |
||||
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ |
||||
|
||||
/*
|
||||
* SDRAM settings & memory map |
||||
* |
||||
*/ |
||||
|
||||
#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ |
||||
#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ |
||||
#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 |
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) |
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ |
||||
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) |
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#endif |
||||
|
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
|
||||
#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024) |
||||
#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1) |
||||
#define CONFIG_LOADADDR 0x01000000 |
||||
|
||||
#define CFG_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
|
||||
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000) |
||||
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) |
||||
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) |
||||
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) |
||||
|
||||
/* Check to make sure everything fits in SDRAM */ |
||||
#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE) |
||||
#error Memory Map does not fit into configuration |
||||
#endif |
||||
|
||||
#if ( CONFIG_CLKIN_HALF == 0 ) |
||||
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) |
||||
#else |
||||
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) |
||||
#endif |
||||
|
||||
#if (CONFIG_PLL_BYPASS == 0) |
||||
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) |
||||
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) |
||||
#else |
||||
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ |
||||
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ |
||||
#endif |
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) |
||||
#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000) |
||||
#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */ |
||||
#else |
||||
#undef CONFIG_SPI_FLASH_FAST_READ |
||||
#endif |
||||
#endif |
||||
/*
|
||||
* Command settings |
||||
* |
||||
*/ |
||||
|
||||
#define CFG_LONGHELP 1 |
||||
#define CONFIG_CMDLINE_EDITING 1 |
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) |
||||
#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ |
||||
#endif |
||||
/* configuration lookup from the BOOTP/DHCP server, */ |
||||
/* but not try to load any image using TFTP */ |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ |
||||
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) |
||||
#define CONFIG_BOOTCOMMAND "run ramboot" |
||||
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) |
||||
#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000" |
||||
#endif |
||||
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" |
||||
|
||||
#if (CONFIG_DRIVER_SMC91111) |
||||
#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DATE) |
||||
|
||||
#else |
||||
#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DATE) |
||||
|
||||
#endif |
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) |
||||
#if (CONFIG_DRIVER_SMC91111) |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
|
||||
"$(rootpath) console=ttyBF0,57600\0" \
|
||||
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
|
||||
"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
|
||||
"ramboot=tftpboot $(loadaddr) linux; " \
|
||||
"run ramargs;run addip;bootelf\0" \
|
||||
"nfsboot=tftpboot $(loadaddr) linux; " \
|
||||
"run nfsargs;run addip;bootelf\0" \
|
||||
"flashboot=bootm 0x20100000\0" \
|
||||
"update=tftpboot $(loadaddr) u-boot.bin; " \
|
||||
"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
|
||||
"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
|
||||
"" |
||||
#else |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||
"flashboot=bootm 0x20100000\0" \
|
||||
"" |
||||
#endif |
||||
|
||||
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
|
||||
"$(rootpath) console=ttyBF0,57600\0" \
|
||||
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
|
||||
"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
|
||||
"ramboot=tftpboot $(loadaddr) linux; " \
|
||||
"run ramargs;run addip;bootelf\0" \
|
||||
"nfsboot=tftpboot $(loadaddr) linux; " \
|
||||
"run nfsargs;run addip;bootelf\0" \
|
||||
"flashboot=bootm 0x20100000\0" \
|
||||
"update=tftpboot $(loadaddr) u-boot.ldr;" \
|
||||
"eeprom write $(loadaddr) 0x0 $(filesize);\0"\
|
||||
"" |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SOFT_I2C |
||||
#if (!CONFIG_SOFT_I2C) |
||||
#undef CONFIG_SOFT_I2C |
||||
#endif |
||||
#endif |
||||
|
||||
#if (CONFIG_SOFT_I2C) |
||||
#define CONFIG_COMMANDS2 CFG_CMD_I2C |
||||
#else |
||||
#define CONFIG_COMMANDS2 0 |
||||
#endif /* CONFIG_SOFT_I2C */ |
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) |
||||
#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP) |
||||
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) |
||||
#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2) |
||||
#endif |
||||
|
||||
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Console settings |
||||
* |
||||
*/ |
||||
|
||||
#define CONFIG_BAUDRATE 57600 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) |
||||
#if (BFIN_CPU == ADSP_BF531) |
||||
#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */ |
||||
#elif (BFIN_CPU == ADSP_BF532) |
||||
#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */ |
||||
#else |
||||
#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */ |
||||
#endif |
||||
#else |
||||
#if (BFIN_CPU == ADSP_BF531) |
||||
#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */ |
||||
#elif (BFIN_CPU == ADSP_BF532) |
||||
#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */ |
||||
#else |
||||
#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */ |
||||
#endif |
||||
#endif |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 |
||||
|
||||
/*
|
||||
* I2C settings |
||||
* By default PF2 is used as SDA and PF3 as SCL on the Stamp board |
||||
*/ |
||||
#if (CONFIG_SOFT_I2C) |
||||
|
||||
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") |
||||
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") |
||||
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") |
||||
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") |
||||
#define I2C_SDA(bit) if(bit) { \ |
||||
*pFIO_FLAG_S = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} |
||||
#define I2C_SCL(bit) if(bit) { \ |
||||
*pFIO_FLAG_S = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CFG_I2C_SPEED 50000 |
||||
#define CFG_I2C_SLAVE 0xFE |
||||
#endif /* CONFIG_SOFT_I2C */ |
||||
|
||||
/*
|
||||
* Compact Flash settings |
||||
*/ |
||||
|
||||
/* Enabled below option for CF support */ |
||||
/* #define CONFIG_STAMP_CF 1 */ |
||||
|
||||
#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) |
||||
|
||||
#define CONFIG_MISC_INIT_R 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
/*
|
||||
* IDE/ATA stuff |
||||
*/ |
||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
||||
#undef CONFIG_IDE_LED /* no led for ide supported */ |
||||
#undef CONFIG_IDE_RESET /* no reset for ide supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ |
||||
|
||||
#define CFG_ATA_BASE_ADDR 0x20200000 |
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ |
||||
#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ |
||||
|
||||
#define CFG_ATA_STRIDE 2 |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
|
||||
#define CFG_HZ 1000 /* 1ms time tick */ |
||||
|
||||
#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ |
||||
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ |
||||
|
||||
#define CONFIG_SPI |
||||
|
||||
#ifdef CONFIG_VIDEO |
||||
#if (CONFIG_VIDEO) |
||||
#define CONFIG_SPLASH_SCREEN 1 |
||||
#define CONFIG_SILENT_CONSOLE 1 |
||||
#else |
||||
#undef CONFIG_VIDEO |
||||
#endif |
||||
#endif |
||||
|
||||
/*
|
||||
* FLASH organization and environment definitions |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ |
||||
/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
||||
#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ |
||||
B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) |
||||
#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ |
||||
B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) |
||||
*/ |
||||
#define AMGCTLVAL 0xFF |
||||
#define AMBCTL0VAL 0xBBC3BBC3 |
||||
#define AMBCTL1VAL 0x99B39983 |
||||
#define CF_AMBCTL1VAL 0x99B3ffc2 |
||||
|
||||
#ifdef CONFIG_VDSP |
||||
#define ET_EXEC_VDSP 0x8 |
||||
#define SHT_STRTAB_VDSP 0x1 |
||||
#define ELFSHDRSIZE_VDSP 0x2C |
||||
#define VDSP_ENTRY_ADDR 0xFFA00000 |
||||
#endif |
||||
|
||||
|
||||
#endif |
||||
@ -1,188 +0,0 @@ |
||||
#ifndef __CONFIG_EZKIT533_H__ |
||||
#define __CONFIG_EZKIT533_H__ |
||||
|
||||
#define CFG_LONGHELP 1 |
||||
#define CONFIG_BAUDRATE 57600 |
||||
#define CONFIG_STAMP 1 |
||||
#define CONFIG_BOOTDELAY 5 |
||||
|
||||
#define CONFIG_DRIVER_SMC91111 1 |
||||
#define CONFIG_SMC91111_BASE 0x20310300 |
||||
#if 0 |
||||
#define CONFIG_MII |
||||
#define CFG_DISCOVER_PHY |
||||
#endif |
||||
|
||||
#define CONFIG_RTC_BF533 1 |
||||
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ |
||||
|
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 27000000 |
||||
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ |
||||
/* 1=CLKIN/2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ |
||||
/* 1=bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ |
||||
/* Values can range from 1-64 */ |
||||
#define CONFIG_VCO_MULT 22 |
||||
/* CONFIG_CCLK_DIV controls what the core clock divider is */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 5 |
||||
|
||||
#if ( CONFIG_CLKIN_HALF == 0 ) |
||||
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) |
||||
#else |
||||
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) |
||||
#endif |
||||
|
||||
#if (CONFIG_PLL_BYPASS == 0) |
||||
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) |
||||
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) |
||||
#else |
||||
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ |
||||
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ |
||||
#endif |
||||
|
||||
#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ |
||||
#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ |
||||
#define CONFIG_MEM_MT48LC16M16A2TG_75 1 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 |
||||
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_DATE) |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ |
||||
#define CFG_LOAD_ADDR 0x01000000 /* default load address */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_MAX_RAM_SIZE 0x02000000 |
||||
#define CFG_FLASH_BASE 0x20000000 |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) |
||||
#define CFG_GBL_DATA_SIZE 0x4000 |
||||
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) |
||||
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) |
||||
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
#define CFG_FLASH0_BASE 0x20000000 |
||||
#define CFG_FLASH1_BASE 0x20200000 |
||||
#define CFG_FLASH2_BASE 0x20280000 |
||||
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR 0x20020000 |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
|
||||
/* JFFS Partition offset set */ |
||||
#define CFG_JFFS2_FIRST_BANK 0 |
||||
#define CFG_JFFS2_NUM_BANKS 1 |
||||
/* 512k reserved for u-boot */ |
||||
#define CFG_JFFS2_FIRST_SECTOR 11 |
||||
|
||||
|
||||
/*
|
||||
* Stack sizes |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
|
||||
#define POLL_MODE 1 |
||||
#define FLASH_TOT_SECT 40 |
||||
#define FLASH_SIZE 0x220000 |
||||
#define CFG_FLASH_SIZE 0x220000 |
||||
|
||||
/*
|
||||
* Initialize PSD4256 registers for using I2C |
||||
*/ |
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
/*
|
||||
* I2C settings |
||||
* By default PF1 is used as SDA and PF0 as SCL on the Stamp board |
||||
*/ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PF_SCL PF0 |
||||
#define PF_SDA PF1 |
||||
|
||||
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") |
||||
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") |
||||
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") |
||||
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") |
||||
#define I2C_SDA(bit) if(bit) { \ |
||||
*pFIO_FLAG_S = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} |
||||
#define I2C_SCL(bit) if(bit) { \ |
||||
*pFIO_FLAG_S = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CFG_I2C_SPEED 50000 |
||||
#define CFG_I2C_SLAVE 0xFE |
||||
|
||||
|
||||
#define __ADSPLPBLACKFIN__ 1 |
||||
#define __ADSPBF533__ 1 |
||||
|
||||
/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ |
||||
/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
||||
#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ |
||||
~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) |
||||
#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ |
||||
B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) |
||||
*/ |
||||
#define AMGCTLVAL 0xFF |
||||
#define AMBCTL0VAL 0x7BB07BB0 |
||||
#define AMBCTL1VAL 0xFFC27BB0 |
||||
|
||||
#define CONFIG_VDSP 1 |
||||
|
||||
#ifdef CONFIG_VDSP |
||||
#define ET_EXEC_VDSP 0x8 |
||||
#define SHT_STRTAB_VDSP 0x1 |
||||
#define ELFSHDRSIZE_VDSP 0x2C |
||||
#define VDSP_ENTRY_ADDR 0xFFA00000 |
||||
#endif |
||||
|
||||
#endif |
||||
@ -1,333 +0,0 @@ |
||||
/*
|
||||
* U-boot - stamp.h Configuration file for STAMP board |
||||
* having BF533 processor |
||||
* |
||||
* Copyright (c) 2005 blackfin.uclinux.org |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_STAMP_H__ |
||||
#define __CONFIG_STAMP_H__ |
||||
|
||||
/*
|
||||
* Board settings |
||||
* |
||||
*/ |
||||
|
||||
#define __ADSPLPBLACKFIN__ 1 |
||||
#define __ADSPBF533__ 1 |
||||
#define CONFIG_STAMP 1 |
||||
#define CONFIG_RTC_BF533 1 |
||||
|
||||
/* FLASH/ETHERNET uses the same address range */ |
||||
#define SHARED_RESOURCES 1 |
||||
|
||||
#define CONFIG_VDSP 1 |
||||
|
||||
/*
|
||||
* Clock settings |
||||
* |
||||
*/ |
||||
|
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 11059200 |
||||
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ |
||||
/* 1=CLKIN/2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ |
||||
/* 1=bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ |
||||
/* Values can range from 1-64 */ |
||||
#define CONFIG_VCO_MULT 45 |
||||
/* CONFIG_CCLK_DIV controls what the core clock divider is */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 6 |
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
/* network support */ |
||||
#define CONFIG_IPADDR 192.168.0.15 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
#define CONFIG_GATEWAYIP 192.168.0.1 |
||||
#define CONFIG_SERVERIP 192.168.0.2 |
||||
#define CONFIG_HOSTNAME STAMP |
||||
#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs |
||||
|
||||
/* To remove hardcoding and enable MAC storage in EEPROM */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ |
||||
|
||||
/*
|
||||
* Command settings |
||||
* |
||||
*/ |
||||
|
||||
#define CFG_LONGHELP 1 |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ |
||||
#define CONFIG_BOOTCOMMAND "run ramboot" |
||||
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" |
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_JFFS2 | \
|
||||
CFG_CMD_DATE) |
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):eth0:off\0" \
|
||||
"ramboot=tftpboot 0x1000000 linux;" \
|
||||
"run ramargs;run addip;bootelf\0" \
|
||||
"nfsboot=tftpboot 0x1000000 linux;" \
|
||||
"run nfsargs;run addip;bootelf\0" \
|
||||
"flashboot=bootm 0x20100000\0" \
|
||||
"" |
||||
|
||||
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Console settings |
||||
* |
||||
*/ |
||||
|
||||
#define CONFIG_BAUDRATE 57600 |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 |
||||
|
||||
/*
|
||||
* Network settings |
||||
* |
||||
*/ |
||||
|
||||
#define CONFIG_DRIVER_SMC91111 1 |
||||
#define CONFIG_SMC91111_BASE 0x20300300 |
||||
/* To remove hardcoding and enable MAC storage in EEPROM */ |
||||
/* #define HARDCODE_MAC 1 */ |
||||
|
||||
/*
|
||||
* Flash settings |
||||
* |
||||
*/ |
||||
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */ |
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
#define CFG_FLASH_CFI_AMD_RESET |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
|
||||
#define CFG_FLASH_BASE 0x20000000 |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_ENV_ADDR 0x20020000 |
||||
#define CFG_ENV_SIZE 0x10000 |
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ |
||||
#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
/* JFFS Partition offset set */ |
||||
#define CFG_JFFS2_FIRST_BANK 0 |
||||
#define CFG_JFFS2_NUM_BANKS 1 |
||||
/* 512k reserved for u-boot */ |
||||
#define CFG_JFFS2_FIRST_SECTOR 11 |
||||
|
||||
/*
|
||||
* following timeouts shall be used once the |
||||
* Flash real protection is enabled |
||||
*/ |
||||
#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ |
||||
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ |
||||
|
||||
/*
|
||||
* I2C settings |
||||
* By default PF2 is used as SDA and PF3 as SCL on the Stamp board |
||||
*/ |
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration |
||||
*/ |
||||
#define PF_SCL PF3 |
||||
#define PF_SDA PF2 |
||||
|
||||
#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") |
||||
#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") |
||||
#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") |
||||
#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") |
||||
#define I2C_SDA(bit) if(bit) { \ |
||||
*pFIO_FLAG_S = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SDA; \
|
||||
asm("ssync;"); \
|
||||
} |
||||
#define I2C_SCL(bit) if(bit) { \ |
||||
*pFIO_FLAG_S = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} \
|
||||
else { \
|
||||
*pFIO_FLAG_C = PF_SCL; \
|
||||
asm("ssync;"); \
|
||||
} |
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
||||
|
||||
#define CFG_I2C_SPEED 50000 |
||||
#define CFG_I2C_SLAVE 0xFE |
||||
|
||||
/*
|
||||
* Compact Flash settings |
||||
*/ |
||||
|
||||
/* Enabled below option for CF support */ |
||||
/* #define CONFIG_STAMP_CF 1 */ |
||||
|
||||
#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) |
||||
|
||||
#define CONFIG_MISC_INIT_R 1 |
||||
#define CONFIG_DOS_PARTITION 1 |
||||
|
||||
/*
|
||||
* IDE/ATA stuff |
||||
*/ |
||||
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
||||
#undef CONFIG_IDE_LED /* no led for ide supported */ |
||||
#undef CONFIG_IDE_RESET /* no reset for ide supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
||||
#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ |
||||
|
||||
#define CFG_ATA_BASE_ADDR 0x20200000 |
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ |
||||
#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ |
||||
|
||||
#define CFG_ATA_STRIDE 2 |
||||
#endif |
||||
|
||||
/*
|
||||
* SDRAM settings |
||||
* |
||||
*/ |
||||
|
||||
#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ |
||||
#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ |
||||
#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ |
||||
#define CFG_LOAD_ADDR 0x01000000 /* default load address */ |
||||
|
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_MAX_RAM_SIZE 0x08000000 |
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) |
||||
|
||||
#if ( CONFIG_CLKIN_HALF == 0 ) |
||||
#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) |
||||
#else |
||||
#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) |
||||
#endif |
||||
|
||||
#if (CONFIG_PLL_BYPASS == 0) |
||||
#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) |
||||
#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) |
||||
#else |
||||
#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ |
||||
#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_HZ 1000 /* 1ms time tick */ |
||||
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) |
||||
#define CFG_GBL_DATA_SIZE 0x4000 |
||||
#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) |
||||
#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) |
||||
|
||||
#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ |
||||
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ |
||||
|
||||
/*
|
||||
* Stack sizes |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
|
||||
/*
|
||||
* FLASH organization and environment definitions |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ |
||||
/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
|
||||
#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ |
||||
B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) |
||||
#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ |
||||
B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) |
||||
*/ |
||||
#define AMGCTLVAL 0xFF |
||||
#define AMBCTL0VAL 0xBBC3BBC3 |
||||
#define AMBCTL1VAL 0x99B39983 |
||||
#define CF_AMBCTL1VAL 0x99B3ffc2 |
||||
|
||||
#ifdef CONFIG_VDSP |
||||
#define ET_EXEC_VDSP 0x8 |
||||
#define SHT_STRTAB_VDSP 0x1 |
||||
#define ELFSHDRSIZE_VDSP 0x2C |
||||
#define VDSP_ENTRY_ADDR 0xFFA00000 |
||||
#endif |
||||
|
||||
#endif |
||||
@ -0,0 +1,109 @@ |
||||
/* |
||||
* File: arch/blackfin/lib/memcmp.S |
||||
* Based on: |
||||
* Author: |
||||
* |
||||
* Created: |
||||
* Description: |
||||
* |
||||
* Rev: $Id: memcmp.S 2386 2006-11-01 04:57:26Z magicyang $ |
||||
* |
||||
* Modified: |
||||
* Copyright 2004-2006 Analog Devices Inc. |
||||
* |
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/ |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc., |
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
||||
*/ |
||||
|
||||
.align 2
|
||||
|
||||
/* |
||||
* C Library function MEMCMP |
||||
* R0 = First Address |
||||
* R1 = Second Address |
||||
* R2 = count |
||||
* Favours word aligned data. |
||||
*/ |
||||
|
||||
.globl _memcmp;
|
||||
_memcmp: |
||||
I1 = P3;
|
||||
P0 = R0; /* P0 = s1 address */
|
||||
P3 = R1; /* P3 = s2 Address */
|
||||
P2 = R2 ; /* P2 = count */
|
||||
CC = R2 <= 7(IU);
|
||||
IF CC JUMP .Ltoo_small;
|
||||
I0 = R1; /* s2 */
|
||||
R1 = R1 | R0; /* OR addresses together */
|
||||
R1 <<= 30; /* check bottom two bits */
|
||||
CC = AZ; /* AZ set if zero. */
|
||||
IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned. */
|
||||
|
||||
P1 = P2 >> 2; /* count = n/4 */
|
||||
R3 = 3;
|
||||
R2 = R2 & R3; /* remainder */
|
||||
P2 = R2; /* set remainder */
|
||||
|
||||
LSETUP (.Lquad_loop_s , .Lquad_loop_e) LC0=P1;
|
||||
.Lquad_loop_s: |
||||
NOP;
|
||||
R0 = [P0++];
|
||||
R1 = [I0++];
|
||||
CC = R0 == R1;
|
||||
IF !CC JUMP .Lquad_different;
|
||||
.Lquad_loop_e: |
||||
NOP;
|
||||
|
||||
P3 = I0; /* s2 */
|
||||
.Ltoo_small: |
||||
CC = P2 == 0; /* Check zero count*/
|
||||
IF CC JUMP .Lfinished; /* very unlikely*/
|
||||
|
||||
.Lbytes: |
||||
LSETUP (.Lbyte_loop_s , .Lbyte_loop_e) LC0=P2;
|
||||
.Lbyte_loop_s: |
||||
R1 = B[P3++](Z); /* *s2 */
|
||||
R0 = B[P0++](Z); /* *s1 */
|
||||
CC = R0 == R1;
|
||||
IF !CC JUMP .Ldifferent;
|
||||
.Lbyte_loop_e: |
||||
NOP;
|
||||
|
||||
.Ldifferent: |
||||
R0 = R0 - R1;
|
||||
P3 = I1;
|
||||
RTS;
|
||||
|
||||
.Lquad_different: |
||||
/* We've read two quads which don't match. |
||||
* Can't just compare them, because we're |
||||
* a little-endian machine, so the MSBs of |
||||
* the regs occur at later addresses in the |
||||
* string. |
||||
* Arrange to re-read those two quads again, |
||||
* byte-by-byte. |
||||
*/ |
||||
P0 += -4; /* back up to the start of the */
|
||||
P3 = I0; /* quads, and increase the*/
|
||||
P2 += 4; /* remainder count*/
|
||||
P3 += -4;
|
||||
JUMP .Lbytes;
|
||||
|
||||
.Lfinished: |
||||
R0 = 0;
|
||||
P3 = I1;
|
||||
RTS;
|
||||
@ -0,0 +1,130 @@ |
||||
/* |
||||
* File: arch/blackfin/lib/memcpy.S |
||||
* Based on: |
||||
* Author: |
||||
* |
||||
* Created: |
||||
* Description: internal version of memcpy(), issued by the compiler |
||||
* to copy blocks of data around. |
||||
* This is really memmove() - it has to be able to deal with |
||||
* possible overlaps, because that ambiguity is when the compiler |
||||
* gives up and calls a function. We have our own, internal version |
||||
* so that we get something we trust, even if the user has redefined |
||||
* the normal symbol. |
||||
* Rev: $Id: memcpy.S 2775 2007-02-21 13:58:44Z hennerich $ |
||||
* |
||||
* Modified: |
||||
* Copyright 2004-2006 Analog Devices Inc. |
||||
* |
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/ |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc., |
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
||||
*/ |
||||
|
||||
|
||||
|
||||
.align 2
|
||||
|
||||
.globl _memcpy_ASM;
|
||||
_memcpy_ASM: |
||||
CC = R2 <= 0; /* length not positive?*/
|
||||
IF CC JUMP .L_P1L2147483647; /* Nothing to do */
|
||||
|
||||
P0 = R0 ; /* dst*/
|
||||
P1 = R1 ; /* src*/
|
||||
P2 = R2 ; /* length */
|
||||
|
||||
/* check for overlapping data */ |
||||
CC = R1 < R0; /* src < dst */
|
||||
IF !CC JUMP .Lno_overlap;
|
||||
R3 = R1 + R2;
|
||||
CC = R0 < R3; /* and dst < src+len */
|
||||
IF CC JUMP .Lhas_overlap;
|
||||
|
||||
.Lno_overlap: |
||||
/* Check for aligned data.*/ |
||||
|
||||
R3 = R1 | R0;
|
||||
R0 = 0x3;
|
||||
R3 = R3 & R0;
|
||||
CC = R3; /* low bits set on either address? */
|
||||
IF CC JUMP .Lnot_aligned;
|
||||
|
||||
/* Both addresses are word-aligned, so we can copy |
||||
at least part of the data using word copies.*/ |
||||
P2 = P2 >> 2;
|
||||
CC = P2 <= 2;
|
||||
IF !CC JUMP .Lmore_than_seven;
|
||||
/* less than eight bytes... */ |
||||
P2 = R2;
|
||||
LSETUP(.Lthree_start, .Lthree_end) LC0=P2;
|
||||
R0 = R1; /* setup src address for return */
|
||||
.Lthree_start: |
||||
R3 = B[P1++] (X);
|
||||
.Lthree_end: |
||||
B[P0++] = R3;
|
||||
|
||||
RTS;
|
||||
|
||||
.Lmore_than_seven: |
||||
/* There's at least eight bytes to copy. */ |
||||
P2 += -1; /* because we unroll one iteration */
|
||||
LSETUP(.Lword_loop, .Lword_loop) LC0=P2;
|
||||
R0 = R1;
|
||||
I1 = P1;
|
||||
R3 = [I1++];
|
||||
.Lword_loop: |
||||
MNOP || [P0++] = R3 || R3 = [I1++];
|
||||
|
||||
[P0++] = R3;
|
||||
/* Any remaining bytes to copy? */ |
||||
R3 = 0x3;
|
||||
R3 = R2 & R3;
|
||||
CC = R3 == 0;
|
||||
P1 = I1; /* in case there's something left, */
|
||||
IF !CC JUMP .Lbytes_left;
|
||||
RTS;
|
||||
.Lbytes_left: P2 = R3;
|
||||
.Lnot_aligned: |
||||
/* From here, we're copying byte-by-byte. */ |
||||
LSETUP (.Lbyte_start , .Lbyte_end) LC0=P2;
|
||||
R0 = R1; /* Save src address for return */
|
||||
.Lbyte_start: |
||||
R1 = B[P1++] (X);
|
||||
.Lbyte_end: |
||||
B[P0++] = R1;
|
||||
|
||||
.L_P1L2147483647: |
||||
RTS;
|
||||
|
||||
.Lhas_overlap: |
||||
/* Need to reverse the copying, because the |
||||
* dst would clobber the src. |
||||
* Don't bother to work out alignment for |
||||
* the reverse case. |
||||
*/ |
||||
R0 = R1; /* save src for later. */
|
||||
P0 = P0 + P2;
|
||||
P0 += -1;
|
||||
P1 = P1 + P2;
|
||||
P1 += -1;
|
||||
LSETUP(.Lover_start, .Lover_end) LC0=P2;
|
||||
.Lover_start: |
||||
R1 = B[P1--] (X);
|
||||
.Lover_end: |
||||
B[P0--] = R1;
|
||||
|
||||
RTS;
|
||||
@ -0,0 +1,102 @@ |
||||
/* |
||||
* File: arch/blackfin/lib/memmove.S |
||||
* Based on: |
||||
* Author: |
||||
* |
||||
* Created: |
||||
* Description: |
||||
* |
||||
* Rev: $Id: memmove.S 2205 2006-09-23 07:53:49Z vapier $ |
||||
* |
||||
* Modified: |
||||
* Copyright 2004-2006 Analog Devices Inc. |
||||
* |
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/ |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc., |
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
||||
*/ |
||||
|
||||
.align 2
|
||||
|
||||
/* |
||||
* C Library function MEMMOVE |
||||
* R0 = To Address (leave unchanged to form result) |
||||
* R1 = From Address |
||||
* R2 = count |
||||
* Data may overlap |
||||
*/ |
||||
|
||||
.globl _memmove;
|
||||
_memmove: |
||||
I1 = P3;
|
||||
P0 = R0; /* P0 = To address */
|
||||
P3 = R1; /* P3 = From Address */
|
||||
P2 = R2 ; /* P2 = count */
|
||||
CC = P2 == 0; /* Check zero count*/
|
||||
IF CC JUMP .Lfinished; /* very unlikely */
|
||||
|
||||
CC = R1 < R0 (IU); /* From < To */
|
||||
IF !CC JUMP .Lno_overlap;
|
||||
R3 = R1 + R2;
|
||||
CC = R0 <= R3 (IU); /* (From+len) >= To */
|
||||
IF CC JUMP .Loverlap;
|
||||
.Lno_overlap: |
||||
R3 = 11;
|
||||
CC = R2 <= R3;
|
||||
IF CC JUMP .Lbytes;
|
||||
R3 = R1 | R0; /* OR addresses together */
|
||||
R3 <<= 30; /* check bottom two bits */
|
||||
CC = AZ; /* AZ set if zero.*/
|
||||
IF !CC JUMP .Lbytes ; /* Jump if addrs not aligned.*/
|
||||
|
||||
I0 = P3;
|
||||
P1 = P2 >> 2; /* count = n/4 */
|
||||
P1 += -1;
|
||||
R3 = 3;
|
||||
R2 = R2 & R3; /* remainder */
|
||||
P2 = R2; /* set remainder */
|
||||
R1 = [I0++];
|
||||
|
||||
LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
|
||||
.Lquad_loop: MNOP || [P0++] = R1 || R1 = [I0++];
|
||||
[P0++] = R1;
|
||||
|
||||
CC = P2 == 0; /* any remaining bytes? */
|
||||
P3 = I0; /* Ammend P3 to updated ptr. */
|
||||
IF !CC JUMP .Lbytes;
|
||||
P3 = I1;
|
||||
RTS;
|
||||
|
||||
.Lbytes: LSETUP (.Lbyte2_s , .Lbyte2_e) LC0=P2;
|
||||
.Lbyte2_s: R1 = B[P3++](Z);
|
||||
.Lbyte2_e: B[P0++] = R1;
|
||||
|
||||
.Lfinished: P3 = I1;
|
||||
RTS;
|
||||
|
||||
.Loverlap: |
||||
P2 += -1;
|
||||
P0 = P0 + P2;
|
||||
P3 = P3 + P2;
|
||||
R1 = B[P3--] (Z);
|
||||
CC = P2 == 0;
|
||||
IF CC JUMP .Lno_loop;
|
||||
LSETUP (.Lol_s, .Lol_e) LC0 = P2;
|
||||
.Lol_s: B[P0--] = R1;
|
||||
.Lol_e: R1 = B[P3--] (Z);
|
||||
.Lno_loop: B[P0] = R1;
|
||||
P3 = I1;
|
||||
RTS;
|
||||
@ -0,0 +1,103 @@ |
||||
/* |
||||
* File: arch/blackfin/lib/memset.S |
||||
* Based on: |
||||
* Author: |
||||
* |
||||
* Created: |
||||
* Description: |
||||
* |
||||
* Rev: $Id: memset.S 2769 2007-02-19 16:45:53Z hennerich $ |
||||
* |
||||
* Modified: |
||||
* Copyright 2004-2006 Analog Devices Inc. |
||||
* |
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/ |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, see the file COPYING, or write
|
||||
* to the Free Software Foundation, Inc., |
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
||||
*/ |
||||
|
||||
|
||||
.align 2
|
||||
|
||||
/* |
||||
* C Library function MEMSET |
||||
* R0 = address (leave unchanged to form result) |
||||
* R1 = filler byte |
||||
* R2 = count |
||||
* Favours word aligned data. |
||||
*/ |
||||
|
||||
.globl _memset;
|
||||
_memset: |
||||
P0 = R0 ; /* P0 = address */
|
||||
P2 = R2 ; /* P2 = count */
|
||||
R3 = R0 + R2; /* end */
|
||||
CC = R2 <= 7(IU);
|
||||
IF CC JUMP .Ltoo_small;
|
||||
R1 = R1.B (Z); /* R1 = fill char */
|
||||
R2 = 3;
|
||||
R2 = R0 & R2; /* addr bottom two bits */
|
||||
CC = R2 == 0; /* AZ set if zero. */
|
||||
IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
|
||||
|
||||
.Laligned: |
||||
P1 = P2 >> 2; /* count = n/4 */
|
||||
R2 = R1 << 8; /* create quad filler */
|
||||
R2.L = R2.L + R1.L(NS);
|
||||
R2.H = R2.L + R1.H(NS);
|
||||
P2 = R3;
|
||||
|
||||
LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
|
||||
.Lquad_loop: |
||||
[P0++] = R2;
|
||||
|
||||
CC = P0 == P2;
|
||||
IF !CC JUMP .Lbytes_left;
|
||||
RTS;
|
||||
|
||||
.Lbytes_left: |
||||
R2 = R3; /* end point */
|
||||
R3 = P0; /* current position */
|
||||
R2 = R2 - R3; /* bytes left */
|
||||
P2 = R2;
|
||||
|
||||
.Ltoo_small: |
||||
CC = P2 == 0; /* Check zero count */
|
||||
IF CC JUMP .Lfinished; /* Unusual */
|
||||
|
||||
.Lbytes: |
||||
LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
|
||||
.Lbyte_loop: |
||||
B[P0++] = R1;
|
||||
|
||||
.Lfinished: |
||||
RTS;
|
||||
|
||||
.Lforce_align: |
||||
CC = BITTST (R0, 0); /* odd byte */
|
||||
R0 = 4;
|
||||
R0 = R0 - R2;
|
||||
P1 = R0;
|
||||
R0 = P0; /* Recover return address */
|
||||
IF !CC JUMP .Lskip1;
|
||||
B[P0++] = R1;
|
||||
.Lskip1: |
||||
CC = R2 <= 2; /* 2 bytes */
|
||||
P2 -= P1; /* reduce count */
|
||||
IF !CC JUMP .Laligned;
|
||||
B[P0++] = R1;
|
||||
B[P0++] = R1;
|
||||
JUMP .Laligned;
|
||||
@ -0,0 +1,435 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <console.h> |
||||
#include <watchdog.h> |
||||
#include <post.h> |
||||
|
||||
#ifdef CONFIG_LOGBUFFER |
||||
#include <logbuff.h> |
||||
#endif |
||||
|
||||
#ifdef CONFIG_POST |
||||
|
||||
#define POST_MAX_NUMBER 32 |
||||
|
||||
#define BOOTMODE_MAGIC 0xDEAD0000 |
||||
|
||||
int post_init_f(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int res = 0; |
||||
unsigned int i; |
||||
|
||||
for (i = 0; i < post_list_size; i++) { |
||||
struct post_test *test = post_list + i; |
||||
|
||||
if (test->init_f && test->init_f()) { |
||||
res = -1; |
||||
} |
||||
} |
||||
|
||||
gd->post_init_f_time = post_time_ms(0); |
||||
if (!gd->post_init_f_time) { |
||||
printf |
||||
("post/post.c: post_time_ms seems not to be implemented\n"); |
||||
} |
||||
|
||||
return res; |
||||
} |
||||
|
||||
void post_bootmode_init(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
int bootmode = post_bootmode_get(0); |
||||
int newword; |
||||
|
||||
if (post_hotkeys_pressed() && !(bootmode & POST_POWERTEST)) { |
||||
newword = BOOTMODE_MAGIC | POST_SLOWTEST; |
||||
} else if (bootmode == 0) { |
||||
newword = BOOTMODE_MAGIC | POST_POWERON; |
||||
} else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) { |
||||
newword = BOOTMODE_MAGIC | POST_NORMAL; |
||||
} else { |
||||
/* Use old value */ |
||||
newword = post_word_load() & ~POST_COLDBOOT; |
||||
} |
||||
|
||||
if (bootmode == 0) { |
||||
/* We are booting after power-on */ |
||||
newword |= POST_COLDBOOT; |
||||
} |
||||
|
||||
post_word_store(newword); |
||||
|
||||
/* Reset activity record */ |
||||
gd->post_log_word = 0; |
||||
} |
||||
|
||||
int post_bootmode_get(unsigned int *last_test) |
||||
{ |
||||
unsigned long word = post_word_load(); |
||||
int bootmode; |
||||
|
||||
if ((word & 0xFFFF0000) != BOOTMODE_MAGIC) { |
||||
return 0; |
||||
} |
||||
|
||||
bootmode = word & 0x7F; |
||||
|
||||
if (last_test && (bootmode & POST_POWERTEST)) { |
||||
*last_test = (word >> 8) & 0xFF; |
||||
} |
||||
|
||||
return bootmode; |
||||
} |
||||
|
||||
/* POST tests run before relocation only mark status bits .... */ |
||||
static void post_log_mark_start(unsigned long testid) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
gd->post_log_word |= (testid) << 16; |
||||
} |
||||
|
||||
static void post_log_mark_succ(unsigned long testid) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
gd->post_log_word |= testid; |
||||
} |
||||
|
||||
/* ... and the messages are output once we are relocated */ |
||||
void post_output_backlog(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
int j; |
||||
|
||||
for (j = 0; j < post_list_size; j++) { |
||||
if (gd->post_log_word & (post_list[j].testid << 16)) { |
||||
post_log("POST %s ", post_list[j].cmd); |
||||
if (gd->post_log_word & post_list[j].testid) |
||||
post_log("PASSED\n"); |
||||
else { |
||||
post_log("FAILED\n"); |
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS |
||||
show_boot_progress(-31); |
||||
#endif |
||||
} |
||||
} |
||||
} |
||||
} |
||||
|
||||
static void post_bootmode_test_on(unsigned int last_test) |
||||
{ |
||||
unsigned long word = post_word_load(); |
||||
|
||||
word |= POST_POWERTEST; |
||||
|
||||
word |= (last_test & 0xFF) << 8; |
||||
|
||||
post_word_store(word); |
||||
} |
||||
|
||||
static void post_bootmode_test_off(void) |
||||
{ |
||||
unsigned long word = post_word_load(); |
||||
|
||||
word &= ~POST_POWERTEST; |
||||
|
||||
post_word_store(word); |
||||
} |
||||
|
||||
static void post_get_flags(int *test_flags) |
||||
{ |
||||
int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST }; |
||||
char *var[] = { "post_poweron", "post_normal", "post_slowtest" }; |
||||
int varnum = sizeof(var) / sizeof(var[0]); |
||||
char list[128]; /* long enough for POST list */ |
||||
char *name; |
||||
char *s; |
||||
int last; |
||||
int i, j; |
||||
|
||||
for (j = 0; j < post_list_size; j++) { |
||||
test_flags[j] = post_list[j].flags; |
||||
} |
||||
|
||||
for (i = 0; i < varnum; i++) { |
||||
if (getenv_r(var[i], list, sizeof(list)) <= 0) |
||||
continue; |
||||
|
||||
for (j = 0; j < post_list_size; j++) { |
||||
test_flags[j] &= ~flag[i]; |
||||
} |
||||
|
||||
last = 0; |
||||
name = list; |
||||
while (!last) { |
||||
while (*name && *name == ' ') |
||||
name++; |
||||
if (*name == 0) |
||||
break; |
||||
s = name + 1; |
||||
while (*s && *s != ' ') |
||||
s++; |
||||
if (*s == 0) |
||||
last = 1; |
||||
else |
||||
*s = 0; |
||||
|
||||
for (j = 0; j < post_list_size; j++) { |
||||
if (strcmp(post_list[j].cmd, name) == 0) { |
||||
test_flags[j] |= flag[i]; |
||||
break; |
||||
} |
||||
} |
||||
|
||||
if (j == post_list_size) { |
||||
printf("No such test: %s\n", name); |
||||
} |
||||
|
||||
name = s + 1; |
||||
} |
||||
} |
||||
|
||||
for (j = 0; j < post_list_size; j++) { |
||||
if (test_flags[j] & POST_POWERON) { |
||||
test_flags[j] |= POST_SLOWTEST; |
||||
} |
||||
} |
||||
} |
||||
|
||||
static int post_run_single(struct post_test *test, |
||||
int test_flags, int flags, unsigned int i) |
||||
{ |
||||
if ((flags & test_flags & POST_ALWAYS) && |
||||
(flags & test_flags & POST_MEM)) { |
||||
WATCHDOG_RESET(); |
||||
|
||||
if (!(flags & POST_REBOOT)) { |
||||
if ((test_flags & POST_REBOOT) |
||||
&& !(flags & POST_MANUAL)) { |
||||
post_bootmode_test_on(i); |
||||
} |
||||
|
||||
if (test_flags & POST_PREREL) |
||||
post_log_mark_start(test->testid); |
||||
else |
||||
post_log("POST %s ", test->cmd); |
||||
} |
||||
|
||||
if (test_flags & POST_PREREL) { |
||||
if ((*test->test) (flags) == 0) |
||||
post_log_mark_succ(test->testid); |
||||
} else { |
||||
if ((*test->test) (flags) != 0) { |
||||
post_log("FAILED\n"); |
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS |
||||
show_boot_progress(-32); |
||||
#endif |
||||
} else |
||||
post_log("PASSED\n"); |
||||
} |
||||
|
||||
if ((test_flags & POST_REBOOT) && !(flags & POST_MANUAL)) { |
||||
post_bootmode_test_off(); |
||||
} |
||||
|
||||
return 0; |
||||
} else { |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
int post_run(char *name, int flags) |
||||
{ |
||||
unsigned int i; |
||||
int test_flags[POST_MAX_NUMBER]; |
||||
|
||||
post_get_flags(test_flags); |
||||
|
||||
if (name == NULL) { |
||||
unsigned int last; |
||||
|
||||
if (post_bootmode_get(&last) & POST_POWERTEST) { |
||||
if (last < post_list_size && |
||||
(flags & test_flags[last] & POST_ALWAYS) && |
||||
(flags & test_flags[last] & POST_MEM)) { |
||||
|
||||
post_run_single(post_list + last, |
||||
test_flags[last], |
||||
flags | POST_REBOOT, last); |
||||
|
||||
for (i = last + 1; i < post_list_size; i++) { |
||||
post_run_single(post_list + i, |
||||
test_flags[i], |
||||
flags, i); |
||||
} |
||||
} |
||||
} else { |
||||
for (i = 0; i < post_list_size; i++) { |
||||
post_run_single(post_list + i, |
||||
test_flags[i], flags, i); |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} else { |
||||
for (i = 0; i < post_list_size; i++) { |
||||
if (strcmp(post_list[i].cmd, name) == 0) |
||||
break; |
||||
} |
||||
|
||||
if (i < post_list_size) { |
||||
return post_run_single(post_list + i, |
||||
test_flags[i], flags, i); |
||||
} else { |
||||
return -1; |
||||
} |
||||
} |
||||
} |
||||
|
||||
static int post_info_single(struct post_test *test, int full) |
||||
{ |
||||
if (test->flags & POST_MANUAL) { |
||||
if (full) |
||||
printf("%s - %s\n" |
||||
" %s\n", test->cmd, test->name, test->desc); |
||||
else |
||||
printf(" %-15s - %s\n", test->cmd, test->name); |
||||
|
||||
return 0; |
||||
} else { |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
int post_info(char *name) |
||||
{ |
||||
unsigned int i; |
||||
|
||||
if (name == NULL) { |
||||
for (i = 0; i < post_list_size; i++) { |
||||
post_info_single(post_list + i, 0); |
||||
} |
||||
|
||||
return 0; |
||||
} else { |
||||
for (i = 0; i < post_list_size; i++) { |
||||
if (strcmp(post_list[i].cmd, name) == 0) |
||||
break; |
||||
} |
||||
|
||||
if (i < post_list_size) { |
||||
return post_info_single(post_list + i, 1); |
||||
} else { |
||||
return -1; |
||||
} |
||||
} |
||||
} |
||||
|
||||
int post_log(char *format, ...) |
||||
{ |
||||
va_list args; |
||||
uint i; |
||||
char printbuffer[CFG_PBSIZE]; |
||||
|
||||
va_start(args, format); |
||||
|
||||
/* For this to work, printbuffer must be larger than
|
||||
* anything we ever want to print. |
||||
*/ |
||||
i = vsprintf(printbuffer, format, args); |
||||
va_end(args); |
||||
|
||||
#ifdef CONFIG_LOGBUFFER |
||||
/* Send to the logbuffer */ |
||||
logbuff_log(printbuffer); |
||||
#else |
||||
/* Send to the stdout file */ |
||||
puts(printbuffer); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void post_reloc(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
unsigned int i; |
||||
|
||||
/*
|
||||
* We have to relocate the test table manually |
||||
*/ |
||||
for (i = 0; i < post_list_size; i++) { |
||||
ulong addr; |
||||
struct post_test *test = post_list + i; |
||||
|
||||
if (test->name) { |
||||
addr = (ulong) (test->name) + gd->reloc_off; |
||||
test->name = (char *)addr; |
||||
} |
||||
|
||||
if (test->cmd) { |
||||
addr = (ulong) (test->cmd) + gd->reloc_off; |
||||
test->cmd = (char *)addr; |
||||
} |
||||
|
||||
if (test->desc) { |
||||
addr = (ulong) (test->desc) + gd->reloc_off; |
||||
test->desc = (char *)addr; |
||||
} |
||||
|
||||
if (test->test) { |
||||
addr = (ulong) (test->test) + gd->reloc_off; |
||||
test->test = (int (*)(int flags))addr; |
||||
} |
||||
|
||||
if (test->init_f) { |
||||
addr = (ulong) (test->init_f) + gd->reloc_off; |
||||
test->init_f = (int (*)(void))addr; |
||||
} |
||||
|
||||
if (test->reloc) { |
||||
addr = (ulong) (test->reloc) + gd->reloc_off; |
||||
test->reloc = (void (*)(void))addr; |
||||
|
||||
test->reloc(); |
||||
} |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Some tests (e.g. SYSMON) need the time when post_init_f started, |
||||
* but we cannot use get_timer() at this point. |
||||
* |
||||
* On PowerPC we implement it using the timebase register. |
||||
*/ |
||||
unsigned long post_time_ms(unsigned long base) |
||||
{ |
||||
return (unsigned long)get_ticks() / (get_tbclk() / CFG_HZ) - base; |
||||
} |
||||
|
||||
#endif /* CONFIG_POST */ |
||||
@ -0,0 +1,253 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Be sure to mark tests to be run before relocation as such with the |
||||
* CFG_POST_PREREL flag so that logging is done correctly if the |
||||
* logbuffer support is enabled. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#ifdef CONFIG_POST |
||||
|
||||
#include <post.h> |
||||
#define CFG_POST_FLASH 0x00004000 |
||||
#define CFG_POST_LED 0x00008000 |
||||
#define CFG_POST_BUTTON 0x00010000 |
||||
|
||||
extern int cache_post_test(int flags); |
||||
extern int watchdog_post_test(int flags); |
||||
extern int i2c_post_test(int flags); |
||||
extern int rtc_post_test(int flags); |
||||
extern int memory_post_test(int flags); |
||||
extern int cpu_post_test(int flags); |
||||
extern int uart_post_test(int flags); |
||||
extern int ether_post_test(int flags); |
||||
extern int spi_post_test(int flags); |
||||
extern int usb_post_test(int flags); |
||||
extern int spr_post_test(int flags); |
||||
extern int sysmon_post_test(int flags); |
||||
extern int dsp_post_test(int flags); |
||||
extern int codec_post_test(int flags); |
||||
|
||||
extern int sysmon_init_f(void); |
||||
|
||||
extern void sysmon_reloc(void); |
||||
|
||||
extern int flash_post_test(int flags); |
||||
extern int led_post_test(int flags); |
||||
extern int button_post_test(int flags); |
||||
|
||||
struct post_test post_list[] = { |
||||
#if CONFIG_POST & CFG_POST_CACHE |
||||
{ |
||||
"Cache test", |
||||
"cache", |
||||
"This test verifies the CPU cache operation.", |
||||
POST_RAM | POST_ALWAYS, |
||||
&cache_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_CACHE}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_WATCHDOG |
||||
{ |
||||
"Watchdog timer test", |
||||
"watchdog", |
||||
"This test checks the watchdog timer.", |
||||
POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, |
||||
&watchdog_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_WATCHDOG}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_I2C |
||||
{ |
||||
"I2C test", |
||||
"i2c", |
||||
"This test verifies the I2C operation.", |
||||
POST_RAM | POST_ALWAYS, |
||||
&i2c_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_I2C}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_RTC |
||||
{ |
||||
"RTC test", |
||||
"rtc", |
||||
"This test verifies the RTC operation.", |
||||
POST_RAM | POST_SLOWTEST | POST_MANUAL, |
||||
&rtc_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_RTC}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_MEMORY |
||||
{ |
||||
"Memory test", |
||||
"memory", |
||||
"This test checks RAM.", |
||||
POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL, |
||||
&memory_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_MEMORY}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_CPU |
||||
{ |
||||
"CPU test", |
||||
"cpu", |
||||
"This test verifies the arithmetic logic unit of" " CPU.", |
||||
POST_RAM | POST_ALWAYS, |
||||
&cpu_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_CPU}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_UART |
||||
{ |
||||
"UART test", |
||||
"uart", |
||||
"This test verifies the UART operation.", |
||||
POST_RAM | POST_SLOWTEST | POST_MANUAL, |
||||
&uart_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_UART}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_ETHER |
||||
{ |
||||
"ETHERNET test", |
||||
"ethernet", |
||||
"This test verifies the ETHERNET operation.", |
||||
POST_RAM | POST_ALWAYS | POST_MANUAL, |
||||
ðer_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_ETHER}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_SPI |
||||
{ |
||||
"SPI test", |
||||
"spi", |
||||
"This test verifies the SPI operation.", |
||||
POST_RAM | POST_ALWAYS | POST_MANUAL, |
||||
&spi_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_SPI}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_USB |
||||
{ |
||||
"USB test", |
||||
"usb", |
||||
"This test verifies the USB operation.", |
||||
POST_RAM | POST_ALWAYS | POST_MANUAL, |
||||
&usb_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_USB}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_SPR |
||||
{ |
||||
"SPR test", |
||||
"spr", |
||||
"This test checks SPR contents.", |
||||
POST_ROM | POST_ALWAYS | POST_PREREL, |
||||
&spr_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_SPR}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_SYSMON |
||||
{ |
||||
"SYSMON test", |
||||
"sysmon", |
||||
"This test monitors system hardware.", |
||||
POST_RAM | POST_ALWAYS, |
||||
&sysmon_post_test, |
||||
&sysmon_init_f, |
||||
&sysmon_reloc, |
||||
CFG_POST_SYSMON}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_DSP |
||||
{ |
||||
"DSP test", |
||||
"dsp", |
||||
"This test checks any connected DSP(s).", |
||||
POST_RAM | POST_MANUAL, |
||||
&dsp_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_DSP}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_CODEC |
||||
{ |
||||
"CODEC test", |
||||
"codec", |
||||
"This test checks any connected codec(s).", |
||||
POST_RAM | POST_MANUAL, |
||||
&codec_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_CODEC}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_FLASH |
||||
{ |
||||
"FLASH test", |
||||
"flash", |
||||
"This test checks flash.", |
||||
POST_RAM | POST_ALWAYS | POST_MANUAL, |
||||
&flash_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_FLASH}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_LED |
||||
{ |
||||
"LED test", |
||||
"LED", |
||||
"This test checks LED ", |
||||
POST_RAM | POST_ALWAYS | POST_MANUAL, |
||||
&led_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_LED}, |
||||
#endif |
||||
#if CONFIG_POST & CFG_POST_BUTTON |
||||
{ |
||||
"Button test", |
||||
"button", |
||||
"This test checks Button ", |
||||
POST_RAM | POST_ALWAYS | POST_MANUAL, |
||||
&button_post_test, |
||||
NULL, |
||||
NULL, |
||||
CFG_POST_BUTTON}, |
||||
#endif |
||||
|
||||
}; |
||||
|
||||
unsigned int post_list_size = sizeof(post_list) / sizeof(struct post_test); |
||||
|
||||
#endif /* CONFIG_POST */ |
||||
Loading…
Reference in new issue