The "tb0229" board has long been unmaintained, and is broken. Remove it. Signed-off-by: Wolfgang Denk <wd@denx.de>master
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@ -1,47 +0,0 @@ |
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#
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# (C) Masami Komiya <mkomiya@sonare.it> 2004
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o vr4131-pci.o
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SOBJS = lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,30 +0,0 @@ |
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#
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# (C) Masami Komiya <mkomiya@sonare.it> 2004
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# ROM version
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CONFIG_SYS_TEXT_BASE = 0xBFC00000
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# RAM version
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#CONFIG_SYS_TEXT_BASE = 0x80400000
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File diff suppressed because it is too large
Load Diff
@ -1,70 +0,0 @@ |
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/* |
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* Memory sub-system initialization code for TANBAC Evaluation board TB0229. |
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* |
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* Copyright (c) 2003 Masami Komiya <mkomiya@sonare.it>
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2, or (at
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* your option) any later version. |
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*/ |
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#include <config.h> |
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#include <asm/regdef.h> |
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.globl lowlevel_init
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lowlevel_init: |
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/* BCUCNTREG1 = 0x0040 */ |
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la t0, 0xaf000000 |
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li t1, 0x0040 |
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sh t1, 0(t0) |
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/* ROMSIZEREG = 0x3333 */ |
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la t0, 0xaf000004 |
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li t1, 0x3333 |
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sh t1, 0(t0) |
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/* ROMSPEEDREG = 0x3003 */ |
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la t0, 0xaf000006 |
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li t1, 0x3003 |
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sh t1, 0(t0) |
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/* BCUCNTREG3 = 0 */ |
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la t0, 0xaf000016 |
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li t1, 0x0000 |
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sh t1, 0(t0) |
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/* CMUCLKMSK */ |
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la t0, 0xaf000060 |
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li t1, 0x39a2 |
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sh t1, 0(t0) |
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/* PMUCNTREG */ |
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la t0, 0xaf0000c2 |
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li t1, 0x0006 |
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sh t1, 0(t0) |
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/* SDRAMMODEREG = 0x8029 */ |
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la t0, 0xaf000400 |
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li t1, 0x8029 |
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sh t1, 0(t0) |
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/* SDRAMCNTREG = 0x2322 */ |
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la t0, 0xaf000402 |
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li t1, 0x2322 |
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sh t1, 0(t0) |
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/* BCURFCNTREG = 0x0106 */ |
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la t0, 0xaf000404 |
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li t1, 0x0106 |
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sh t1, 0(t0) |
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/* RAMSZEREG = 0x5555 (64MB Bank) */ |
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la t0, 0xaf000408 |
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li t1, 0x5555 |
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sh t1, 0(t0) |
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j ra |
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nop |
@ -1,54 +0,0 @@ |
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/*
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* Board initialize code for TANBAC Evaluation board TB0229. |
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* |
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* (C) Masami Komiya <mkomiya@sonare.it> 2004 |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2, or (at |
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* your option) any later version. |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <netdev.h> |
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#include <asm/addrspace.h> |
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#include <asm/io.h> |
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#include <asm/reboot.h> |
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#include <pci.h> |
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void _machine_restart(void) |
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{ |
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void (*f)(void) = (void *) 0xbfc00000; |
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f(); |
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} |
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#if defined(CONFIG_PCI) |
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static struct pci_controller hose; |
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void pci_init_board (void) |
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{ |
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init_vr4131_pci(&hose); |
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} |
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#endif |
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phys_size_t initdram(int board_type) |
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{ |
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return get_ram_size (CONFIG_SYS_SDRAM_BASE, 0x8000000); |
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} |
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int checkboard (void) |
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{ |
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printf("Board: TANBAC TB0229 "); |
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printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000); |
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set_io_port_base(0); |
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return 0; |
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} |
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int board_eth_init(bd_t *bis) |
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{ |
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return pci_eth_init(bis); |
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} |
@ -1,70 +0,0 @@ |
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/* |
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* (C) Masami Komiya <mkomiya@sonare.it> 2004 |
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* |
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* (C) Copyright 2003 |
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* Wolfgang Denk Engineering, <wd@denx.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips") |
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OUTPUT_ARCH(mips) |
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ENTRY(_start) |
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SECTIONS |
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{ |
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. = 0x00000000; |
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. = ALIGN(4); |
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.text : |
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{ |
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*(.text*) |
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} |
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. = ALIGN(4); |
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.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } |
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. = ALIGN(4); |
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.data : { *(.data*) } |
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. = .; |
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_gp = ALIGN(16) + 0x7ff0; |
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.got : { |
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__got_start = .; |
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*(.got) |
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__got_end = .; |
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} |
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.sdata : { *(.sdata*) } |
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.u_boot_cmd : { |
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__u_boot_cmd_start = .; |
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*(.u_boot_cmd) |
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__u_boot_cmd_end = .; |
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} |
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uboot_end_data = .; |
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num_got_entries = (__got_end - __got_start) >> 2; |
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. = ALIGN(4); |
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.sbss (NOLOAD) : { *(.sbss*) } |
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.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); } |
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uboot_end = .; |
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} |
@ -1,254 +0,0 @@ |
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/*
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* VR4131 PCIU support code for TANBAC Evaluation board TB0229. |
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* |
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* (C) Masami Komiya <mkomiya@sonare.it> 2004 |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2, or (at |
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* your option) any later version. |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <asm/addrspace.h> |
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#define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00) |
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#define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04) |
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#define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08) |
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#define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c) |
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#define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10) |
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#define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14) |
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#define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18) |
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#define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c) |
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#define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24) |
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#define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28) |
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#define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c) |
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#define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30) |
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#define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34) |
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#define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38) |
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#define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c) |
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#define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60) |
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#define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) |
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#define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) |
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#define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00) |
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#define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) |
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#define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04) |
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#define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) |
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#define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08) |
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#define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) |
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#define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c) |
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#define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10) |
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#define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14) |
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#define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18) |
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/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */ |
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/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */ |
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/*#define VR4122_PCI_HOST_BASE 0xa0000000 */ |
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volatile unsigned int *pciconfigaddr; |
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volatile unsigned int *pciconfigdata; |
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#define PCI_ACCESS_READ 0 |
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#define PCI_ACCESS_WRITE 1 |
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/*
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* Access PCI Configuration Register for VR4131 |
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*/ |
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static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg, |
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u32 * data) |
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{ |
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u32 bus; |
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u32 device; |
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bus = ((dev & 0xff0000) >> 16); |
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device = ((dev & 0xf800) >> 11); |
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if (bus == 0) { |
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/* Type 0 Configuration */ |
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*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc)); |
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} else { |
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/* Type 1 Configuration */ |
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*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1); |
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} |
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if (access_type == PCI_ACCESS_WRITE) { |
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*VR4131_PCICONFDREG = *data; |
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} else { |
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*data = *VR4131_PCICONFDREG; |
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} |
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return (0); |
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} |
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static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val) |
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{ |
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u32 data; |
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) |
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return -1; |
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*val = (data >> ((reg & 3) << 3)) & 0xff; |
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return 0; |
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} |
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static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val) |
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{ |
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u32 data; |
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if (reg & 1) |
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return -1; |
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) |
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return -1; |
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*val = (data >> ((reg & 3) << 3)) & 0xffff; |
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return 0; |
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} |
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static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg, |
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u32 * val) |
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{ |
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u32 data = 0; |
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if (reg & 3) |
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return -1; |
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) |
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return -1; |
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*val = data; |
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return (0); |
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} |
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static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val) |
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{ |
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u32 data = 0; |
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) |
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return -1; |
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data = (data & ~(0xff << ((reg & 3) << 3))) | (val << |
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((reg & 3) << 3)); |
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if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) |
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return -1; |
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return 0; |
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} |
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static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val) |
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{ |
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u32 data = 0; |
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if (reg & 1) |
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return -1; |
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data)) |
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return -1; |
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data = (data & ~(0xffff << ((reg & 3) << 3))) | (val << |
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((reg & 3) << 3)); |
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if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) |
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return -1; |
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return 0; |
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} |
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static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val) |
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{ |
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u32 data; |
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if (reg & 3) { |
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return -1; |
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} |
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data = val; |
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if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data)) |
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return -1; |
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return (0); |
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} |
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/*
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* Initialize VR4131 PCIU |
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*/ |
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static void vr4131_pciu_init(void) |
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{ |
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/* PCI clock */ |
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*VR4131_PCICLKSELREG = 0x00000002; |
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|
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/* PCI memory and I/O space */ |
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*VR4131_PCIMMAW1REG = 0x100F9010; |
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*VR4131_PCIMMAW2REG = 0x140FD014; |
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*VR4131_PCIMIOAWREG = 0x160FD000; |
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/* Target memory window */ |
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*VR4131_PCITAW1REG = 0x00081000; /* 64MB */ |
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*VR4131_PCITAW2REG = 0x00000000; |
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*VR4131_MAILBAREG = 0UL; |
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*VR4131_PCIMBA1REG = 0UL; |
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*VR4131_PCITRDYREG = 0x00008004; |
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*VR4131_PCIENREG = 0x00000004; /* PCI enable */ |
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*VR4131_COMMANDREG = 0x02000007; |
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} |
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/*
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* Initialize Module |
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*/ |
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void init_vr4131_pci (struct pci_controller *hose) |
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{ |
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hose->first_busno = 0; |
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hose->last_busno = 0xff; |
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vr4131_pciu_init (); /* Initialize VR4131 PCIU */ |
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/* PCI memory space #1 */ |
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pci_set_region (hose->regions + 0, |
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0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM); |
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/* PCI memory space #2 */ |
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pci_set_region (hose->regions + 1, |
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0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM); |
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/* PCI I/O space */ |
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pci_set_region (hose->regions + 2, |
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0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO); |
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/* System memory space */ |
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pci_set_region (hose->regions + 3, |
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0x00000000, |
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0x80000000, |
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0x04000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
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|
||||
hose->region_count = 4; |
||||
|
||||
hose->read_byte = vr4131_pci_read_config_byte; |
||||
hose->read_word = vr4131_pci_read_config_word; |
||||
hose->read_dword = vr4131_pci_read_config_dword; |
||||
hose->write_byte = vr4131_pci_write_config_byte; |
||||
hose->write_word = vr4131_pci_write_config_word; |
||||
hose->write_dword = vr4131_pci_write_config_dword; |
||||
|
||||
pci_register_hose (hose); |
||||
|
||||
hose->last_busno = pci_hose_scan (hose); |
||||
|
||||
return; |
||||
} |
Loading…
Reference in new issue